JPH0583564A - Image processor - Google Patents

Abstract

PURPOSE:To provide the image processor accelerating an image processing by always fixing time for encoding one pixel block almost equal to one time of scanning. CONSTITUTION:A buffer memory 105 stores image data orthogonally transformed by a discrete cosine transformation(DCT) circuit 101 and quantized by a quantizer (Q) 103. First of all, an address value obtained by passing the output of a zig-zag address generator 106 through an address inverter circuit 107 is supplied through a switch 108 to the buffer memory 105, and the data in the buffer memory 105 are read out by reverse scan from a high-order address to a low-order address. When a significant coefficient detection circuit 109 detects the first significant coefficient of the read data, the output of the zig-zag address generator 106 is initialized to '00' and the switch 108 is changed over to a side (b) and changed to forward scan so as to start encoding. The encoding is finished at the address where the first significant coefficient appears in backward scan.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device for compressing an image by orthogonal transformation.

[0002]

2. Description of the Related Art The memory capacity required to store a halftone image such as a photograph in a memory is (number of pixels) × (number of gradation bits), which is enormous for storing a high-quality color image. Memory capacity was required. For this reason, various information amount compression methods have been proposed, and the amount of memory is reduced by storing the information amount in the memory after compressing the information amount.

FIG. 9 shows JPEG (Joint Photographic) as an international standard for color still image coding.
c Experts Group) encoding method of a baseline system (basic method) proposed by Yasuda: "International standardization of color still image coding", Journal of Image Electronics Engineers, Vol. 18, No. 6, pp. 398- 409, 198
It is a block diagram which shows the structure of 9).

In FIG. 9, the halftone image data input from the input terminal 1 is 8 × in the block circuit 2.
It is cut out into a block of 8 pixels (hereinafter referred to as “pixel block”), orthogonally transformed by a discrete cosine transform (hereinafter referred to as “DCT”) circuit 17, and a transform coefficient is stored in a quantizer (hereinafter referred to as “Q”) 40. Supplied. In Q40, linear quantization of the transform coefficient is performed according to the quantization step information applied by the quantization table (hereinafter referred to as "Q table") 41. Among the quantized transform coefficients, the DC coefficient is calculated by the predictive coding circuit (hereinafter referred to as “DPCM”) 42.
The difference (prediction error) from the DC component of the previous pixel block is calculated and supplied to the one-dimensional Huffman coding circuit 43.

FIG. 10 is a block diagram showing the detailed structure of the DPCM 42. The DC coefficient quantized by Q40 is applied to the delay circuit 53 and the subtractor 54. The DC coefficient input to the delay circuit 53 is delayed by the time required for the DCT circuit 17 to calculate one pixel block. Therefore,
The DC coefficient of the previous pixel block is supplied from the delay circuit 53 to the subtractor 54, and the subtractor 54 outputs the difference (prediction error) between the DC coefficient of the current pixel block and the DC coefficient of the previous pixel block.
(Since the previous pixel block value is used as the prediction value in this prediction coding, the prediction coding circuit is configured by the delay circuit as described above.) The one-dimensional Huffman coding circuit 43
The prediction error signal supplied from the DPCM 42 is variable length coded according to the DC Huffman table 44, and the multiplexing circuit 5
Supply DC Huffman code to 1.

On the other hand, the AC coefficient (coefficients other than the DC coefficient) quantized in Q40 is zigzag scanned by the scan coefficient conversion circuit 45 in order from the low-order coefficient, as shown in FIG. 46. The significant coefficient detection circuit 46 determines whether the quantized AC coefficient is "0" or a significant coefficient other than "0", and when it is "0", supplies a count-up signal to the run length counter 47, and Increases the value by +1. When the AC coefficient is a significant coefficient other than "0", the reset signal is supplied to the run length counter 47, the counter value is reset, and the AC coefficient is supplied to the grouping circuit 48.

The run length counter 47 is a circuit for counting the run length of "0", and supplies the number NNNN of "0" existing between the significant coefficient and the next significant coefficient to the two-dimensional Huffman coding circuit 49. .. In the grouping circuit 48, the AC coefficient is divided into the group number SSSS and the additional bit shown in FIG. 12, and the group number SSSS is divided into the Huffman coding circuit 49.
Then, the additional bit is supplied to the multiplexing circuit 51.

The two-dimensional Huffman coding circuit 49 performs variable length coding on the supplied run length NNNN of "0" and the group number SSSS of the significant coefficient in accordance with the AC Huffman code table 50, and causes the multiplexing circuit 51 to perform AC Huffman coding. Supply the code. In the multiplexing circuit 51, D for one pixel block
The C Huffman code, the AC Huffman code, and the additional bit are multiplexed, and the compressed image data is output from the output terminal 52.

Therefore, it is possible to reduce the image memory capacity by storing the compressed image data output from the output terminal 52 in the memory and expanding it by the reverse operation at the time of reading. Generally, in a halftone image such as a photograph input by using an image scanner, significant coefficients are likely to be concentrated in the low range of an orthogonally transformed block such as DCT, and the high range is often "0". The variable length coding operation described above is executed until the last significant coefficient that appears when the AC coefficient of the block is zigzag scanned. Therefore, as the high-order AC coefficients are all “0” and the last significant coefficient appears in the lower order, the compression by the variable length coding is performed more efficiently.

[0010]

However, the image processing in the above conventional example has the following problems. It is difficult to complete the variable length coding of the AC coefficient by performing the zigzag scan shown in FIG. 11 once. This is because it is not possible to determine whether the significant coefficient that appears in one zigzag scan scan is the last significant coefficient.

Therefore, conventionally, zigzag scanning is performed twice, the last significant coefficient is detected in the first zigzag scanning, and encoding is performed up to the last significant coefficient detected in the second zigzag scanning. It was Therefore, there is a drawback that high-speed encoding cannot be expected and image processing becomes slow.

[0012]

SUMMARY OF THE INVENTION The present invention is intended to solve the above problems, and has the following structure as one means for solving the above problems. An image processing apparatus for performing image compression by orthogonal transformation, comprising storage means for storing orthogonal transformation coefficients, address inverting means for inverting each bit of an address value obtained from the address generating means, and the address generating means. And an address value obtained from the address inverting means to the storage means.

[0013]

With the above structure, it is possible to provide an image processing apparatus capable of high-speed encoding and fast image processing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the drawings.

[0015]

[First Embodiment] FIG. 1 is a block diagram showing a configuration example of the first embodiment. An object of the present invention is to use AC among the orthogonal transform coefficients.
Since the coefficient coding is performed at high speed, the DC coefficient coding method is the same as the conventional method. Therefore, in FIG. 1, only the configuration example required for encoding the AC coefficient is shown, and details of the configuration required for encoding the DC coefficient are omitted.

In FIG. 1, 100 is a block circuit,
101 is a DCT circuit, 102 is a Q table, 103 is Q, 104 is a scan conversion unit, 105 is a buffer memory, 106 is a zigzag address generation circuit, 107 is an address inversion circuit, 108 is an address switching switch, and 109 is a significant coefficient detection circuit. , 110 is a run length counter, 111 is a grouping circuit, 112 is a two-dimensional Huffman coding circuit, 113 is an AC Huffman table, 114 is a multiplexing circuit, 115 is a DC Huffman coding unit, 116 is an output terminal, 117 is an input It is a terminal.

2 to 7 are views for explaining the operation of FIG. 1. FIGS. 2, 3 and 5 to 7 are schematic diagrams of the buffer memory 105 and a scan state of the buffer memory 105, and FIG. FIG. 6 is a diagram showing the order of scanning addresses in the buffer memory 105. The halftone image data input from the input terminal 117 is cut out into pixel blocks of 8 × 8 pixels in the block converting circuit 100, subjected to orthogonal transform in the DCT circuit 101, and the transform coefficient is supplied to Q103.

At Q103, linear quantization of the transform coefficient is performed according to the quantization step information applied by the Q table 102. Among the quantized transform coefficients, the DC coefficient is the DC Huffman coding unit 115 and has the same configuration as the conventional one.
Encoded in the method. On the other hand, the AC coefficient is sent to the scan conversion unit 104 and stored in the buffer memory 105 in the scan conversion unit 104.

Conventionally, the AC coefficient stored in the buffer memory 105 is read according to the address value output from the zigzag address generator 106, and the A coefficient is read in the order shown in FIG.
The C coefficient was output. In the present embodiment, the address output from the zigzag address generator 106 or the address obtained by inverting each bit of the address by the address inverting circuit 107 is selected by the switch 108 and the buffer memory 105 is selected.
Apply to.

Therefore, when the switch 108 is connected to the a side, the AC coefficient is read from the buffer memory 105 while zigzag scanning in the reverse direction from the high band to the low band as shown in FIG. Switch 108 is b
When it is connected to the side, as shown in FIG. 3, from the low range to the high range, while zigzagging in the forward direction, A
The C coefficient is read from the buffer memory 105.

In the conventional example, as shown in FIG. 11, the start of scanning starts from the address immediately to the right of the DC component, whereas in the present embodiment, it starts from the address corresponding to the DC component. FIG. 4 is a diagram for explaining that the scan start of this embodiment is an address corresponding to the DC component. The addresses shown in FIG. 4 represent the positions of the 8 × 8 blocks shown in FIGS. 2 and 3 by the two-digit numbers 0 to 7. The upper digit of the address represents the horizontal direction, and the low side of the horizontal spatial frequency is "0" and the high side of the horizontal spatial frequency is "7". The lower digit of the address represents the vertical direction, and the low side of the vertical spatial frequency is "0" and the high side of the vertical spatial frequency is "7". For example, the address of the DC component is represented by "00", and the address immediately to the right of the DC component is represented by "10".

As shown in FIG. 4, the scanning in the conventional example starts from the address "10", proceeds to "01" and "02", and ends at "77", whereas the reverse direction of the present embodiment. In Sukiyan, it is necessary to start from address "77". Therefore, the address generator needs to generate an address from "00" which is the bit of "77" inverted, and the forward scan in this embodiment is the address "00".
It starts from "10", "01", "02", and ends at "77".

When the AC coefficient is read from the buffer memory 105 by the reverse scan as described above,
Usually after the output of some "0" s, the first significant coefficient appears. The first significant coefficient that appears in the backward scan is
Since it becomes the last significant coefficient in forward scan, up to the address where the first significant coefficient appears in backward scan,
It may be encoded by forward scan.

Therefore, when the first significant coefficient is detected by the significant coefficient detection circuit 109 during the backward scan, the significant coefficient detection circuit 109 causes the zigzag address generator 106 to operate.
Is initialized to "00" and the switch 108 is switched to the b side to change to the forward scan. Then, encoding of the AC coefficient is started. The coding of the AC coefficient ends at the address where the first significant coefficient appeared in the backward scan.

The above processing will be described in detail with reference to FIGS. In FIG. 5, the shaded area is a significant coefficient. Figure 6
6 shows a state in which the buffer memory 105 in the state shown in FIG. 5 is being scanned backward. FIG. 7 shows a state in which the buffer memory 105 in the state of FIG. 5 is forward scanned. When the buffer memory 105 is in the state shown in FIG. 5, the backward scan ends at the shaded area (address “12”) in FIG. 6, and then the forward scan in FIG.

As described above, the address of the buffer memory 105 to be scanned is constant at a total of 65 through the backward scan and the forward scan. That is, the time required to encode the AC coefficient of one pixel block is always constant,
It is approximately the same as the time for one zigzag skiyan. The encoding process after exiting the significant coefficient detection circuit is the same as that of the conventional example, and therefore will be briefly described.

The significant coefficient detection circuit 109 determines whether the quantized AC coefficient is "0", and when it is "0", supplies a count-up signal to the run length counter 110 and increments the counter value by +1. Let When the AC coefficient is a significant coefficient other than "0", the reset signal is sent to the run length counter 11
0, reset the counter value, and set A
The C coefficient is supplied to the grouping circuit 111.

The run length counter 110 is a circuit for counting the run length of "0", and supplies the number NNNN of "0" existing between the significant coefficient and the next significant coefficient to the two-dimensional Huffman coding circuit 112. .. In the grouping circuit 111, the AC
The coefficient is divided into a group number SSSS and additional bits, and the group number SSSS is divided into two-dimensional Huffman coding circuit 112.
Then, the additional bit is supplied to the multiplexing circuit 114.

The two-dimensional Huffman coding circuit 112 performs variable length coding on the supplied run length NNNN of "0" and the group number SSSS of the significant coefficient in accordance with the AC Huffman table 113, and the multiplexing circuit 114 executes the AC Huffman code. To supply. The multiplexing circuit 114 multiplexes the DC Huffman code for one pixel block sent from the DC Huffman processing unit 115, the AC Huffman code for one pixel block and the additional bit, and outputs compressed image data from the output terminal 116. To do.

In the description of this embodiment and FIGS. 3 and 7, an example in which the zigzag address generator 106 is initialized to "00" at the time of switching from the backward scan to the forward scan is shown. Initial value "1"
0 ”may be given. When the initial value“ 10 ”is given to the zigzag address generator 106, the address“ 00 ”of the buffer memory 105 is not subject to scanning, so that the coding of the AC coefficient can be further speeded up.

In the description of this embodiment and FIG. 1, the orthogonal transformation by the DCT of 8 × 8 pixels is used. However, this embodiment is not limited to this, and any block size can be used. It goes without saying that the orthogonal transformation can be performed by an arbitrary method. As described above, according to the present embodiment, the time required for encoding the AC coefficient of one pixel block is always constant and is substantially equal to the time required for one zigzag scan scan, and image processing capable of high-speed encoding is performed. It can be a device.

[0032]

[Second Embodiment] A second embodiment of the present invention will be described below. In the second embodiment, the same components as those in the first embodiment are designated by the same reference numerals and detailed description thereof will be omitted. FIG. 8 is a diagram showing a configuration example of the second embodiment according to the present invention. In the scan conversion unit 104 of the first embodiment shown in FIG. 1, the zigzag address generator 106 is replaced with a binary counter 203, and further decrement is performed. The circuit 202 and the zigzag conversion circuit 201 are added.

The operation of the scan conversion unit 104 of this embodiment will be described below. The AC coefficient sent from Q103 is converted into a forward scan order as shown in FIG. 11 by the zigzag conversion circuit 201, and then stored in the buffer memory 105. AC coefficient to store is 6
Since there are three AC coefficients, the AC coefficients are stored in addresses 0 to 62 of the buffer memory 105.

That is, the AC coefficient is stored in the buffer memory 105.
Before storing in the buffer memory 105, the zigzag conversion circuit 201 rearranges in the forward scan order and stores the rearranged AC coefficients in the buffer memory 105. Binary counter 2
When the AC coefficient is read from the buffer memory 105 using the value output from 03 as an address, the AC coefficient is output in the same order as when storing, that is, the same order as the forward scan.

When each bit of the output of the binary counter 203 is inverted by the address inverting circuit 107, and the output of the address inverting circuit 107 is decremented by the decrementing circuit 202, the AC coefficient is read from the buffer memory 105 by using the value as an address. , In reverse order of storage,
That is, the AC coefficient is output in the same order as the backward scan.

The decrement circuit 202 is necessary to correct the address obtained by the address inversion circuit 107. The value obtained by passing the initial value “0” of the binary counter 203 through the address inverting circuit 107 is “63”, while the last (63rd) AC coefficient is stored as described above. Is 62. That is, the value obtained from the address inversion circuit 107 and the buffer memory 1
Since the storage address of 05 has a difference of 1, this difference is corrected by the decrement circuit 202.

The operation other than the scan conversion unit 104 of this embodiment is the same as that of the first embodiment, and therefore its explanation is omitted. As described above, according to this embodiment, as in the first embodiment,
The time required to encode the AC coefficient of the pixel block is always constant, and is substantially equal to the time required for one zigzag scan, so that the image processing apparatus capable of high-speed encoding can be obtained. Furthermore, in this embodiment, a binary counter can be used instead of the zigzag address generator of the first embodiment, and the address generator can be simplified.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0039]

As described above, according to the present invention, it is possible to provide an image processing apparatus capable of high-speed encoding and fast image processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an embodiment according to the present invention.

FIG. 2 is a schematic diagram showing a state of reverse scanning of DCT coefficients in the present embodiment.

FIG. 3 is a schematic diagram showing a state of forward scanning of DCT coefficients in the present embodiment.

FIG. 4 is a diagram showing the order of scanning addresses in this embodiment.

FIG. 5 is a diagram showing an example of a state of occurrence of significant coefficients after DCT in the present embodiment.

FIG. 6 is a diagram showing an example of a backward scan range of DCT coefficients in the present embodiment.

FIG. 7 is a diagram showing an example of a forward scan range of DCT coefficients in the present embodiment.

FIG. 8 is a block diagram showing a configuration example of a second embodiment according to the present invention.

FIG. 9 is a block diagram showing a conventional configuration.

FIG. 10 is a diagram showing a configuration of a conventional predictive coding circuit.

FIG. 11 is a diagram showing a conventional forward scan of DCT coefficients.

FIG. 12 is a diagram illustrating a relationship between a conventional AC coefficient and a group number.

[Explanation of symbols]

 100 Blocking Circuit 101 DCT Circuit 103 Quantizer Q 104 Scanyan Transform Unit 105 Buffer Memory 106 Zigzag Address Generator 107 Address Inversion Circuit 108 Switch 109 Significant Coefficient Detection Circuit 110 Run Length Counter 111 Grouping Circuit 112 Two-Dimensional Huffman Coding Circuit 114 Multiplexing circuit 115 DC Huffman coding unit 201 Zigzag conversion circuit 202 Decrementing circuit 203 Binary counter

Claims (2)

[Claims] 1. An image processing apparatus for performing image compression by orthogonal transformation, comprising: storage means for storing orthogonal transformation coefficients; address inverting means for inverting each bit of an address value obtained from address generating means; An image processing apparatus comprising: a switching unit that supplies either the address value obtained from the address generating unit or the address value obtained from the address inverting unit to the storage unit. 2. The image processing apparatus according to claim 1, wherein the switching of the address value by the switching unit is performed by detecting a specific pattern from the output of the storage unit. apparatus.