JPH0328894A - Audio signal data processor - Google Patents

Abstract

PURPOSE:To simplify the whole circuit constitution by regarding output signal data of respective channels from a 2nd processing means as processing output data in either case, cascade processing or parallel processing. CONSTITUTION:The audio signal data processor is equipped with 1st and 2nd processing means DSP 1 and DSP 2 which have input ports IN1 and IN2 and output ports OUT1 and OUT2 of at least two channels and process audio signal data and a control means which controls processing operations of the 1st and 2nd processing means DSP 1 and DSP 2. Then the input audio signal data are supplied to the input port IN1 of one channel between the 1st and 2nd processing means DSP 1 and DSP 2, output data from the output port OUT1 of one channel of the 1st processing means DSP 1 is supplied to the input port IN2 of the other channel of the 2nd processing means DSP 2, and output audio signal data are obtained from the output ports OUT1 and OUT2 of both the channels of the 2nd processing means DSP 2. Consequently, when the signal data are converted into analog signals, timing signals need not be prepared individually and the circuit constitution is simplified.

Description

[Detailed description of the invention] Technical field The present invention relates to an audio signal data processing device.

BACKGROUND ART Audio signal data processing devices capable of controlling a sound field in order to create reverberation and a sense of presence in acoustic spaces such as concert halls and theaters in homes and cars are well known. This is shown in Japanese Patent No. 72615. In such a sound reproduction device,
A DSP (digital signal processor) is provided that performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. The DSP is capable of repeatedly performing arithmetic processing such as four arithmetic operations at high speed.

In the case where a plurality of DSPs are used to selectively perform either cascade processing or parallel processing, it has conventionally been necessary to provide an external changeover switch 50 as shown in FIG. That is, the human power signal data is supplied to the human power IN of the IDSP 51 and one fixed contact of the changeover/switch 50, and the output data from the output port OUT of the IDSP 51 is supplied to the ID/A converter (not shown). It is also supplied to the other fixed contact of the changeover switch 50. The data selected by the changeover switch 50 is
is supplied to the input port IN of the DSP52, and its second DS
The output data of P52 is sent from the output port OUT to the second D/A.
A transducer (not shown) is supplied. Therefore, when the selector switch 50 is switched to select the output data of the IDSP 51, cascade processing is performed, and when it is switched to select the input signal data, parallel processing is performed.

In the case of selectively performing cascade processing and parallel processing in this way, it has not only been necessary to provide a changeover switch, but also because cascade processing causes a time lag in the signal data output from each DSP. There is a problem in that it is necessary to separately prepare a timing signal when each data is converted into an analog signal, making the circuit configuration complicated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an audio signal data processing device that can perform cascade processing and parallel processing with a simple configuration without providing an external switch or timing adjustment circuit. The goal is to provide the following.

The audio signal data processing device according to the present invention includes first and second processing means each having an input port and an output port of at least two channels and processing audio signal data, and processing operations of the first and second processing means. control means for controlling the human-powered audio signal data.
and a second processing means, supplying output data from an output port of one channel of the first processing means to an input port of the other channel of the second processing means; It is characterized in that output audio signal data is obtained from each output port of both channels of the processing means.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the audio signal data processing apparatus which is an embodiment of the present invention shown in FIGS. 1 and 2, DSPs 1 and 2 having the same configuration are provided as first and second processing means. The input audio signal is sent to the DS via the A/D converter 41.
PI and 2 first person port IN, respectively.

The first output port OUT of the DSPI is connected to the input port N2 of the DSP2. DSP2 output port O
A D/A converter 43 is connected to UT+ via a digital filter 42, and a D/A converter 45 is connected via a digital filter 44 to the output port OUT2 of the DSP2.

In the DSPI, as shown in FIG. 2, input signal data from the first person IN+ is supplied to the person output interface 3a. A first data bus 4 is connected to the input/output interface 3a. Similarly, input signal data from the second person port IN2 is supplied to the input/output interface 3b, and the input/output interface 3b is connected to the first data bus 4. 1st data bus 4
Two signal data RAMs 5.6 are connected as data memories for storing audio signal data. Further, a buffer memory 7 is connected to the data bus 4, and the output of the buffer memory 7 is connected to one input terminal of a multiplier 8. A buffer memory 9 for holding coefficient data is connected to the other side of the multiplier 8, and a coefficient data RAMIO for storing a plurality of coefficient data is further connected to the buffer memory 9. ALU (computing unit)
Reference numeral 11 is provided for performing calculations such as accumulation of the calculation output of the multiplier 8, and the calculation output of the multiplier 8 is supplied to one human power. The output of an accumulator 12 that holds the calculation output of the ALUI 1 is supplied to the other human power. Further, the output of the accumulator 12 is connected to the data bus 4.

A memory control circuit 31 is connected to the signal data RAM 5. The memory control circuit 31 generates a control signal for controlling writing of data to a designated address in the RAM 5 and reading of data from the designated address. Signal data RAM
6 includes a memory control circuit 32 similar to the memory control circuit 31;
are connected via a switching circuit 33. Switching circuit 33
is controlled by the RAM 6 by a control signal from the memory control circuit 31.
Switching is performed so that data is written to the designated address and data read from the designated address. Further, a memory control circuit 34 similar to the memory control circuit 31 is connected to RAMIO.

The signal data RAM 6 is also connected to a second data bus 14 different from the first data bus 4. Specifically, as shown in FIG. 3, 3-state buffers 39a. 3 b are provided, and RA
Three-state buffers 40a and 40b are provided between M6 and the second data bus 14. The three-state buffers 39a, 39b, 40a, and 40b are individually turned on and off in response to command signals from a sequence controller 18, which will be described later. That is, when writing signal data from the first data bus 4 to the RAM 6, the 3-state buffer 39
a is turned on, and when reading signal data from the RAM 6 to the first data bus 4, the state buffer 39b is turned on. Similarly, when writing signal data from the second data bus 14 to the RAM 6, the 3-state buffer 40
a turns on and when reading signal data from the RAM 6 to the second data bus 14, the 3-state buffer 40b
turns on. The three-state buffers that are turned on in response to command signals are 39a, 39b. 40g, 40b
It is always one of these.

An interface 16 for data transfer with an external RAM 15a is connected to the data bus 14. external RAM
Reference numeral 15a denotes a delay memory provided for creating delayed signal data of audio signal data, and the larger the storage capacity, the more signal data with a longer delay time can be created. A memory control circuit 35 is provided to designate write and read addresses of the RAM 15a, and a delay time data RAM 17 is connected to the memory control circuit 35. Writing and reading of delay time data in the RAM 17 is controlled by a memory control circuit 38.

Interfaces 3a, 3b, 16, multiplier 8, buffer memories 7, 9, ALU II, accumulator 12,
The operations of the memory control circuits 31, 32, 34, 35, and 38 and the switching circuit 33 are controlled by the sequence controller 18. A program RAM 19 is connected to the sequence controller 18.
It operates according to the program written in it. A program counter 20 is connected to the program RAM 19,
Every time the count value of the program counter 20 is added, the instruction code of the step corresponding to the new count value is read from the program RAM 19 and supplied to the sequence controller 18. In addition, sequence controller 1
8 is connected to a register 21 that holds a plurality of commands from a microcomputer 24, which will be described later.

Program RAM 19 and register 21 are main bus 2
2 are connected to each other. A microcomputer 24 is connected to the main bus 22 via an interface 23. Also, the main bus 22 has a transfer buffer 26.
, 27 are connected. The transfer buffer 26 transfers coefficient data supplied from the microcomputer 24 to RAMI.
Temporarily held in order to be stored in O. The transfer buffer 27 temporarily holds delay time data supplied from the microcomputer 24 in order to be stored in the RAM 17.

The microcomputer 24 is a microprocessor, RA
It consists of an MSROM and an interface (both not shown). A keyboard 25 is connected to the microcomputer 24.

The keyboard 25 has a plurality of mode keys for specifying sound field modes such as Hall 1 and Hall 2 with different sound field characteristics, a frequency band setting key for the graphic equalizer, a level adjustment key, and a mute key ( A plurality of keys (not shown) are provided. The ROM of the microcomputer 24 stores, in addition to the DSP control program processed by the microcomputer 24 itself, a plurality of sequence control programs processed by the sequence controller 18, a plurality of coefficient data groups supplied to RAMIO, and the RAM1.
A plurality of delay time data groups for setting read addresses to be supplied to 7 are written in advance.

A clock generator 28 is provided in the DSPI, and clock pulses are sent from the clock generator 28 to the sequence controller 18 and the program counter 20.
supplied to Further, a clock pulse generated from the clock generator is supplied to the A/D converter 41 as a sampling timing signal.

Further, the audio signal data output from the interface 3a is transmitted to the first mute switch circuit 30a.
The signal is supplied to the output port OUT.

The audio signal data output from the interface 3b is supplied to the second output OUT2 via the mute switch circuit 30b. Mute switch circuit 30
The ON/OFF state of a and 30b is controlled by a command signal outputted from the sequence controller l8.

DSP2 is also configured similarly to DSPI.

An interface 23 of the DSP 2 is connected to a microcomputer 24. Also, DSP2 has external RAM.
An external RAM similar to 15a is connected.

In this configuration of DSPI and 2, in addition to the above-mentioned on/off instruction signals for the 3-state buffers 39a to 40b and the mute switch circuit 30g, the sequence controller 18 sends an instruction to transfer the coefficient data group held in the transfer buffer 26 to the RAMIO. Signal, transfer buffer 27
A command signal to transfer the address data group held in the RAM 17 to the RAM 17, a command signal to transfer the audio signal data from the interface 3 to the specified address of the signal data RAM 5.6, and read signal data from the specified address of the signal data RAM 5.6. command signal to read the coefficient data from the specified address of RAMIO and transfer it to the buffer memory 9, ALU
11 various arithmetic operation command signals, transfer command signals of the signal data held in the accumulator 12 to the designated address of the signal data RAM 5.6 or the buffer memory 7, and transfer command signals from the designated address of the signal data RAM 6 to the designated write address of the external RAM 15a. Transfer command signal, external RAM1
Transfer command signal from delay designated address 5a to designated address of signal data RAM 6, RAM 5.6 and external RAM
A command signal such as a reset command signal for initializing M15a is generated. These command signals are generated at appropriate timings according to commands from the microcomputer 24 or programs stored in the program RAM 19. Note that since commands from the microcomputer 24 are held in the command register 21, the sequence controller 18 monitors the contents of the command register 21 during operation according to the program and uses an interrupt operation to generate command signals in response to commands from the microcomputer 24. will occur. For example, the command held in the command register 21 is sent to the sequence controller 1 when a corresponding command signal is generated.
Cancelled by 8.

When any mode key on the keyboard 25 is operated, the microcomputer 24 determines whether or not the mode key is operated to specify a sound field mode different from the current sound field mode, as shown in FIG. 41). If you specify a sound field mode that is different from the current sound field mode, immediately
In order to turn off the mute switch circuits 30a and 30b of PI, 2 and put them in a mute state, a mute command is sent to D.
SPI,2 sequence controller 18 (step 42), the sequence control program and coefficient data group α1.corresponding to the operated key are generated. α2...
...αn and delay time data groups t1, t2...
Read tn from ROM and transfer it (step 43~
45). The sequence control program is sent to R via the DSPI,2 interface 23 and the main bus 22.
The data is transferred to AM19 and written by a program memory control circuit (not shown). The coefficient data group is transferred to the transfer buffer 26 via the interface 23 and the main bus 22. The delay time data group is transferred to the transfer buffer 27 via the interface 23 and the main bus 22. After transferring the coefficient data and delay time data to the transfer buffers 26 and 27 in this manner, the microcomputer 24 issues a data switching command to the sequence controller 18 of the DSPI 2 (step 46), and further issues an initialization command. (Step 47).

The sequence controller 18 generates a predetermined command signal to the memory control circuits 34 and 38 in response to the data switching command, and transfers the coefficient data group transferred to the transfer buffer 26.
Write to the specified area of AMIO, and transfer buffer 27
The delay time data group transferred to is written into a predetermined area of the RAM 17. Further, since the sequence controller 18 generates the above-described reset command signal to the memory control circuits 31, 32.35 in response to the initialization command, the memory control circuits 31, 32, and 35 cause the signal data RAM5.
6 and all storage areas of the external RAM 15a are written with "0".

After executing step 47, the mute switch circuit 30a,
A mute release command for turning on 30b and releasing the mute state is issued to the sequence controller 18 (step 48). That is, the mute switch circuit 30 is turned off only during the period when RAMI 0.17 and the data and programs within it are changed in order to switch the current sound field mode to another sound field mode. This is to prevent noise signals caused by changes in data or programs from being output.

When parallel processing is specified by operating the keyboard 25, the microcomputer 24 puts the first channel of DSPI and 2 into the data processing state between the input port IN and the output port OUT+, and
I and the second channel of 2, i.e., the input port}I
Data is passed between Nz and output port OUTz. On the other hand, if cascade processing is specified due to the operation of the keyboard 25, the microcomputer 24
The first channels of PI and 2 are in a data processing state, and the second channels of DSPI and 2 are also in a data processing state.

Next, data processing operations within the DSPI will be explained. The audio signal input to the A/D converter 41 is converted into digital audio signal data groups dl, d2, . The data group is supplied to the first data bus 4 via the interface 3a. The signal data group supplied to the data bus 4 is supplied to the RAM 5 or 6 and stored therein.

The signal data written in the RAM 6 of the DSPI is sequentially transferred to an output register (not shown) in the interface 16 via the data bus 14, and further written from the output register to a storage location specified by a write address in the external RAM 15a. This write address is controlled by the memory control circuit 35, and the number of addresses corresponding to the number of storage locations in the external RAM 15a is changed in a predetermined order for each transfer signal data. Signal data at a storage location specified by the read address in the external RAM 15a is read out and transferred to an input register (not shown) in the interface 16. The read address is RAM17
Since the delay time data stored in the memory control circuit 38 is read out and supplied to the memory control circuit 35, the write address is set as a reference according to the delay time data supplied in the memory control circuit 35.

In other words, R of one signal data is determined by the delay time data.
There is a delay time between the write timing to the AM 15a and the read timing. The signal data transferred and held in the input register in the interface 16 is transferred to the signal data RAM 6 by the data bus 14. By this transfer operation with the external RAM 15a, delayed audio signal data for sound field control is created.

On the other hand, the coefficient data read from RAMIO is supplied to the buffer memory 9 and held there. By properly timing the sequence controller 18, signal data is transferred from the RAM 5.6 or the accumulator 12 to the buffer memory 7, and the multiplier 8 transfers the signal data held in the buffer memory 7 and the signal data held in the buffer memory 9. Multiply the calculated coefficient data. For example, when performing a product-sum operation on the signal data group di, d2...dn and the coefficient data group a1, α2...αn, first, d1 is held and output to the buffer memory 7. , α1 is held and output to the buffer memory 9, α1・d1 is calculated in the multiplier 8, and the ALUI is applied to this α1・d1.
0 is added at I, and the result of the operation is held in the accumulator 12. Next, the buffer memory 7
d2 is held and outputted, α2 is held and outputted to the buffer memory 9, and when α2・d2 is calculated in the multiplier 8, α1・d1 is outputted from the accumulator 12, and α1 *d1+a2・d2 is calculated in the ALU 11. Ru. By repeating this, Σαt adε can be calculated. This Xαt”clL is output from the interface 3a.

Although such processing operations are shown for the first channel, they are also performed for the second channel in cascade processing. Data processing operations are similarly performed in the DSP2.

The data passing operation in parallel processing is to supply the signal data group output from the interface 3b to the interface 3b via the data bus 4.

Note that these operations are performed in response to command signals generated by the sequence controller 18 according to a sequence control program stored in the program RAM 19.

Furthermore, in the above embodiment, each DSP is provided with a clock generator, but the clock pulses from any one of the clock generators are supplied to each DSP and D/A converter. Also good.

Furthermore, in the embodiments described above, it is clear that the input audio signal is not limited to a monaural signal, but may also be a stereo audio signal.

FIG. 5 shows a connection when parallel processing and cascade processing are selectively performed by three DSPs 45 to 47. In this case, the DSPs 45 to 47 have three channels, INI to IN3, and output ports OUT, to OU.
Each has T3. In the case of parallel processing, the first channel is in a data processing state, and the second and third channels are in a data passing state. In the case of cascade processing, the first to third channels are placed in a data processing state.

Effects of the Invention As described above, in the audio signal data processing device of the present invention, human-powered audio signal data is supplied to the input port of one channel of each of the first and second processing means,
supplying output data from an output port of one channel of the first processing means to an input port of the other channel of the second processing means, and obtaining output audio signal data from each output port of both channels of the second processing means; things will be done. Therefore, it is possible to selectively perform either cascade processing or parallel processing without connecting a changeover switch to the outside. Furthermore, in both cascade processing and parallel processing, the output signal data of each channel from the second processing means becomes the processed output data, so that time lag in signal data between channels is prevented. Therefore, there is no need to adjust the timing when each signal data is converted into an analog signal, and the overall circuit configuration can be simplified. Furthermore, when the first and second processing means operate according to a program, there is an advantage that the same program can be shared between the first and second processing means.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram specifically showing the DSP in the device in FIG. 1, and FIG. 3 is a block diagram specifically showing a part of the DSP in FIG. 4 is a flow diagram showing the operation of the microcomputer in the DSP of FIG. 2, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a diagram showing conventional audio signal data. FIG. 2 is a block diagram showing a processing device. Explanation of symbols of main parts 1, 2.45 to 47, 51.52...DSP4, 14
...Data paths 5, 6...Signal data RAM 7,9...Buffer memory 8...Multiplier 10...Coefficient data RAM 11...ALU 12...Accumulator 17...Delay Time data RAM 18...Sequence controller

Claims (3)

[Claims] (1) first and second processing means each having an input port and an output port of at least two channels and processing audio signal data respectively; and a control means for controlling processing operations of the first and second processing means. providing input audio signal data to an input port of one channel of each of said first and second processing means, and providing output data from an output port of one channel of said first processing means to said second processing means;
An audio signal data processing apparatus characterized in that the audio signal data is supplied to the input port of the other channel of the processing means, and output audio signal data is obtained from each output port of both channels of the second processing means. (2) The audio signal data processing device according to claim 1, wherein the second processing means puts the input port and output port of the other channel into a data passing state in response to a command signal. (3) The one and the other channels of the first processing means and the one and the other channels of the second processing means each have the same function.
The audio signal data processing device as described.