JPH03288249A - Vme bus general-purpose interface circuit - Google Patents

Abstract

PURPOSE:To extremely reduce the cost of development and the circuit scale by providing a switch means which varies the timing to return a data acknowledge DTACK* to a VME bus master as well as the assignment of an I/O address. CONSTITUTION:An address setting switch 6 is provided together with a DTACK* timing setting switch 7, a decoder 8, and a shift register 9. Then it is not required to decide the decoding value, i.e., an I/O address at design of a circuit owing to use of the switch 6 and an address decoder 2. Furthermore the production timing of the DTACK* can be varied in the cycle of an SYSCLK in regard of the generation of the DTACK* by decoding the set value of the switch 7 via the decoder 8 and gating the output of the register 9 with the decoded value of the decoder 8. Thus a general-purpose interface circuit is transformed into a PLD or an LSI. Then the cost of development and the circuit scale can be extremely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a slave-side interface circuit in a VME bus system.

[Conventional technology]

Figure 3 shows, for example, the rVME system complete mask, Showa 6.
The conventional VME shown in "Published by CQ Publishing Co., Ltd. on June 1, 2013"
FIG. 2 is a block system diagram of a VME interface section in a bus slave (hereinafter simply referred to as "slave"). In the figure, 1 is a VME bus, 2 is an address decoder,
3 is a control signal generation circuit that generates a control signal for the internal circuit from a data transfer control line, 4 is a DTACK* generation circuit that returns a data acknowledge to the mask, and 5 is a bidirectional data hash buffer.

Next, the operation will be explained. When the address is asserted on VME hash 1 by the mask, the slave asserts the AS
When * is asserted, this is captured and the address
The address is decoded by the decoder 2 and checked to see if it is the own address. If it is its own address, the control signal generation circuit 3 uses the AM code (AM5-0) and data transfer control lines such as IACK* and LWORD* to determine whether or not the access should be a predetermined response. If the access is correct, DS1*
～Data bus using DSO* and WRITE* signals
Enable buffer 5. After this, DTACK*
The generation circuit 4 asserts DTACK* according to the response speed of the internal circuit of the slave, and negates it according to the RORA or ROAK option.

[Problem to be solved by the invention]

The VME interface circuit in a conventional slave is configured as described above, so when designing the system, it is necessary to
Since it is necessary to determine the O address and the timing of asserting DTACK* is fixed at the time of slave design, the address decoder and DTA
There were problems such as the need to modify the CK* generation circuit.

The present invention has been made in view of these points, and its purpose is to be relocatable in the address space of the VME, to be able to support slaves with varying response speeds, and to be able to be implemented as a PLD or LSI. The object of the present invention is to obtain a slave VME bus general-purpose interface circuit that can reduce the circuit scale.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a switch means that makes the assignment of I/O addresses and the timing of returning data acknowledgement DTACK* to the VME bus master variable.

[Effect]

The I/O address in the VME bus general-purpose interface circuit according to the present invention is arbitrarily changed by the switch means, and the timing of assertion of DTACK)k is also selected by the switch means. As a result, by converting the general-purpose interface circuit into a PLD or an LSI, both the development cost and the circuit scale can be significantly reduced compared to the conventional example.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a VME bus general-purpose interface circuit according to the present invention. In the figure, 6 is an address setting switch, 7 is a DTACK* timing setting switch, 8 is a decoder, and 9 is a shift register. In FIG. 1, the same or equivalent parts as in FIG. 3 are given the same reference numerals.

Next, the operation will be explained. VM configured as above
The I/O address decoding in the E interface circuit is exactly the same as the conventional example in terms of decoding timing and other operations, but by configuring the address setting switch 6 and address decoder 2 as shown in FIG.
There is no need to determine the decoded value, ie, the I/O address, at the time of circuit design.

Regarding the generation of DTACK*, the setting value of the timing setting switch 7 is decoded by the decoder 8, and the output of the shift register 9 is gated with the decoded value, thereby changing the timing of generating DTACK* to 5YS.
It can be made variable with the CLK cycle.

As described above, since the operation is exactly the same as that of the conventional VME interface circuit shown in Fig. 3 and can be shared, the PL
By converting to D or LSI, it is possible to realize a general-purpose VME interface circuit that can significantly reduce both development cost and circuit scale.

In addition, in the above embodiment, I/O address setting and DT
The example shown has a switch only for setting the ACK*assertion timing, but it is also possible to install a switch for the interrupter.
The status ID byte and interrupt level can be set with switches, and the general-purpose VME includes an increment button.
It may also be an interface circuit.

FIG. 2 is a block system diagram showing a second embodiment of the present invention. In the first embodiment, the common circuit of the VME interface circuit of only slaves was explained, but in the second embodiment, an incrementer 11 is further added, and in order to make this common, a status ID byte setting switch/
By providing the O and interrupt level setting switches 12, it is possible to realize a VME bus general-purpose interface circuit in the slave subsystem.

As a result, the common parts of the system are improved compared to the above embodiments, and the overall development cost can be further reduced.

〔Effect of the invention〕

As explained above, the present invention provides switch means that makes the assignment of I/O addresses and the timing of returning data acknowledgement DTACK* to the VME bus master variable, so that each slave responds to the I/O address. (2) ME interface circuits, which differ only in speed, can be made common by switching means, reducing the cost of system development, and reducing the slave circuit scale by converting to PLD or LSI.

[Brief explanation of drawings]

1 and 2 are block diagrams showing first and second embodiments of the present invention, and FIG. 3 is a block diagram showing a conventional VME interface circuit. 1...VME bus, 2...Address decoder, 3.
...Control signal generation circuit, 4...DTACK*
Generation circuit, 5... Data bus buffer, 6...
Address setting switch, 7... Timing setting switch, 8... Decoder, 9... Shift register. Diagram

Claims (1)

[Claims] In the I/O circuit that interfaces to the VME bus,
I/O address assignment and data acknowledgment DT
A VME bus general-purpose interface circuit characterized by comprising a switch means for making variable the timing of returning ACK* to a VME bus master.