JPH0328823U - - Google Patents

Info

Publication number
JPH0328823U
JPH0328823U JP8864589U JP8864589U JPH0328823U JP H0328823 U JPH0328823 U JP H0328823U JP 8864589 U JP8864589 U JP 8864589U JP 8864589 U JP8864589 U JP 8864589U JP H0328823 U JPH0328823 U JP H0328823U
Authority
JP
Japan
Prior art keywords
fader level
allocation
fader
channel
adjustment operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8864589U
Other languages
Japanese (ja)
Other versions
JPH0722903Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989088645U priority Critical patent/JPH0722903Y2/en
Publication of JPH0328823U publication Critical patent/JPH0328823U/ja
Application granted granted Critical
Publication of JPH0722903Y2 publication Critical patent/JPH0722903Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、この考案の一実施例を示すブロツク
図である。第２図は割当状態の一例を示す図であ
る。第３図は、第１図の表示器２６における表示
の具体例を示す図である。 Ｆ１〜Ｆ４……フエーダ操作子（フエーダレベ
ル調整操作手段）、２０ａ，２０ｂ……発光ダイ
オード（割当内容表示手段）、２２……メモリ（
フエーダレベル記憶手段）、２４……信号処理回
路（フエーダレベル制御手段）、２６ａ……チヤ
ンネルフエーダレベル表示、２６ｂ……割当内容
表示。 FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 is a diagram showing an example of an allocation state. FIG. 3 is a diagram showing a specific example of the display on the display 26 of FIG. 1. F1 to F4...Fader operator (fader level adjustment operating means), 20a, 20b...Light emitting diode (allocation content display means), 22...Memory (
24...signal processing circuit (fader level control means), 26a...channel fader level display, 26b...allocation content display.

Claims (1)

【実用新案登録請求の範囲】 (1) フエーダレベル調整可能なチヤンネルの数
よりも少ない数のフエーダレベル調整操作手段と
、 このフエーダレベル調整操作手段によるフエー
ダレベル調整操作を選択的に前記各チヤンネルに
割り当てる割当手段と、 この割当手段による割当内容を表示する割当内
容表示手段と、 前記各チヤンネルについて調整されたフエーダ
レベルを記憶するフエーダレベル記憶手段と、 各チヤンネルについて調整された値に各チヤン
ネルのフエーダレベルを制御するフエーダレベル
制御手段と を具備してなるフエーダ装置。 (2) 前記割当手段が割当内容をスクロール変化
させることを特徴とする請求項１記載のフエーダ
装置。[Claims for Utility Model Registration] (1) A fader level adjustment operation means whose number is smaller than the number of channels capable of adjusting the fader level, and an allocation means for selectively allocating the fader level adjustment operation by the fader level adjustment operation means to each of the channels. , an allocation content display means for displaying the allocation contents by the allocation means, a fader level storage means for storing the fader level adjusted for each channel, and a fader level control means for controlling the fader level of each channel to the adjusted value for each channel. A feeder device comprising: and . (2) The feeder device according to claim 1, wherein the allocation means changes the allocation contents by scrolling.
JP1989088645U 1989-07-28 1989-07-28 Fader device Expired - Lifetime JPH0722903Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989088645U JPH0722903Y2 (en) 1989-07-28 1989-07-28 Fader device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989088645U JPH0722903Y2 (en) 1989-07-28 1989-07-28 Fader device

Publications (2)

Publication Number Publication Date
JPH0328823U true JPH0328823U (en) 1991-03-22
JPH0722903Y2 JPH0722903Y2 (en) 1995-05-24

Family

ID=31638246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989088645U Expired - Lifetime JPH0722903Y2 (en) 1989-07-28 1989-07-28 Fader device

Country Status (1)

Country Link
JP (1) JPH0722903Y2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118526U (en) * 1979-02-15 1980-08-21
JPS5824210A (en) * 1981-08-05 1983-02-14 Arupain Kk Equalizer device
JPS61202917U (en) * 1985-06-11 1986-12-20
JPS6428524A (en) * 1987-07-23 1989-01-31 Hitachi Heating Appl Thermistor unit
JPH01143516A (en) * 1987-11-30 1989-06-06 Sony Corp Digital signal processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118526U (en) * 1979-02-15 1980-08-21
JPS5824210A (en) * 1981-08-05 1983-02-14 Arupain Kk Equalizer device
JPS61202917U (en) * 1985-06-11 1986-12-20
JPS6428524A (en) * 1987-07-23 1989-01-31 Hitachi Heating Appl Thermistor unit
JPH01143516A (en) * 1987-11-30 1989-06-06 Sony Corp Digital signal processor

Also Published As

Publication number Publication date
JPH0722903Y2 (en) 1995-05-24

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