JPH0353047U - - Google Patents
Info
- Publication number
- JPH0353047U JPH0353047U JP11553589U JP11553589U JPH0353047U JP H0353047 U JPH0353047 U JP H0353047U JP 11553589 U JP11553589 U JP 11553589U JP 11553589 U JP11553589 U JP 11553589U JP H0353047 U JPH0353047 U JP H0353047U
- Authority
- JP
- Japan
- Prior art keywords
- display
- clock
- channel
- time
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Circuits Of Receivers In General (AREA)
Description
第1図は本考案一実施例の要部回路ブロツク図
、第2図は同表示器の詳細図、第3図及び第4図
は表示例を示す図、第5図及び第6図は表示切換
えの動作を説明するフローチヤート図、第7図は
表示器周辺回路構成図、第8図はマイコンの表示
信号波形図、第9図は表示とセグメントデータと
の関係図である。
1……マイクロコンピユーター、3……セグメ
ントLED数字表示器、5……内蔵時計。
Fig. 1 is a main circuit block diagram of an embodiment of the present invention, Fig. 2 is a detailed view of the display, Figs. 3 and 4 are diagrams showing display examples, and Figs. 5 and 6 are displays. FIG. 7 is a flowchart explaining the switching operation, FIG. 7 is a diagram of the peripheral circuitry of the display, FIG. 8 is a waveform diagram of the display signal of the microcomputer, and FIG. 9 is a diagram of the relationship between display and segment data. 1...Microcomputer, 3...Segment LED numeric display, 5...Built-in clock.
Claims (1)
数字表示器を用いたチヤンネル表示装置において
、 該チヤンネル表示装置の内蔵時計の時刻合わせ
を指示する時刻合せ指示手段と、 前記時刻合せ指示に応じてチヤンネル表示から
時計表示に切替える表示切替手段と、 前記内蔵時計への表示時計内容を修正する時計
内容変更手段と、 前記時計表示からチヤンネル表示に復帰させる
表示復帰手段とを備えてなることを特徴とするチ
ヤンネル表示装置。[Claims for Utility Model Registration] A channel display device using a segmented numeric display that displays the currently selected channel, comprising: a time setting instruction means for instructing a built-in clock of the channel display device to set the time; and the time. A display switching means for switching from a channel display to a clock display in response to a setting instruction, a clock content changing means for modifying display clock content on the built-in clock, and a display return means for returning from the clock display to a channel display. A channel display device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11553589U JPH0353047U (en) | 1989-09-29 | 1989-09-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11553589U JPH0353047U (en) | 1989-09-29 | 1989-09-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0353047U true JPH0353047U (en) | 1991-05-22 |
Family
ID=31663862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11553589U Pending JPH0353047U (en) | 1989-09-29 | 1989-09-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0353047U (en) |
-
1989
- 1989-09-29 JP JP11553589U patent/JPH0353047U/ja active Pending
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