JPH0328805U - - Google Patents
Info
- Publication number
- JPH0328805U JPH0328805U JP8923389U JP8923389U JPH0328805U JP H0328805 U JPH0328805 U JP H0328805U JP 8923389 U JP8923389 U JP 8923389U JP 8923389 U JP8923389 U JP 8923389U JP H0328805 U JPH0328805 U JP H0328805U
- Authority
- JP
- Japan
- Prior art keywords
- series circuits
- resistor
- diodes
- connects
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Non-Reversible Transmitting Devices (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
本考案の他の実施例の回路図、第３図は従来の減
衰器の回路図、第４図は従来の減衰器を複数段に
構成した回路図である。
１……ハイブリツド、２……入力端子、３……
出力端子、４，４ａ〜４ｃ……抵抗体、５，５ａ
〜５ｃ……ＰＩＮダイオード、６，６ａ〜６ｃ…
…バイアス端子、７ａ，７ｂ……直流カツトコン
デンサ。
Figure 1 is a circuit diagram of one embodiment of the present invention, Figure 2 is a circuit diagram of another embodiment of the present invention, Figure 3 is a circuit diagram of a conventional attenuator, and Figure 4 is a circuit diagram of a conventional attenuator. It is a circuit diagram configured in multiple stages. 1...Hybrid, 2...Input terminal, 3...
Output terminal, 4, 4a to 4c...Resistor, 5, 5a
~5c...PIN diode, 6,6a~6c...
...Bias terminal, 7a, 7b...DC cut capacitor.
Claims (1)
他のアイソレーシヨンされた端子に、抵抗体とＰ
ＩＮダイオードの直列回路をそれぞれ接続し、こ
のＰＩＮダイオードに印加するバイアスに応じて
減衰を行うスイツチ型の減衰器において、前記抵
抗体とＰＩＮダイオードの直列回路は、異なる抵
抗値の抵抗体とＰＩＮダイオードからなる複数の
直列回路を並列に接続した構成とし、かつこれら
の直列回路に選択的に所要のバイアスを印加し得
るように構成したことを特徴とする減衰器。 Connect the resistor and P to the other isolated terminal of the hybrid that connects the input terminal and output terminal.
In a switch-type attenuator that connects series circuits of IN diodes and performs attenuation according to the bias applied to the PIN diodes, the series circuit of the resistor and the PIN diode has resistors and PIN diodes of different resistance values. 1. An attenuator characterized in that it has a configuration in which a plurality of series circuits consisting of the following are connected in parallel, and a required bias can be selectively applied to these series circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8923389U JPH0328805U (en) | 1989-07-31 | 1989-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8923389U JPH0328805U (en) | 1989-07-31 | 1989-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0328805U true JPH0328805U (en) | 1991-03-22 |
Family
ID=31638823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8923389U Pending JPH0328805U (en) | 1989-07-31 | 1989-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0328805U (en) |
-
1989
- 1989-07-31 JP JP8923389U patent/JPH0328805U/ja active Pending