JPS63153614U - - Google Patents

Info

Publication number
JPS63153614U
JPS63153614U JP4836087U JP4836087U JPS63153614U JP S63153614 U JPS63153614 U JP S63153614U JP 4836087 U JP4836087 U JP 4836087U JP 4836087 U JP4836087 U JP 4836087U JP S63153614 U JPS63153614 U JP S63153614U
Authority
JP
Japan
Prior art keywords
operational amplifier
resistor
input
circuit
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4836087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4836087U priority Critical patent/JPS63153614U/ja
Publication of JPS63153614U publication Critical patent/JPS63153614U/ja
Pending legal-status Critical Current

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Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の原理ブロツク図、第2図は本
考案の電圧制限回路の一実施例の回路構成図、第
3図は本考案の回路特性を説明する図、第4図は
本考案の他の実施例と特性を説明する図、第5図
は従来の回路特性を説明する図である。 図において、1は入力端子、2は出力端子、R
a,Rbは抵抗器、Icは演算増幅器、Dはダイ
オード、Dzは定電圧ダイオードである。
Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit configuration diagram of an embodiment of the voltage limiting circuit of the present invention, Fig. 3 is a diagram explaining the circuit characteristics of the present invention, and Fig. 4 is a diagram of the present invention. FIG. 5 is a diagram illustrating the characteristics of a conventional circuit. In the figure, 1 is an input terminal, 2 is an output terminal, and R
a and Rb are resistors, Ic is an operational amplifier, D is a diode, and Dz is a constant voltage diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力抵抗器Raが接続された演算増幅器Icの
入力端子1と該演算増幅器Icの出力端子2間に
抵抗器Rbと定電圧ダイオードDzとを直列接続
した帰還回路を接続してなることを特徴とする電
圧制限回路。
A feedback circuit having a resistor Rb and a constant voltage diode Dz connected in series is connected between the input terminal 1 of the operational amplifier Ic to which the input resistor Ra is connected and the output terminal 2 of the operational amplifier Ic. voltage limiting circuit.
JP4836087U 1987-03-30 1987-03-30 Pending JPS63153614U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4836087U JPS63153614U (en) 1987-03-30 1987-03-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4836087U JPS63153614U (en) 1987-03-30 1987-03-30

Publications (1)

Publication Number Publication Date
JPS63153614U true JPS63153614U (en) 1988-10-07

Family

ID=30869817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4836087U Pending JPS63153614U (en) 1987-03-30 1987-03-30

Country Status (1)

Country Link
JP (1) JPS63153614U (en)

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