JPH03285417A - Pulse output circuit - Google Patents

Abstract

PURPOSE:To suppress the distortion of an output waveform by supplying a voltage equal with an external terminal voltage through a balance resistor to the other side terminal of another switch element and varying the power supply voltage of a constant voltage circuit in a certain direction so as to cancel the external terminal voltage. CONSTITUTION:A pair of FET 10 and 11 which are mutually connected to the same constant current source 12, input pulse signals (a) and (b) which are mutually opposite, from a pulse generation source or the like at the respective gates. Therefore, the drains and sources of the FET 10 and 11 are alternately turned on/off corresponding to the levels of the pulse signals. As result, the pulse signal with an amplitude value A is supplied to a load circuit Rm connected to the drain of the FET 10. On the other hand, the voltage equal with an external terminal voltage Vt is supplied through a balance resistor Rb to the drain on the FET 11 side as well. Thus, even in the case it is not matching to the load circuit, the distortion in the waveform of the output pulse is small since a terminate resistor Rt absorbs reflected waves.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD OF THE INVENTION The present invention relates to a pulse output circuit used in a pattern generator or the like that outputs a high-speed pulse signal. <Prior Art> This type of pulse generator is required to be able to arbitrarily set the amplitude of the pulse signal and the DC component voltage (offset voltage) variably according to the characteristics of the connected load circuit. Further, in order to output high-speed pulses in the GHz band without waveform deterioration, the output connector is usually directly connected to a switching element such as a transistor that is turned on and off according to the level of the input pulse signal. Therefore, when using this pulse generator as an input signal source for an ECL circuit that requires a bias voltage of 12 volts on the ground side of the input termination resistor, or for a laser diode whose operating point is set by the bias voltage, the bias voltage Due to the influence of the voltage, the offset voltage of the output pulse signal differs from the set value. To solve this problem, there has been a conventional pulse output circuit in which the output of a constant voltage circuit 2 is connected to the drain of a FET (field effect transistor) 1 as a switching element via a coil L, as shown in Figure 4. . In this circuit, even if a voltage Vt (external termination voltage) exists on the ground side of the load circuit 3 connected to the drain of the FET 1, the offset voltage is forcibly maintained at a constant value by the constant voltage circuit 2. Therefore, it is not affected by the load circuit 3. However, in the conventional pulse output circuit as described above, if there is a mismatch in the load impedance, the reflected wave cannot be absorbed, and the pulse signal cannot be sufficiently transmitted to the load circuit 3. There is a problem that waveform distortion increases. Furthermore, it is difficult to stabilize the impedance of the coil L over a wide frequency range, and the influence of the coil L connected to the output line on the output waveform cannot be overlooked. An object of the present invention is to provide a pulse output circuit that solves this problem. Means for Solving the Problems> In order to solve the above problems, the pulse output circuit of the present invention includes a pair of pulse output circuits, each of which has one side terminal connected to a single constant current source, and which is turned on and off alternately by an input pulse signal. A pulse output circuit in which the other side terminals of the switch elements are each terminated with a predetermined resistor, and a pulse signal corresponding to an input pulse signal is directly output from the other side terminal of one switch element, and the power source is connected from the ground side of the predetermined resistor. A constant voltage circuit that supplies the voltage, a current detection circuit that detects the current flowing from the constant voltage circuit to a predetermined resistance, and an external termination voltage that is supplied to the ground side of the load circuit connected to the other side terminal of one switch element. A termination voltage detection circuit that detects the voltage based on the output of the current detection circuit, and an offset voltage that offsets the external termination voltage by varying the supply voltage of the constant voltage circuit to a predetermined resistance by the voltage detected by the termination voltage detection circuit. It includes a holding circuit and a balance resistor that is terminated at the other side terminal of the other switch element and supplies from the ground side a voltage equal to the external termination voltage detected by the termination voltage detection circuit. Therefore, when a load circuit whose ground side is supplied with an external termination voltage is connected to the other terminal of one switch element, this voltage is detected by the current detection circuit as a change in the current flowing through the specified resistance. A voltage equal to this external termination voltage is supplied to the other side terminal of the other switch element via the balance resistor, and the power supply voltage of the constant voltage circuit is varied in a direction to offset the external termination voltage. Embodiment of the present invention> Hereinafter, an embodiment of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram showing an embodiment of a pulse output circuit in which offset voltage and amplitude can be varied. In FIG. 1, 10 and 11 are a pair of FETs whose sources are connected to the same constant current 1i12, and opposite pulse signals from a pulse generation source are input to each gate. Therefore, the drain and source of the FETs 10 and 11 are alternately turned on and off depending on the level of the pulse signal. The constant current source 12 is formed so that the current IO can be varied in accordance with the set amplitude value A. The drains of FETl0111 are each terminated by a 50Ω termination resistor Rt, which is equal to a predetermined characteristic impedance used for high frequency signals. The drain of the FET 10 is directly connected to the output connector 13 so that it can be connected to an external circuit, and the drain of the other FET 11 is connected to a 50Ω balance resistor Rb5M. In addition, the termination resistor Rt and balance resistor MRI)
Contact Jt! The l side is grounded via a capacitor C in terms of high frequency. FIG. 2 shows a state in which one of the switch elements, FETIO, is off and the other FET 11 is on. Suppose that y is connected to the ground side of the load circuit Ill and the balance resistor Rb.
Assuming that a voltage t is supplied and a voltage Vx is supplied to the termination resistor Rt, the voltage at the connection point of Rt and R1, that is, the high level voltage V1 (offset voltage)
is, Vl = Vt + (Vx - vt) / 2 = (
Vx +Vt )/2 (however, Rt = R1 = R). This voltage 1 is equal to the offset setting value B, and Vt
In order to be independent of changes in Vx = -Vt
+2B -------- It is necessary that the relationship (1) always hold; for example, Vx may be controlled so that if yt decreases by 1 volt, Vx increases by 1 volt. Since it is difficult to directly detect the value of yt, the relationship between Vt and each 1i flow is determined. In FIG. 2, Rt and R1m1. :The flowing current I] is Ij=
<vx −vt )/2R. Also, considering the current on the FET 11 side that is on, (I2 + 13)R = Vx - Vt 13 = 12 - IO (Rt = Rb = R), and from these two equations, 12
= f (Vx - Vt)/2R] + <Io
/2). IO is the value 2 obtained by dividing the amplitude value A by the parallel resistance of Rt and Rb
Since it is A/R, the sum of the currents flowing through both termination resistors Rt

[X is IX=It+Iz = (Vx -Vt +A> /R, and by substituting the previous formula (1), lx = (2(-Vt +8) +A / R... (2) Therefore, the value of yt can be found using the laminar flow lx. Note that the input pulse is reversed, FET10 is turned on, and FET10 is turned on.
11 is turned off, the same relationship holds true because the circuit is symmetrical. Reference numeral 14 in FIG. 1 is a current detection circuit that detects this current
The signal is then converted to Vs/Rs (=IX) and output. 16 is a termination voltage detection circuit that calculates the external termination voltage (1) of the load circuit R11 from the output lx of the current detection circuit 14, and uses the offset setting value B and the setting amplitude value A to calculate the external termination voltage 1 of the load circuit R11.
The following equation is obtained by solving the equation for yt: Vt = (-RIx +
According to 28+A>/2, Vt is extracted by the controller 17 and supplied to the balance resistor Rb via the driver 18. Reference numeral 19 denotes a constant voltage circuit that supplies power from the ground side of the termination resistor Rt, and is composed of a voltage buffer 20 and a driver 21.
A voltage equal to the voltage VX is applied to two terminating resistors Rt,
Rt. 22 is an offset voltage holding circuit which calculates the detected external termination using the voltage yt and the offset setting value B according to the above-mentioned equation (1), and outputs the output voltage VX to the constant '14ri circuit 19; The value B is set to 2B by the adder 23, and the external termination voltage Vt is subtracted from this 2B by the subtracter 24 to obtain the voltage V that satisfies the relationship of the previous formula (1).
x is output to the constant voltage circuit 19. Two FETs of the pulse output circuit configured as above
10.11 gates (a) and (b) in Figure 3, respectively.
When the pulse signal shown in is input, the two FETs 10,
11 are turned on alternately, a pulse signal with an amplitude value A is supplied to the load circuit R11 connected to the drain of the FET 10, as shown in (C) of the figure. In (C) of the same figure, when the external termination voltage yt is zero, the supply voltage VX from the constant If pressure circuit 19 is 2B,
The offset layer pressure V] is equal to the offset setting value B. Further, when an external termination voltage of 12 volts used for biasing the ECL circuit is supplied, the supply voltage V× of the constant voltage circuit 19 is set so as to cancel out this 12 volts (2B+
2) The voltage increases by 2 volts, and the actual offset voltage Vj remains at the offset setting value B and does not change. Also, when the offset setting value B is varied, (
When the pulse waveform shown in 1 moves vertically in parallel and the amplitude value A is varied, a 'H' level voltage (offset voltage
1) is fixed at 8, the voltage vO at the "off" level will fluctuate up and down. Note that since a voltage equal to the external termination voltage Vt is also supplied to the drain of the FET 11 side via the balance resistor Rb, the two FETs 10 and 11 perform almost completely symmetrical switching operations, and there is no disturbance to the load circuit. Even in the case of matching, there is little disturbance in the waveform of the output pulse because the terminating resistor Rt absorbs the reflected wave. Other Embodiments of the Invention In the embodiments described above, analog arithmetic units were used in each part to control the external termination voltage Vt, but this does not define the present invention. Each part may be configured with a digital processor, or a transistor may be used as a switch element. Further, in the above embodiment, the terminating resistor Rt and the balance resistor Rb as the predetermined resistors were set to 50Ω, which is the characteristic impedance of the high frequency circuit, but these may be any value (although R↑=Rb is desirable). Also, the fruit 71! In the example, the "H" level voltage offset voltage of the pulse signal is used, but this does not limit the present invention, and it may be set as the intermediate voltage between the "H level" and "L" level, or the "L" level voltage offset voltage. Further, in the above embodiment, a pulse output circuit that can arbitrarily vary the offset voltage and amplitude has been described, but the present invention is also applicable to a fixed type pulse output circuit that cannot vary either or both of these. <Effects of the Present Invention> As explained above, the pulse output circuit of the present invention can be applied to a pair of switching elements each having one terminal connected to one constant current source. Terminate each with a specified resistance,
The external terminal voltage of the load circuit connected to the other side terminal of one switch element is detected based on the current flowing through this predetermined resistance, and the voltage of the constant voltage circuit is changed in a direction to cancel this voltage, and the voltage of the constant voltage circuit is changed in the direction of canceling this voltage. Since a voltage equal to the external termination voltage is supplied to the other side terminal of the side switch element via the balance resistor, the offset voltage of the pulse signal supplied to the load circuit can be adjusted to the desired level without being affected by the external termination voltage of the load circuit. can be maintained at the value of In addition, the switching operation of a pair of switching elements can be balanced by the voltage supplied through the balancing resistor, and since both terminals on the other side are terminated with a predetermined resistor, high-speed pulse signals can be processed without waveform distortion. It is possible to output in a small state.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. M2 is a circuit diagram for explaining the operation of a main part of the embodiment, and FIG. 3 is a waveform diagram showing the operation of the embodiment. FIG. 4 is a circuit diagram showing a conventional circuit. 10.11... FET, 12... Constant current source, 14... Current detection circuit, 16...
・Terminal voltage detection circuit, 19... Constant voltage circuit, 2
2...Offset voltage holding circuit, Rt...
...Termination resistor, Hb...Balance resistor, R1...Load circuit, yt...External termination '741:i.

Claims (1)

[Claims] The other side terminals of a pair of switching elements each having one terminal connected to one constant current source and turned on and off alternately in response to an input pulse signal are each terminated with a predetermined resistor, and the input pulse signal a pulse output circuit that directly outputs a pulse signal corresponding to the other side terminal of one switch element, the constant voltage circuit supplying power from the ground side of the predetermined resistor; a current detection circuit that detects a current flowing through the switch element; and a current detection circuit that detects an external termination voltage supplied to the ground side of a load circuit connected to the other side terminal of the one switch element based on the output of the current detection circuit. a termination voltage detection circuit; an offset voltage holding circuit that varies the supply voltage of the constant voltage circuit to the predetermined resistance by the voltage detected by the termination voltage detection circuit to offset the external termination voltage; and the other switch element. a balance resistor that is terminated at the other terminal of the terminal and supplies a voltage equal to the external termination voltage detected by the termination voltage detection circuit from the ground side.