IE902893A1 - Integrable transistor switching stage with adjustable¹switching threshold - Google Patents

Abstract

An integratable transistor switching stage with a switching threshold dependent on a predeterminable reference voltage value is formed by a CMOS invertor which is connected in series between two mutually complementary load-current field-effect transistors (Q1, Q2). The gate electrodes of the two load current field-effect transistors (Q1, Q2) are connected to one another and are supplied with a reference voltage (VREF). An adjustment range, in which the transfer characteristic of the transistor switching stage exhibits an advantageous variation, can be predetermined for the switching threshold by dimensioning the transistors.

Description

Siemens Aktiengesellschaft Integrable transistor switching stage with adjustable switching threshold The invention relates to an integrable transistor 5 switching stage in accordance with the preamble of Patent Claim 1.

In digital technology, transistor switching stages are also frequently used as signal level converters and serve, above all, to identify the binary value represented by an input signal level and to generate an output signal level provided for representing this binary value. In many instances, a signal level converter inverts the identified binary value, and thus further carries out a logic negator function in addition to the level conversion.

In order for a particular input signal level to be capable of being correctly identified with the greatest possible reliability, it is necessary for the switching threshold of the signal level converter to lie as accurately as possible in the middle between the voltage values of the signal levels of the input signal, which are assigned to the logic zero and one values.

For the purpose of implementing a signal level converter whose switching threshold can be adjusted to match a particular input signal, a switching stage is known which consists of a series connection of an N-channel MOS field effect transistor and a P-channel MOS field effect transistor to a centre tap serving as switching output. One of the two field effect transis30 tors, whose gate electrode is constructed as switching input, can be designated as control transistor, the other, to whose gate electrode a predeterminable reference voltage is connected, as load current transistor.

The load current transistor represents an ohmic resistance which varies as a function of the reference voltage value. Consequently, the intensity of the current through the control transistor depends upon the adjusted reference voltage, as a result of which the value of the input signal voltage, which effects changeover of the switching stage and is designated as switching threshold, is displaced towards more positive or more negative voltage values, depending upon the adjusted reference voltage value.

However, a higher current through the control transistor entails the disadvantage, because of the associated varying drain-source voltage, that the transit) fer characteristic of the switching stage becomes flatter, i.e. that the change in level at the switching stage output does not occur abruptly but gradually.

This fact, which throws up substantial problems, in particular in the case of input signals with a low signal-to-noise ratio, that is to say with a low voltage difference between the signal levels assigned to the zero and one values, makes plain the weaknesses of the known switching stage.

It is, therefore, the object of the present invention to develop a transistor switching stage according to the preamble of Patent Claim 1 in such a way that the switching threshold is variable at least within a predetermined region while retaining an optimum transfer characteristic.

This object is achieved according to the invention by means of the features specified in the characterizing part of Patent Claim 1.

The switching stage constructed according to the invention is based on a CMOS inverter which, viewed per se, as a consequence of the push-pull operating mode of its two complementary control FETs has a transfer characteristic which can be regarded as ideal, on the one hand, and can, by dimensioning of the proportions of the two control FETs, on the other hand, be set to a switching threshold which can be adjusted in the case of the known switching stage only by accepting an unfavourable transfer characteristic.

An additional advantage of the switching stage constructed according to the invention arises from the CMOS inverter, which by contrast with the known stages enables a lower power loss.

Also capable of being regarded as a further advantage is the fact that in view of the dimensioning of the further transistors additional degrees of freedom are created in the case of integration of the switching stage.

Advantageous developments of the invention follow from the sub-claims.

Using a further load current FET, which is connected to the particular other supply voltage potential, the switching threshold of the CMOS inverter can be displaced in both directions.

Such a switching stage offers three degrees of freedom in the dimensioning of the transistors. For one thing, the proportion between the two control FETs, with which the switching threshold is preadjusted in the case of an ideal transfer characteristic; further, the ratio between the two load current FETs, with which the switch20 ing threshold can be balanced with reference to the available region of the reference voltage; and moreover, the ratio of the magnitudes between load current and control FETs, with which a measure of the effect achievable by varying the reference voltage can be fixed.

Two illustrative embodiments are explained below in more detail with reference to the drawing, wherein FIG. 1 shows one circuit diagram each for the polarity variants of the known switching stage; FIG. 2 shows transfer characteristics for the known switching stage in both polarity variants; FIG. 3 shows a circuit diagram for a switching stage constructed according to the invention as a series connection; FIG. 4 shows transfer characteristics for the switching stage according to FIG. 3; and FIG. 5 shows a circuit diagram for a switching stage constructed according to the invention as a parallel connection.

FIG. 1 shows two circuit diagrams for the two polarity variants of the known switching stage. In the first variant N of the switching stage (left-hand circuit diagram), a load current transistor Ql, constructed as a P-channel MOS field effect transistor (abbreviated to P-channel MOSFET) is connected in series to a control transistor SI, constructed as an N-channel MOS field effect transistor, abbreviated to N-channel MOSFET. The two transistors Ql, SI are connected to one another at their drain electrodes D, this connection also serving as switching stage output A.

The load current transistor Ql is connected with its source electrode S to a voltage potential VCC (e.g. + 5 volt), and the control transistor Q2 is connected to a further voltage potential VEE (e.g. 0 volt), which is negative in comparison to the voltage potential VCC. The gate electrode G of the control transistor SI is constructed as switching stage input E, and a reference voltage VREF is connected to the gate electrode G of the load current transistor Ql.

The second variant P of the known switching stage (right-hand circuit diagram) differs from the first variant N only in that the control transistor SI is constructed as a P-channel MOSFET, and the load current transistor Ql is constructed as an N-channel MOSFET and is connected to the voltage potential VCC or the further voltage potential VEE.

FIG. 2 represents transfer characteristics for the first and second variant N, P of the known switching stage, from which characteristics the value of the output voltage UA can be read off with the aid, in each case, of two curves as a function of a particular input voltage UE.

In the first variant N, the switching threshold can be displaced between a first and second input voltage value SN1, SN2. If the source-gate voltage at the load current transistor Ql is low, the switching threshold is at the first input voltage value SN1; the associated transfer characteristic is relatively steep. With increasing source-gate voltage, the switching threshold is displaced towards the second input voltage value SN2, the associated transfer characteristic then being relatively flat.

An analogous behaviour holds for the second 5 variant P of the known switching stage, in which within increasing gate-source voltage at the load current transistor QI the switching threshold is displaced from a first input voltage value SP1 to a second input voltage value SP2.

FIG. 3 shows a circuit diagram of a switching stage constructed according to the invention, in which a CMOS inverter consisting of control transistors SI, S2 is connected in series between two load current transistors QI, Q2. The CMOS inverter consists of a control transis15 tor SI, constructed as an N-channel MOSFET, and a further control transistor S2, constructed as a P-channel MOSFET, which are connected to one another both via their drain electrodes D and also by gate electrodes G. The gate electrodes form the switching stage input E, and the drain electrodes form the switching stage output A.

The further control transistor S2 is connected with its source electrode S via the drain-source section of a load current transistor QI, constructed as a P-channel MOSFET, to a voltage potential VCC (e.g. + 5 volt), and the control transistor SI is connected via a further load current transistor Q2, constructed as an N-channel MOSFET, to a further voltage potential VEE (e.g. 0 volt), which is more negative than the voltage potential VCC. The gate electrodes of the load current transistors QI, Q2 are connected to one another, and a reference voltage VREF is applied to them.

The two load current transistors QI, Q2 can be regarded as correction elements, and act as resistors that can be adjusted in antiphase to one another by the reference voltage VREF. The more positive, for example, the reference voltage VREF becomes, the larger the resistance of the load current transistor QI becomes, and the smaller the resistance of the further load current transistor Q2 becomes. As a consequence, the switching threshold is displaced in the negative direction, that is to say towards the further voltage potential VEE.

By appropriate dimensioning of the control and load current field effect transistors SI, S2, Ql, Q2, it is possible to adjust a switching threshold that offers optimum conditions for an application to hand. The way in which the dimensioning of the transistors affects the switching threshold and the transfer characteristic of the switching stage is explained below in more detail in conjunction with FIG. 4.

FIG. 4 represents the transfer characteristics for switching thresholds lying at different input voltage values SO, Sil, S12, S21, S22.

A so-called nominal switching threshold for the 15 input voltage value SO is adjusted in the case of the switching stage constructed according to the invention by the ratio between the two control transistors Si, S2. The transfer characteristic associated with the nominal switching threshold has an optimally steep variation, if the two load current transistors are assumed to be shortcircuited.

The ratio between control and load current transistors determines the displacement region of the switching threshold that is possible by varying the reference voltage VREF. Using load current transistors Ql, Q2 that are constructed to be large by comparison with the control transistors SI, S2 (i.e. being provided with a low internal resistance), a variation in the reference voltage VREF has a weak effect on the displace30 ment of the switching threshold, but the transfer characteristic remains steep. The transfer characteristics associated with the input voltage values Sil or S12 illustrate this case in FIG. 4.

If the load current transistors Ql, Q2 are con35 structed to be smaller, a change in the reference voltage has a stronger effect on the displacement of the switching threshold, but the transfer characteristics then become flatter. The transfer characteristics associated with the input voltage values S21 and S22 are intended to illustrate this case.

In the case when the voltage range for balancing is available to a limited extent for the reference voltage VREF, the ratio between the two load current transistors Ql, Q2 can be varied, so that the nominal switching threshold is, for example, precisely adjusted when the reference voltage value lies in the middle of the voltage range available for forming the reference voltage.

FIG. 5 represents a circuit diagram for a switching stage constructed according to the invention with load current transistors connected in parallel to the control transistors of a CMOS inverter.

A control transistor SI constructed as an N-channel MOSFET, and a further control transistor S2, constructed as P-channel MOSFET, are connected to one another via their drain and gate electrodes D, G to form a CMOS inverter. The source electrode S of the control transistor SI is connected to the further voltage poten20 tial VEE (e.g. 0 volt), and the source electrode of the further control transistor S2 is connected to the more positive voltage potential VCC (e.g· 5 volt). Furthermore, a load current transistor Ql, constructed as P-channel MOSFET, and a further load current transistor Q2, constructed as an N-channel MOSFET, are connected to one another via their drain and gate electrodes D, G and connected with their source electrodes S to the voltage potential VCC or the further voltage potential VEE.

The gate electrodes G of the control transistors SI, S2 form the switching stage input E, and a reference voltage VREF is taken to the gate electrodes G of the load current transistors Ql, Q2. The switching stage output A is formed by means of a connection of the drain electrodes D between the control transistors SI, S2 and the load current transistors Ql, Q2.

In this switching stage, the two load current transistors Ql, Q2 can be regarded as current sources. If the reference voltage VREF is adjusted such that the currents through the two load current transistors Ql, Q2 cancel one another, the CMOS inverter is not influenced, and the nominal switching threshold is fixed by the ratio between the two control transistors SI, S2. The associated transfer characteristic is to be regarded as ideal in conformity with that of a CMOS inverter.

If the reference voltage VREF is varied to a more positive direction, the further load current transistor Q2 supplies a higher current than the load current transistor Ql. In order to compensate this, the further control transistor S2 must also supply a higher current than the control transistor SI. This causes the switching threshold to be displaced towards more negative values.

In an analogous way, the switching threshold is displaced in the positive direction when the reference voltage VREF approaches the value of the further voltage potential VEE. The shape of the transfer characteristics does not vary in the case of this switching stage, and remains ideal for all possible switching thresholds.

The influence of the reference voltage VREF on displacing the switching threshold can be fixed with the ratio between load current and control transistors. If the load current transistors are constructed relatively small, the switching threshold can be displaced only in a small range by varying the reference voltage. If the load current transistors, by contrast, are constructed to be relatively large, the switching threshold can be displaced in a large range, although in this case it is necessary to reckon with a higher power loss of the switching stage owing to a higher permanent current through the two load current transistors Ql, Q2.

Claims (5)

1. Patent claims

1. Integrable transistor switching stage for signal level conversion, consisting of a current path, which is formed from a load current field effect transistor (QI), connected with its drain-source section to a supply voltage potential, and two control field effect transistors (Si, S2), constructed in a mutually complementary fashion and connected in a known CMOS inverter circuit, the drain-source section of the control field effect transistor (SI) that is constructed in a fashion complementary to the load current field effect transistor (QI) serving as connection of the current path to a further supply voltage potential, the gate electrodes of the control field effect transistors (SI, S2) being constructed in common as switching stage input (E), and the connecting line of the drain-source sections of the control field effect transistors (SI, S2) forming the switching stage output (A), characterized in that the switching threshold of the transistor switching stage can be adjusted by applying a predeterminable reference voltage (VREF) to the gate terminal of the load current field effect transistor (QI).

2. Transistor switching stage according to Claim 1, characterized by a further load current FET (Q2), which is constructed in a fashion complementary to the load current FET (QI) and whose gate electrode (G) is connected to that of the load current FET (QI) and whose drain-source section is connected to the further supply voltage potential.

3. Transistor switching stage according to Claim 2, characterized in that the CMOS inverter is connected via one of the load current FETs (QI, Q2) in each case to the supply voltage potentials.

4. Transistor switching stage according to Claim 2, characterized in that the drain-source section of the load current FET (QI) is connected in parallel to that of the further control FET (S2), and that of the control FET (SI) is connected in parallel to that of the further load current FET (Q2). -10

5. A transistor switching stage according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings .