JPH03284848A - Silicon wafer - Google Patents
Silicon waferInfo
- Publication number
- JPH03284848A JPH03284848A JP8638190A JP8638190A JPH03284848A JP H03284848 A JPH03284848 A JP H03284848A JP 8638190 A JP8638190 A JP 8638190A JP 8638190 A JP8638190 A JP 8638190A JP H03284848 A JPH03284848 A JP H03284848A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- wafer
- nitride film
- silicon wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 33
- 229910052710 silicon Inorganic materials 0.000 title claims description 33
- 239000010703 silicon Substances 0.000 title claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 230000000694 effects Effects 0.000 claims abstract description 19
- 238000005247 gettering Methods 0.000 claims abstract description 16
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 68
- 239000010409 thin film Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 238000001556 precipitation Methods 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000007423 decrease Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 35
- 239000010410 layer Substances 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 6
- 239000002244 precipitate Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、エンハンスドゲッタリング効果を有するシ
リコンウェーハの改良に係り、裏面に減圧ＣＶＤで窒化
シリコン膜、ポリシリコン膜を順次成膜することにより
、ウェーハの反り量が小さく、かつイントリンシックゲ
ッタリング効果を備えたシリコンウェーハに関スる。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the improvement of silicon wafers having an enhanced gettering effect. The present invention relates to a silicon wafer that has a small amount of warpage and has an intrinsic gettering effect.
従来の技術
デイバイスプロセスでのゲッタリング手法の一つである
エンハンスドゲッタリングには、ウェーハの裏面にポリ
シリコン膜あるいは窒化シリコン膜の単層膜を成膜した
ものが知られている。2. Description of the Related Art Enhanced gettering, which is one of the gettering methods used in conventional technology device processes, is known in which a single layer of polysilicon film or silicon nitride film is formed on the back surface of a wafer.
このエンハンスドゲッタリング効果を有するシリコンウ
ェーハは、裏面に設けた膜応力により、ウェーハに反り
が発生し、デイバイスプロセスのフォトリソグラフィの
時に問題となる。In silicon wafers having this enhanced gettering effect, warpage occurs in the wafer due to film stress provided on the back surface, which poses a problem during photolithography in device processes.
すなわち、ポリシリコン膜の場合は、膜の引張り応力の
ために、シリコンウェーハの鏡面側が凹型に反りが発生
し、窒化シリコン膜の場合は、減圧ＣＶＤでの窒化シリ
コン膜では圧縮能力のためにシリコンウェーハの鏡面が
凸型に反りが発生し、プラズマＣＶＤでの窒化シリコン
膜では引張り応力のため、シリコンウェーハの鏡面が凹
型に反りが発生し、デイバイス・プロセス中に問題とな
る。In other words, in the case of a polysilicon film, the mirror surface side of the silicon wafer warps in a concave shape due to the tensile stress of the film, and in the case of a silicon nitride film, the silicon wafer warps in a concave shape due to its compressive ability. The mirror surface of the wafer is warped in a convex manner, and the silicon nitride film produced by plasma CVD is warped in a concave manner due to tensile stress, which causes problems during device processing.
この発明は、エンハンスドゲッタリング効果を有スるシ
リコンウェーハにおいて、反りの少すいシリコンウェー
ハの提供を目的としている。The present invention aims to provide a silicon wafer having an enhanced gettering effect and having less warpage.
また、この発明は、前述した薄膜によるゲッタリング効
果を、各膜のもつ特性を利用しさらに向上させ得る薄膜
を設けたシリコンウェーハの提供を目的としている。Another object of the present invention is to provide a silicon wafer provided with a thin film that can further improve the gettering effect of the thin film described above by utilizing the characteristics of each film.
発明の概要
この発明は、エンハンスドゲッタリング効果を有するシ
リコンウェーハの反り防止と、ゲッタリング効果の向上
を目的に、薄膜について種々検討した結果、裏面に減圧
ＣＶＤによる窒化シリコン膜、ポリシリコン膜を順次成
膜した２層膜構成とすることにより、薄膜による反りが
著しく減少し、かつ前記２層膜がイントリンシックゲッ
タリング効果（以下ＩＧ効果という）を有することを知
見し、この発明を完成した。Summary of the Invention The present invention has been developed to prevent warping of silicon wafers having an enhanced gettering effect and to improve the gettering effect. As a result of various studies on thin films, the present invention has been developed by sequentially applying a silicon nitride film and a polysilicon film to the back surface by low-pressure CVD. The present invention was completed based on the finding that warping caused by the thin film is significantly reduced by forming a two-layer film structure, and that the two-layer film has an intrinsic gettering effect (hereinafter referred to as the IG effect).
すなわち、この発明は、
裏面に減圧ＣＶＤによる窒化シリコン膜、ポリシリコン
膜を順次成膜した２層以上の薄膜を有し、イントリンシ
ックゲッタリング効果を備えたことを特徴とするシリコ
ンウェーハである。That is, the present invention is a silicon wafer characterized in that it has two or more thin films on the back surface of which a silicon nitride film and a polysilicon film are sequentially formed by low-pressure CVD, and has an intrinsic gettering effect.
また、この発明は、前記の構成において、窒化シリコン
膜厚みが０．０５〜０．１よ、ポリシリコン膜厚みが０
．５〜１．５−であることを特徴とするシリコンウェー
ハである。Further, in the above structure, the present invention has a silicon nitride film thickness of 0.05 to 0.1 and a polysilicon film thickness of 0.05 to 0.1.
．． It is a silicon wafer characterized in that it is 5 to 1.5-.
発明の構成
この発明によるシリコンウェーハは、その裏面に減圧Ｃ
ＶＤによる窒化シリコン膜、ポリシリコン膜を順次成膜
した２層以上の薄膜を有することを特徴としている。Structure of the Invention The silicon wafer according to the present invention is provided with a reduced pressure C on its back surface.
It is characterized by having two or more thin films formed by sequentially forming a silicon nitride film and a polysilicon film by VD.
かかる構成がシリコンウェーハの反りを低減できる機構
を説明すると、まず、ウェーハ裏面に、膜応力が圧縮応
力である減圧ＣＶＤによる窒化シリコン膜を成長させ、
その窒化シリコン膜の上に膜応力が引張応力であるポリ
シリコン膜を成長させることにより、シリコンウェーハ
に与える応力が緩和されシリコンウェーハの反り量が小
さくなる。To explain the mechanism by which this configuration can reduce the warpage of a silicon wafer, first, a silicon nitride film is grown on the back surface of the wafer by low pressure CVD in which the film stress is compressive stress.
By growing a polysilicon film whose film stress is tensile stress on the silicon nitride film, the stress applied to the silicon wafer is relaxed and the amount of warpage of the silicon wafer is reduced.
反りを低減できる窒化シリコン膜とポリシリコン膜の厚
みには、好ましいい相関関係があり、窒化シリコン膜厚
みが０．０５〜０．１μｍ、ポリシリコン膜厚みが０．
５〜１．５μｍであることが望ましい。There is a favorable correlation between the thickness of the silicon nitride film and the polysilicon film that can reduce warpage, and the thickness of the silicon nitride film is 0.05 to 0.1 μm, and the thickness of the polysilicon film is 0.05 to 0.1 μm.
The thickness is preferably 5 to 1.5 μm.
また、減圧ＣＶＤで窒化シリコン膜とポリシリコン膜を
交互に多数成膜する場合も同様効果を得ることができる
が、まず、シリコンウェーハに減圧ＣＶＤによる窒化シ
リコン膜を成膜する必要があり、多層の場合の全厚みは
、前記２層膜構成の全厚みを越えてもよい。A similar effect can also be obtained by alternately forming a large number of silicon nitride films and polysilicon films by low pressure CVD, but it is first necessary to form a silicon nitride film on a silicon wafer by low pressure CVD, and multilayer The total thickness in this case may exceed the total thickness of the two-layer membrane configuration.
シリコンウェーハの裏面の膜構造が、シリコンウェーハ
／窒化シリコン膜ｌポリシリコン膜ｌどなる場合に限り
、熱処理を施すと、シリコンウェーハの裏面層の１００
１００ｐ：み程度に、酸素析出物の増進が起り、高密度
の析出物が発生する。すなわち、この発明による２層膜
構成とすることにより、ジノコンウェーハに従来以上の
高密度の析出物によるＩＧ効果が与えられ、実施例に示
す如く著しいゲッタリング効果の向上がみられる。Only when the film structure on the back side of the silicon wafer is silicon wafer/silicon nitride film/polysilicon film/etc., 100% of the back side layer of the silicon wafer can be heated by heat treatment.
At about 100p, oxygen precipitates increase and high-density precipitates are generated. That is, by adopting the two-layer film structure according to the present invention, an IG effect is imparted to the Zinocon wafer due to the precipitates having a higher density than before, and as shown in the examples, a remarkable improvement in the gettering effect is observed.
ＩＧ効果を得るための熱処理方法は、１０００℃以上の
雰囲気に１時間以上保持することが必要であり、例えば
１０００℃であれば５時間以上、望ましくは１０時間以
上の熱処理が必要で、実施例に示す如く、１１５０℃×
４時間と、高温雰囲気であれば短時間保持が可能となる
ので、加熱条件を適宜選定する必要ある。The heat treatment method for obtaining the IG effect requires holding in an atmosphere of 1000°C or more for 1 hour or more. For example, if the temperature is 1000°C, heat treatment is required for 5 hours or more, preferably 10 hours or more. As shown, 1150℃×
Since holding for a short time of 4 hours is possible in a high-temperature atmosphere, it is necessary to select the heating conditions appropriately.
製造方法の一例を示すと、シリコンウェーハ製造工程の
メカノケミカルポリッシング（ＭＣＰ）加工前に、シリ
コンウェーハの全面に、減圧ＣＶＤにて窒化シリコン膜
を、例えば５００Ａ〜２０００！みで成膜し、その窒化
シリコン膜の上にポリシリコン膜を、例えば２００ＯＡ
−１５０００に享みで成膜した後、ジノコンウェーハの
鏡面となるべき表面側をＭＣＰ加工し、前記２層膜構成
を裏面側にのみ残し、その後洗浄を行ない、この発明に
よるシリコンウェーハに仕上げる。To give an example of a manufacturing method, before the mechanochemical polishing (MCP) process in the silicon wafer manufacturing process, a silicon nitride film is formed on the entire surface of the silicon wafer by low pressure CVD, for example, at a temperature of 500A to 2000A! For example, a polysilicon film of 200 OA is formed on the silicon nitride film.
- After forming a film at a temperature of 15,000 yen, MCP processing is performed on the front side of the Zinocon wafer that should become a mirror surface, leaving the two-layer film structure only on the back side, and then cleaning is performed to finish the silicon wafer according to the present invention. .
また、鏡面となるべき表面側に所要のマスキングを施し
て、裏面側にのみ成膜してもよく、この場合、ＭＣＰ加
工後にこの発明による前記２層膜構成に成膜してもよい
。Alternatively, the film may be formed only on the back side by applying necessary masking to the front side that should become a mirror surface, and in this case, the film may be formed into the above-mentioned two-layer film structure according to the present invention after MCP processing.
実施例
実施例１
５インチシリコンウェーハの裏面に、窒化シリコン膜、
ポリシリコン膜をそれぞれ単層で設けた場合の反り発生
量を測定した。Examples Example 1 A silicon nitride film,
The amount of warpage generated when each polysilicon film was provided as a single layer was measured.
また、窒化シリコン膜とポリシリコン膜の２層構成とし
たこの発明のシリコンウェーハの場合の反り発生量を測
定した。測定結果は、前記単層の場合と合わせて第１表
に示す。なお、表中の入厚みは全成膜厚みである。Further, the amount of warpage was measured in the case of a silicon wafer of the present invention having a two-layer structure of a silicon nitride film and a polysilicon film. The measurement results are shown in Table 1 together with the case of the single layer. Note that the thickness in the table is the total thickness of the film formed.
第１表に明らかなとおり裏面の膜が１層である場合、窒
化シリコン膜は１３μｍ〜２０μｍの鏡面側が凸型の反
りが発生する。ポリシリコン膜の場合は３０μｍ程の鏡
面側が凹型の反りが発生する。As is clear from Table 1, when the film on the back surface is one layer, the silicon nitride film has a convex warp of 13 μm to 20 μm on the mirror surface side. In the case of a polysilicon film, a concave warp of about 30 μm occurs on the mirror surface side.
ところが、この発明による２層構造にすることにより、
シリコンウェーハの反り量が、８〜１０μｍの鏡面側が
凹型タイプの低反りのシリコンウェーハが得られる。However, by creating a two-layer structure according to this invention,
A low-warpage silicon wafer with a concave mirror surface side and a warpage amount of 8 to 10 μm can be obtained.
実施例２
５インチシリコンウェー ハ（Ｎ（１００） ｐ ４〜
６Ω−ｃｍ。Example 2 5-inch silicon wafer (N(100) p 4~
6Ω-cm.
［Ｏｉｌ １５．５Ｘ１０ ａｔｏｍ／ｃｃ、 Ｃｓ
１．０Ｘ１０ ａｔｍ／ｃｃ）を用いて、種々条件で
成膜、熱処理（１１５０℃×４時間）を施した場合の裏
面成膜側への析出物状況を顕微鏡観察した。[Oil 15.5X10 atom/cc, Cs
1.0 x 10 atm/cc) under various conditions and subjected to heat treatment (1150° C. x 4 hours), and the state of precipitates on the back side where the film was formed was observed using a microscope.
第１図はシリコンウェーハの裏面に窒化シリコン膜とポ
リシリコン膜の２層構成としたものである。FIG. 1 shows a two-layer structure of a silicon nitride film and a polysilicon film on the back surface of a silicon wafer.
第２図は裏面に窒化シリコン膜を設けた場合で、
同図ａは窒化シリコン膜を成膜した後、さらにボッシリ
コン膜を設けた場合（本発明）、同図すは窒化シリコン
膜を成膜した後、さらにボッシリコン膜堆積条件による
アニール処理をした場合、
同図Ｃは窒化シリコン膜堆積条件によるアニール処理を
し、さらにポリシリコン膜堆積条件によるアニール処理
をした場合であ
る。Figure 2 shows a case in which a silicon nitride film is formed on the back surface, and figure a shows a case in which a silicon nitride film is further formed after forming a silicon nitride film (the present invention). After the film is formed, annealing treatment is performed under the conditions for depositing a silicon film.C in the figure shows a case where annealing treatment is performed under the conditions for depositing a silicon nitride film, and then annealing treatment is performed under the conditions for depositing a polysilicon film.
第３図は、シリコンウェーハの裏面に、窒化シリコン膜
ｌポリシリコン膜を成膜した後、所要の熱処理を施した
場合であり、これにのみシリコンウェーハの裏面層１０
０１１ｍ程の所まで７×１０７コ１ｃｍ２以上の析出物
が見られる
発明の効果
この発明の２層膜（シリコンウェーハ／窒化シリコン膜
ｌポリシリコン膜）構成としたシリコンウェーハの反り
量は、従来の１層膜時と比べ、４層ｍ−４層μｍ程の反
り量の低下がみられた。FIG. 3 shows a case in which a silicon nitride film and a polysilicon film are formed on the back surface of a silicon wafer, and then the required heat treatment is performed.
Effects of the invention: Precipitates of 7 x 107 cm2 or more were observed up to a distance of about 0.11m Compared to the case of a single layer film, a reduction in the amount of warpage by about 4 layers m - 4 layers μm was observed.
さらに、シリコンウェーハの裏面層の析出物も、１層膜
の場合に比べ、５Ｘ１０３コ／ｃｍ２から７ｘ１０７コ
／ｃｍ２以上へと析出物を著しく増加させることができ
、イントリンシックゲッタリング効果を備えたシリコン
ウェーハを容易に製造できる。Furthermore, the precipitates on the back layer of the silicon wafer can be significantly increased from 5 x 103 co/cm2 to more than 7 x 107 co/cm2 compared to the case of a single layer film, which has an intrinsic gettering effect. Silicon wafers can be manufactured easily.
第１図、第２図ａ、ｂ、ｃ、第３図はシリコンウェーハ
の縦断面の顕微鏡写真である。FIG. 1, FIG. 2 a, b, c, and FIG. 3 are microscopic photographs of longitudinal sections of silicon wafers.
Claims (1)
コン膜を順次成膜した２層以上の薄膜を有し、イントリ
ンシックゲッタリング効果を備えたことを特徴とするシ
リコンウェーハ。 ２ 窒化シリコン膜厚みが０．０５〜０．１μｍ、ポリ
シリコン膜厚みが０．５〜１．５μｍであることを特徴
とする請求項１記載のシリコンウェーハ。[Scope of Claims] 1. A silicon wafer characterized in that it has two or more thin films formed by successively forming a silicon nitride film and a polysilicon film on its back surface by low-pressure CVD, and has an intrinsic gettering effect. 2. The silicon wafer according to claim 1, wherein the silicon nitride film has a thickness of 0.05 to 0.1 μm and the polysilicon film has a thickness of 0.5 to 1.5 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8638190A JPH03284848A (en) | 1990-03-30 | 1990-03-30 | Silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8638190A JPH03284848A (en) | 1990-03-30 | 1990-03-30 | Silicon wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03284848A true JPH03284848A (en) | 1991-12-16 |
Family
ID=13885298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8638190A Pending JPH03284848A (en) | 1990-03-30 | 1990-03-30 | Silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03284848A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100409407C (en) * | 2002-09-25 | 2008-08-06 | 硅电子股份公司 | Two layer LTO backside seal for a wafer |
-
1990
- 1990-03-30 JP JP8638190A patent/JPH03284848A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100409407C (en) * | 2002-09-25 | 2008-08-06 | 硅电子股份公司 | Two layer LTO backside seal for a wafer |
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