JPH03284817A - Ferroelectric capacitor - Google Patents

Abstract

PURPOSE:To accumulate large charges by a small area, to avoid the series connection of parasitic capacitance, and to enable excellent ferroelectricity even when a ferroelectric layer, a spontaneous polarization axis of which is directed only in the surface direction, is used by mounting first and second electrodes filled into mutually opposed groove sections along the thickness direction of the ferroelectric layer through a ferroelectric substance. CONSTITUTION:The insides of a pair of groove sections 15a, 15b are filled with first and second electrodes 16a, 16b, and a plurality of capacitors having structure in which a ferroelectric layer 14 section between the groove sections 15a, 15b is held by the electrodes 16a, 16b are arranged to the ferroelectric layer 14. According to the constitution, large charges can be accumulated by a small area. Parasitic capacitance resulting from a low dielectric constant layer unavoidably generated between the ferroelectric layer 14 and a foundation when the ferroelectric layer 14 is deposited is not connected in series with ferroelectric capacitance, and a ferroelectric capacitor having excellent ferroelectric characteristics is acquired. Excellent ferroelectricity is displayed even when a ferroelectric layer, a spontaneous polarization axis of which is directed only in the surface direction is employed owing to structure in which an electric field is applied along the surface direction of the ferroelectric layer 14.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a ferroelectric capacitor.

(Prior art) Dynamic φ random access memory (DRAM)
2. Description of the Related Art In semiconductor integrated circuits such as those shown in FIG. For this reason, for example, in a 4M bit DRAM, a stack structure in which an electrode, a dielectric layer, and an electrode are laminated on a semiconductor substrate is used as a capacitor in a memory or cell, and a groove is dug in the substrate and a thin dielectric layer is placed in the groove. A three-dimensional structure such as a trench structure with embedded electrodes is used. However, it is expected that integration will further progress in the future, and the structure of memory cells is likely to become more and more complex.

For these reasons, it is being considered to simplify the structure of capacitors by using ferroelectric materials with a large dielectric constant as the dielectric film instead of the conventionally used silicon oxides and nitrides. . For example, the dielectric constant of lead zirconate titanate (PZT), which is a typical ferroelectric material, is 1000 or more, and in principle, it is possible to store charge in a small area even with a Brehner structure. Conventionally, a ferroelectric capacitor with such a Brener structure is shown in Fig. 35 (
Those shown in A) and (B) are known. That is, 301 in the figure is, for example, a p-type silicon substrate, and the substrate 3
A field oxide film 302 is formed on the surface of 01 to electrically isolate the element regions.

On the surface of the substrate 301 surrounded by the field oxide film 302, there are n''' type source and drain regions 303.30.
4 are formed electrically separated from each other.

A gate oxide film 305 is formed on the substrate 301 including the channel region between these source and drain regions 303 and 304.
A gate electrode 30 made of polycrystalline silicon, for example,
6 is formed. The entire surface of the substrate 301, including the field oxide film 302 and the gate electrode 306, has a
A first interlayer insulating film 307 made of in2 is coated. A contact hole 30B is opened in the interlayer insulating film 307 corresponding to a part of the source and drain regions 303 and 304. On the interlayer insulating film 307, a source electrode (not shown) and a drain electrode 309 made of polycrystalline silicon are connected to the source and drain regions 303 and 304 through the contact hole 308.
are provided for each. A first electrode 310a having a large area is formed at the other end of the drain electrode 309. The interlayer insulating film 307 including the source electrode and drain electrode 309 is coated with a second interlayer insulating film 311 made of, for example, SiO2. In a portion of this interlayer insulating film 311 corresponding to the first electrode 310a,
A hole 312 is opened, and the hole 312 is filled with a ferroelectric layer 313 made of PZT or the like. A second electrode 310b having a large area is provided on the second interlayer insulating film 311 including the ferroelectric layer 313, and the second electrode 310b has a large area.
A wiring 314 disposed on the second interlayer insulating film 311 is connected to 10b.

By the way, it is being considered to manufacture electrically erasable nonvolatile RAM using ferroelectric capacitors. This ferroelectric material takes advantage of the fact that it has a hysteresis characteristic between the electric field and polarization, and even if the voltage is returned to zero, the ferroelectric capacitor retains residual polarization depending on the direction of the applied voltage. . By making the direction of the charge remaining in the ferroelectric material correspond to "0°" and "1", it becomes possible to store digital information in the ferroelectric capacitor.

In the capacitor having the above-mentioned ferroelectric material, there is a relationship between the electric field E and the electric polarization P as shown in FIGS. 33 and 34. That is, FIG. 33 shows an E-P characteristic line observed below the Curie temperature (ferroelectric phase), and FIG. 34 shows an E-P characteristic line observed above the Curie temperature (paraelectric phase). As can be seen from FIG. 33, the nonvolatile RAM is used in a state below the Curie temperature (ferroelectric phase) indicating residual polarization. Furthermore, from FIGS. 33 and 34, it is seen that when the electric field increases beyond a certain level, the polarization P does not increase any further, a so-called saturation phenomenon of polarization. For this reason, in a ferroelectric capacitor, the capacitance is increased by reducing the distance between the electrodes that sandwich the ferroelectric layer, and the effect of accumulating a large amount of charge cannot be expected. Since the dielectric strength voltage is relatively low, it is desirable that the distance between the electrodes is not shorter than when silicon oxide or nitride is used.The power supply voltage used for integrated circuits is usually 5V to 3.3V.
Although it is expected that the distance between the electrodes of a ferroelectric capacitor will become even lower in the future, for the reasons mentioned above, the distance between the electrodes of a ferroelectric capacitor depends on the operating voltage, the threshold electric field of the ferroelectric (or the electric field at which polarization saturates), the dielectric strength voltage, etc. It should be determined from

In this way, in a ferroelectric capacitor, it is not necessarily a good idea to shorten the distance between the electrodes.

In order to increase the amount of charge accumulated in the ferroelectric capacitor, it is necessary to increase the electrode area A. For example, if a capacitor is made using a ferroelectric material with a residual polarization P3 of 0.3 C/m2 and a charge Q of 300 fC is to be stored in this capacitor, the electrode area A is 1.0 μm2.
is necessary. This means that when the Brehner type ferroelectric capacitor shown in FIG. 35 described above is applied, the area of the memory cell cannot be made any smaller.
There are limits to miniaturization.

In addition, in the planar type ferroelectric capacitor shown in FIG. 35 described above, when sputtering the ferroelectric layer 313, the ferroelectric layer 313 and the first electrode 310a, which is the base, are removed.
A low dielectric constant i region layer is inevitably formed at the interface. Therefore, such a ferroelectric capacitor has an equivalent circuit shown in FIG. 36, in which a parasitic capacitor C' caused by the single low dielectric constant layer is connected in series with the ferroelectric capacitor C.

As a result, the overall ferroelectric properties were reduced.

Furthermore, some ferroelectric materials have spontaneous polarization only with respect to fixed crystal axes. Therefore, a ferroelectric layer may be formed in which the spontaneous polarization axis of the crystal is oriented in the in-plane direction. When such a ferroelectric layer is used to construct a Brehner type capacitor as shown in FIG. 35, the electrodes 310a, 310
Since the spontaneous polarization of the ferroelectric layer 313 is not directed in the direction between b, there is a problem that it does not exhibit ferroelectricity.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problems of the conventional art. The present invention aims to provide a ferroelectric capacitor that maintains ferroelectricity by avoiding this, and also exhibits good ferroelectricity even when using a ferroelectric layer in which the axis of spontaneous polarization is oriented only in the plane direction. be.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a ferroelectric layer provided on a substrate, and an opening formed in the ferroelectric layer along the thickness direction of the ferroelectric layer. A groove filled with electrodes formed to face each other with a ferroelectric material in between, and first and second electrodes filled in the trench so as to face each other with the ferroelectric material in between. This is a ferroelectric capacitor that is characterized by:

Examples of the substrate include a silicon substrate.

Among the ferroelectrics mentioned above, ferroelectrics whose Curie temperature is sufficiently higher than room temperature (ferroelectrics in a ferroelectric phase at room temperature) can be used as recording media for nonvolatile ferroelectric memories, and ferroelectrics whose Curie temperature is lower than The dielectric (ferroelectric in the paraelectric phase) is DR
Can be used as a capacitor for AM memory cells. Lead zirconate titanate (PZT) is a typical ferroelectric material.
can be mentioned.

Examples of the electrode include aluminum, polycrystalline silicon, tungsten, platinum, and gold.

The grooves for exposing at least the two surfaces facing each other along the thickness direction of the ferroelectric layer include two columnar grooves that are opened parallel to each other at a certain distance from each other in the dielectric layer. , or a frame-shaped groove. When the latter groove is opened in the dielectric layer, a columnar object having four side surfaces in the thickness direction is formed within the groove.

Further, in the ferroelectric capacitor according to the present invention, the first
, has a structure in which the second electrode is filled in the groove portion with an insulating material interposed therebetween except for the contact portions facing each other along the thickness direction of the ferroelectric material.

Examples of the insulating material include low dielectric constant insulating materials such as silicon oxide, silicon nitride, alumina, and magnesia.

Further, the ferroelectric capacitor according to the present invention may have the following configurations depending on the connection between the first and second electrodes and external wiring.

(2) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; comprising opposing columnar grooves, and first and second electrodes filled in these grooves so as to face each other with the ferroelectric layer interposed therebetween;
The bottom of one of the grooves reaches a diffusion layer formed on the surface of the substrate, a first electrode filled in the groove is connected to the diffusion layer, and a second electrode filled in the other groove is connected to the diffusion layer. A ferroelectric capacitor in which an electrode is connected to wiring arranged on the surface side of the ferroelectric layer.

(2) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; and first and second electrodes filled in the groove so as to face each other with the ferroelectric material in between, the bottom of one of the grooves being connected to the substrate. A first electrode, which is located between the low dielectric constant insulating layers and connected to a diffusion layer of the substrate, is connected to the wiring, and a second electrode, which is filled in the other groove, is connected to the wiring. A ferroelectric capacitor in which an electrode is connected to wiring arranged on the surface side of the ferroelectric layer.

In the configurations (1) and (2) above, the bottom of the other groove is located in the low dielectric constant insulating layer, and the bottom surface of the second electrode filled in the groove is insulated with the low dielectric constant insulating layer. capacitor.

(2) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; comprising columnar grooves facing each other, and eleventh and second electrodes filled in these grooves so as to face each other with the ferroelectric material interposed therebetween;
The bottom of one of the grooves reaches the diffusion layer formed on the substrate, the first electrode filled in the groove is connected to the diffusion layer, and the bottom of the other groove is connected to the substrate and the diffusion layer. It reaches the wiring placed between the dielectric constant insulating layers,
A ferroelectric capacitor in which a second electrode filled in the groove is connected to the wiring.

(2) In the configurations (2) to (3) above, the surface of the ferroelectric layer is coated with another low dielectric constant insulating layer, and the ferroelectric layer is mutually ferroelectrically connected in the thickness direction through the low dielectric constant insulating layer. A ferroelectric capacitor in which columnar grooves facing each other with a body layer in between are opened, and first and second electrodes are filled in these grooves so that their upper ends protrude from the low dielectric constant insulating layer.

(2) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; a plurality of columnar grooves facing each other, and first and second electrodes filled in these grooves so as to face each other with the ferroelectric material interposed therebetween; The first and second electrodes are arranged so that two electrodes are interposed therebetween, and each first
The bottom of the groove filled with electrodes is made to reach the diffusion layer formed on the substrate, each first electrode is connected to the diffusion layer, and each second electrode is connected to a wiring arranged on the surface side of the ferroelectric layer. A ferroelectric capacitor characterized by common connection.

(2) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; a plurality of columnar grooves facing each other, and first and second electrodes filled in these grooves so as to face each other with the ferroelectric material interposed therebetween; The first and second electrodes are arranged so that two electrodes are interposed therebetween, and the bottom of the groove filled with each first electrode is made to reach a diffusion layer formed on the substrate to diffuse each first electrode. Connect to each layer,
allowing the bottom of the groove filled with each second electrode to reach the wiring disposed between the semiconductor substrate and the low dielectric constant insulating layer;
A ferroelectric capacitor in which each second electrode is commonly connected to the wiring.

Examples of the low dielectric constant insulating layer used in items (1) to (4) above include MgO.

(Function) According to the present invention, a ferroelectric layer provided on a substrate and an opening in the ferroelectric layer, for example, at least two surfaces facing each other along the thickness direction of the ferroelectric layer, are provided. By adopting a structure that includes grooves for exposure and first and second electrodes filled in these grooves so as to contact the two exposed surfaces of the ferroelectric material, a large A ferroelectric capacitor capable of storing charge can be obtained.

For example, it is assumed that a capacitor having a ferroelectric layer with a residual polarization of 0.3 C/m2 is manufactured and a capacitor that stores a charge of 300 fC is designed. in this case,
The electrode area of the capacitor is required to be 1,0 μm2. In order to realize such an electrode area with a conventional planar structure in which the upper and lower sides of the ferroelectric layer are sandwiched between electrodes, for example, i, ox t
, oμm in area, and the capacitor occupies a similar area of 1, OX 1.0μm.

On the other hand, in the ferroelectric capacitor according to the present invention, for example, as shown in FIG.
A ferroelectric layer 2 is formed, and in this ferroelectric layer 2, two grooves 3a and 3b with an opening area of 0, 5 × 0, 2 μm and a depth of 2.0 μm are formed at an interval of 0.1 μm. , these grooves 3a and 3b are filled with metal to form the first and second electrodes 4.
a, 4b, the effective electrode area is 1.0 μm2.

By adopting such a structure, the area occupied by the capacitor becomes 0.5×O, 5 μm, which is 1/4th of that of a capacitor having the same electrode area as the conventional brainer structure.
This makes it possible to keep the area within a certain area.

Further, a groove is opened in the ferroelectric layer on the substrate to expose at least two surfaces facing each other along the thickness direction of the ferroelectric layer, and the two exposed surfaces of the ferroelectric are formed in the groove. By filling the first and second electrodes so as to be in contact with the surface, parasitic effects caused by the low dielectric constant I layer that inevitably occur between the ferroelectric layer and the underlayer during deposition of the ferroelectric layer can be avoided. Since the capacitance: -7 is not connected in series with the ferroelectric capacitor but in parallel, a ferroelectric capacitor with excellent ferroelectric properties can be obtained.

Furthermore, according to the present invention, since the structure is such that an electric field is applied along the plane direction of the ferroelectric layer, even if a ferroelectric layer whose spontaneous polarization axis is oriented only in the plane direction is used, a good ferroelectric property can be obtained. It is possible to realize a ferroelectric capacitor that exhibits high properties.

Furthermore, by filling the trench with the first and second electrodes via an insulating film with a low dielectric constant, the insulating film can electrically isolate the capacitors and between the capacitor and the wiring. Therefore, it is possible to realize a capacitor array in which a large number of capacitors are arranged and integrated on the same substrate with fewer malfunctions and a smaller delay time due to stray capacitance. This is because the side surfaces and bottom surface of the electrode except for the top surface are embedded in the insulating film, so the area on the insulating film can be used as a wiring area. In this case, the first or second electrode of the capacitor is drawn out onto the insulating film, and it becomes possible to form a wiring serving as a common electrode with the electrode of another capacitor drawn out in the same way.

Furthermore, as explained in the above-mentioned sections 1 to 2, the first electrode of the first and second electrodes is connected directly or via wiring to the diffusion layer formed on the semiconductor substrate, and the second electrode is connected to the ferroelectric Various excellent characteristics listed below can be exhibited by forming a structure in which the structure is connected to a wiring placed on the upper side of the body layer or a wiring placed between the substrate and the low dielectric constant insulating layer.

(1) Highly integrated DRAM and ferroelectric memory in which a large number of capacitors are arranged on the same substrate can be realized. That is, D
In RAM and ferroelectric memory, memory ψ is arranged in a matrix.
Cells are arranged. Each memory cell typically includes one or two capacitors and one memory cell formed on a silicon substrate.
It is composed of one or two transistors. A first electrode of the capacitor is connected to a transistor on a silicon substrate, and a second electrode is connected as a common electrode. In such a structure, a first electrode is connected to a bit line via a transistor, a second electrode is connected to a plate line (electrode), and a specific word line or bit line is selected to control a specific memory cell. can be accessed.

(2) In the ferroelectric capacitors of ■ to ■ mentioned above, wiring formation on the surface of the ferroelectric layer can be omitted by connecting the first electrode to the diffusion layer (source or drain of the transistor) of the semiconductor substrate. At the same time, the wiring length can be shortened. Further, the second electrode is taken out from the upper side of the ferroelectric layer or from the wiring between the substrate and the low dielectric constant insulating layer, and is commonly connected with the second electrodes of several capacitors. The second electrodes connected to the common wiring may be capacitors arranged only in the same row or column, or may be all the capacitors arranged. In the former wiring structure, the common wiring connected to the second electrode can be used, for example, as a plate line of a ferroelectric memory. In the latter wiring structure, the common wiring connected to the second electrode can be used, for example, as a plate electrode of a DRAM. Therefore, by employing these wiring structures, highly integrated DRAMs and ferroelectric memories in which memory cells having ferroelectric capacitors are integrated can be realized.

(3) By making the low dielectric constant insulating layer act as a stopper when forming the groove portion filled with the second electrode, 1
Since grooves having different depths can be formed through multiple etching steps, the deposition of metal, etc. for electrode formation can be completed in one step, and the process can be simplified.

(4) Wiring connected to the first and second electrodes may be provided on the lower or upper surface of the ferroelectric layer, or the upper end of the electrode may be made to protrude from the ferroelectric material, and the electrode itself may also form wiring. If the electrode is processed to cross over the ferroelectric material, or if the upper end of the electrode is processed to cover the ferroelectric layer, when a voltage is applied to the ferroelectric layer through wiring, etc., the surface of the ferroelectric layer near the electrode may Electric field concentration occurs at locations such as overlying wiring. In such a case, the electric field concentration can be avoided by arranging a low dielectric constant insulating layer on the lower surface side or the upper surface side of the ferroelectric layer.

(5) Fill the plurality of grooves with the first and second electrodes alternately as described in ■ and ■ above, and extend the bottom of the groove filled with each first electrode to the diffusion layer formed on the substrate. Each of the first electrodes is connected to the diffusion layer, and each of the second electrodes is commonly connected to the wiring arranged on the surface side of the ferroelectric layer or the wiring arranged between the substrate and the low dielectric constant insulating layer. By doing so, for example, at least two second electrodes can be arranged opposite to the first electrode, so that a ferroelectric capacitor in which at least two capacitors are suspended from the first electrode can be obtained.

Further, crosstalk between the first electrodes can also be suppressed by the second electrode arranged between those electrodes. As a result, a ferroelectric memory having a compact, high-density, and highly reliable ferroelectric capacitor can be realized.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Example 1 FIG. 1(A) is a plan view showing a ferroelectric capacitor array of Example 1, and FIG. 1(B) is a sectional view taken along line BB in FIG. 1(A). 11 in the figure is a silicon substrate, and the surface of the substrate 11 is covered with a silicon oxide film 12 grown by, for example, thermal oxidation. This silicon oxide film 12 is covered with a buffer layer 13 made of MgO, which is a low dielectric constant insulating layer deposited, for example, by the CVD method and has a thickness of 5,000 nm. This buffer layer 13 is
It has the effect of suppressing the diffusion and reaction of PB of the ferroelectric layer, which will be described later, toward the substrate 11 during the process. A ferroelectric layer 14 made of lead zirconate titanate and having a thickness of 2 μm is coated on the buffer layer 13 by, for example, RF sputtering. This lead zirconate titanate is
P b (Z r 0.52T L O, 4g) Os
600 using a ceramic target with a composition of
A material subjected to RF sputtering at .degree. C. is used.

Further, the ferroelectric layer 14 has a length of 1.0 μm and a width of 0.
．． Two grooves 15 in the shape of a rectangular column with a depth of 5 μm and a depth of 2 μm.
a and 15b are opened at intervals of approximately 0.5 μm.

A plurality of sets (for example, 500 sets) of these two grooves 15a and 15b are opened in the ferroelectric layer 14.

The grooves 15a and 15b are formed by a lithography technique using ion etching using a chlorine-based reactive gas. First and second electrodes 16a and 116b made of metal tungsten are provided in each of the grooves 15a and 15b.
is filled. These electrodes tea, 16b are
For example, CV that reduces tungsten hexafluoride with hydrogen gas.
Formed by method D. On the ferroelectric layer 14, A
11 wirings 17a and 17b are provided, respectively. One ends of these wirings 17a and 17b connect to the plurality of sets of first and second electrodes 1 exposed on the surface of the ferroelectric layer 14.
6a and 16b, respectively, and the other end is shared by one wiring.

According to the capacitor array having such a configuration, the first and second electrodes lea are arranged in the pair of grooves 15a and 15b.
516b, and the portion of the ferroelectric layer 14 between the grooves 15a and 15b is filled with the first and second electrodes 1t3a,
A plurality of capacitors sandwiched by ferroelectric layer I
By arranging them in 4, a large amount of charge can be accumulated in a small area.

Further, for the capacitor Φ array having the above configuration, each of the first and second electrodes 16a is connected to the common wiring 17a, 17b.
, 18b, the voltage and charge hysteresis characteristic diagram shown in FIG. 2 was obtained. From this FIG. 2, the first and second electrodes 16a.

It was confirmed that the capacitor consisting of the ferroelectric layer 14 portion arranged between the electrodes Lea and 18b has memory characteristics.

Furthermore, the first and second electrodes 16a1JE of the capacitor
When a square wave pulse was applied between ib and the transient current flowing into the capacitor at this time was observed, the switching characteristic diagram shown in FIG. 3 was obtained. In FIG. 3, A shows the applied voltage waveform, B shows the inverted current waveform, and B2 shows the non-inverted current waveform. As shown in FIG. 3, each capacitor of Example 1 has memory characteristics, and the time required for polarization reversal is about 1o.
It was confirmed that it was about ns.

Embodiment 2 FIG. 5 is a sectional view showing a ferroelectric memory having a plurality of ferroelectric capacitors according to Embodiment 2. 21 in the figure is, for example, a p-type silicon substrate, and the substrate 21
A field oxide film 22 is formed on the surface of the semiconductor device to electrically isolate the device regions. On the surface of the substrate 21 surrounded by the field oxide film 22, an n" type source,
Drain regions 23 and 24 are formed electrically separated from each other. A gate electrode 26 made of, for example, polycrystalline silicon is formed on the substrate 21 including the channel region between the source and drain regions 23 and 24 with a gate oxide film 25 interposed therebetween. The entire surface of the substrate 21 including the field oxide film 22 and the gate electrode 26 is covered with, for example, SiO.
A first interlayer insulating film 27 made of 2 is coated. A contact hole 28 is opened in the interlayer insulating film 27 corresponding to a part of the source and drain regions 23 and 24. A source electrode 29 made of polycrystalline silicon is connected to the source and drain regions 23 and 24 through the contact hole 28 on the interlayer insulating film 27.
, and drain electrodes 30 are provided, respectively.

The interlayer insulating film 27 including the source electrode 29 and the drain electrode 30 is covered with a second interlayer insulating film 31 made of, for example, 5 in 2 . This interlayer insulating film 31 is coated with a buffer layer 32 made of MgO and having a thickness of 5000 nm, which is a low dielectric constant insulating layer deposited by, for example, a CVD method. The buffer layer 32 is coated with a ferroelectric layer 33 made of lead zirconate titanate and having a thickness of 2 μm, for example.

The ferroelectric layer 33 includes a groove portion 34a1 that penetrates the buffer layer 32 and the second interlayer insulating film 31 and reaches the surface of the drain electrode 30, and a length that reaches the surface of the buffer layer 32 of 1.0 μm and a width of 0.0 μm. Rectangular grooves 34b each having a width of 5 .mu.m and a depth of 2 .mu.m are opened at intervals of about 0.5 .mu.m. A plurality of pairs of such groove portions 34a and 34b are opened in the ferroelectric layer 33. Each groove portion 34a
, 34b are filled with first and second electrodes 35a, 35b made of metallic tungsten.

The first electrode 35a is directly connected to the drain electrode 30 below the ferroelectric layer 33. An All wiring 3B is disposed on the ferroelectric layer 33, and the wiring 3
One end of the electrode 6 is connected to the second electrode 35b of the plurality of electrodes whose surfaces are exposed in the column direction of the ferroelectric layer 33. By forming such wiring, the first electrode 35
a is connected to the drain region 23 of the substrate 21, and the second electrode 35b is connected to the wiring 36 on the surface side of the ferroelectric layer 33. Such a ferroelectric memory has the same circuit as shown in FIG. Note that Tr in FIG. 6 is a field effect transistor composed of the source and drain regions 23 and 24, the gate oxide film 25, and the gate electrode 26, and C is the first and second electrode 35a135b and the field effect transistor sandwiched between them. B is a bit line connected to the source electrode 29; W is a word line connected to the gate electrode 26 of the field effect transistor Tr;
D is a plate line serving as the wiring 36.

According to such a configuration, the first and second electrodes 35a13 are formed in the grooves 34a and 34b opened in the ferroelectric layer 33.
5b and fills the ferroelectric layer 3 between the grooves 34a and 34b.
By arranging a plurality of capacitors having three portions sandwiched between the electrodes 35a and 35b in the ferroelectric layer 33, a large amount of charge can be stored in a small area.

Moreover, by connecting the first electrode 35a to the wiring 29 disposed below the ferroelectric layer 33 and connected to the drain region 24 of the silicon substrate 21, wiring formation on the surface side of the ferroelectric layer 33 is omitted. At the same time, the wiring length can be shortened. Therefore, by employing such a capacitor electrode structure and wiring structure, a ferroelectric memory in which memory cells having ferroelectric capacitors are integrated at high density can be realized.

Furthermore, for such a ferroelectric memory, by adding an appropriate peripheral circuit formed on the silicon substrate 21, it is possible to write and read information to and from any memory cell arranged in a matrix. can be performed and the information can be memorized.

Example 3 This example 3 is applied to a ferroelectric capacitor array, and the manufacturing process shown in FIGS. 7(A), (B) to 10(A), (B) is This will be explained as well.

First, a silicon oxide film 42 is grown on the surface of the substrate 41 by thermal oxidation of the silicon substrate 41, and then a 500-thick film, which is a low dielectric insulating film, is grown on the silicon oxide film 42 by CVD.
A buffer layer 43 consisting of 0 MgO was deposited. Next, on this buffer layer 43 (Z r 0.52T
A ferroelectric layer 44 made of lead zirconate titanate with a thickness of 2.5 μm was coated by RF sputtering at 600° C. using a ceramic target having a composition of i O,48)03.

Subsequently, the ferroelectric layer 44 was selectively etched by ion etching lithography using a chlorine-based reactive gas to open a frame-shaped groove 45 having a width of 1 μm and a depth of 2 μm. The opening of the frame-shaped groove 45 forms a rectangular column 4B as shown in FIGS. 7(A) and 7(B).

Next, plasma C using SiH4 and N20 as source gases
The plasma 5in2 film 47 is formed into the frame-shaped groove 45 by the VD method.
(FIG. 8 CA), (
B) As shown).

Next, the plasma 5in2 film 47 and a part of the rectangular column 4B made of ferroelectric material are selectively etched by a lithography technique using ion etching using a chlorine-based reactive gas to have a width of 0.5 μm and a length of 1.0 μm. A plurality of pairs of groove portions 48a148b having a depth of L8um are formed (
For example, 500 pairs) were opened (as shown in FIGS. 9(A) and 9(B)).

Next, first and second electrodes 49a made of metallic tungsten are formed in each pair of grooves 48a and 48b by a CVD method in which tungsten hexafluoride is reduced with hydrogen gas.
49b was filled. Next, plasma 5in2 film 47
An Ag film is deposited on the entire surface of
0a and 50b were formed (Fig. 1O (A), (B)
(Illustrated). One end of these wirings 50a, 50b is connected to the first wire of the plurality of sets exposed on the surface of the plasma 5in2 film 47.
They are connected to the second electrodes 49a and 49b, respectively, and the other end is shared by one wiring.

According to the ferroelectric capacitor array having such a configuration, the first and second electrodes 49 are provided in each of the grooves 48a and 48b.
By arranging in the ferroelectric layer 44 a plurality of capacitors having a structure in which the portions of the ferroelectric layer 44 between the grooves 48a and 48b are sandwiched between the electrodes 49a and 49b, large capacitors can be formed in a small area. Charge can be accumulated.

Furthermore, by applying a voltage between each node 1 and the second electrodes 49a and 49b through the common wiring 50a and 50b in the ferroelectric capacitor array having the above configuration, the voltage and charge ratio shown in FIG. 2 described above can be obtained. A hysteresis characteristic diagram was obtained, and it was confirmed that each capacitor had memory characteristics. Furthermore, the first and second electrodes 49 of the capacitor
When a square wave pulse was applied between a and 49b and the transient current flowing into the capacitor at this time was observed, the switching characteristic diagram shown in Figure 3 mentioned above was obtained, indicating that each capacitor has memory characteristics and that polarization reversal occurs. It was confirmed that the time required was about 1 Ons.

Embodiment 4 FIG. 11(A) is a plan view showing a ferroelectric memory having a ferroelectric capacitor according to Embodiment 4, and FIG. 11(B) is a cross section taken along line BB in FIG. It is a diagram. 61 in the figure is
For example, the substrate 61 is a p-type silicon substrate, and a field oxide film 62 is formed on the surface of the substrate 61 to electrically isolate element regions.

On the surface of the substrate 61 surrounded by the field oxide film 62, n' type source and drain regions 63 and 64 are formed electrically isolated from each other. A substrate 61 including a channel region between these source and drain regions 63 and 64
A gate electrode 66 made of polycrystalline silicon, for example, is formed thereon with a gate oxide film 65 interposed therebetween. The entire surface of the substrate 61 including the field oxide film 62 and the gate electrode 66 is covered with an interlayer insulating film 67 made of, for example, 5 in 2 . This interlayer insulating film 67 is coated with a buffer layer 68 made of MgO, which is a low dielectric constant insulating layer. This buffer layer 68 is coated with a ferroelectric layer B9 made of, for example, lead zirconate titanate. A rectangular columnar groove 70a is opened from the surface of this ferroelectric layer 69, penetrating the buffer layer 68 and interlayer insulating film 67, and reaching the drain region 64 of the substrate 61.
A first electrode 71a made of metal tungsten is filled in the space a. Note that an eaves portion 72 is formed on the upper end side of the first electrode 71a so as to overlap the surface of the ferroelectric layer 69 due to the etching process. The ferroelectric layer 69 is coated with an insulating layer 73 made of, for example, low-melting glass. A rectangular columnar groove 70 b is opened from the surface of the insulating layer 73 to the surface of the buffer layer 68 through the ferroelectric layer 69 .
A second electrode 71b made of metal tungsten is filled in the second electrode 71b. The upper end of the second electrode 71b protrudes from the insulating layer 73, and is integrally connected to a wiring 74 extending in the same direction as the gate electrode 66 by patterning the metal tungsten that is the electrode forming material.

According to such a configuration, the first and second electrodes yta are provided in the grooves 70a and 70b opened in the ferroelectric layer 69.
.

By filling the ferroelectric layer 71b and arranging a plurality of capacitors in the ferroelectric layer 69, the portion of the ferroelectric layer 69 between the grooves 70a and 70b is sandwiched between the electrodes 71a and 71b, a large amount of charge can be accumulated in a small area. can do.

Furthermore, by directly connecting the first electrode 71a to the drain region 64 of the silicon substrate 61 below the ferroelectric layer 69, wiring formation on the surface side of the ferroelectric layer 69 can be omitted, and the wiring length can be shortened. can. Therefore, by employing such a capacitor electrode structure and wiring structure, a ferroelectric memory in which memory cells having ferroelectric capacitors are integrated at high density can be realized.

Furthermore, for such a ferroelectric memory, by adding an appropriate peripheral circuit formed on the silicon substrate 61, it is possible to write and read information to and from any memory cell arranged in a matrix. can be performed and the information can be memorized.

Further, a low dielectric constant insulating layer is unavoidably formed at the interface between the ferroelectric layer 69 and the buffer layer 68 underlying the ferroelectric layer 69.

These low dielectric constant I layers are the ferroelectric layer 69 and the buffer layer B.
In the structure formed at the interface of No. 8, in the present invention, rectangular columnar grooves 70a and 70b penetrating the interface between the ferroelectric layer 69 and the buffer layer 68 are opened, and first and second grooves are formed in these grooves 70a and 70b. Second electrode 71a
, 71b, and the electrodes 71a, 71b are made to face the low dielectric constant insulating layer in a perpendicular or nearly vertical state, so that the parasitic capacitance C' due to the eight low dielectric constant layers is reduced as shown in FIG. As shown in both circuits, the capacitor C is connected in parallel to the ferroelectric capacitor C. Therefore, it is possible to avoid connecting parasitic capacitances in series as in the conventional Brenna type ferroelectric capacitor shown in FIGS. 35 and 36 described above, thereby obtaining a ferroelectric capacitor with excellent ferroelectric characteristics. be able to. Note that this effect can be similarly achieved in a ferroelectric capacitor in which the first and second electrodes reach the interface between the buffer layer and the ferroelectric layer as in Example 1.2.

Furthermore, by stopping the bottom of the second electrode 71b on the surface of the buffer layer 68, it becomes possible to arrange wiring in the area under the buffer layer 68 (in the area of the interlayer insulating film 67), which makes it possible to A densely integrated ferroelectric memory can be realized.

Example 5 FIG. 13 is a sectional view showing a ferroelectric memory having a ferroelectric capacitor according to Example 5. Components similar to those in FIG. 11 described above are designated by the same reference numerals, and their explanation will be omitted.

In the ferroelectric capacitor of Example 5, the ferroelectric layer 69 is coated with another low dielectric constant insulating layer 75 made of, for example, MgO. , a ferroelectric material in which a rectangular columnar groove 70a penetrating the buffer layer 68 and the interlayer insulating film 67 and reaching the drain region 64 of the silicon substrate 61 is opened, and the groove 70a is filled with a first electrode 71a made of metallic tungsten. It has a structure with a capacitor. Note that the first electrode 7
On the upper end side of 1a, an eaves portion 72 is formed so as to overlap the surface of the low dielectric constant insulating layer 75 due to the etching process.

According to such a configuration, the first and second electrodes 71a are connected to each other by the transistors and wiring 74 formed on the silicon substrate 61
, 71b, the first electrode 71
The electric field concentration on the ferroelectric layer B9 at the eaves portion 72 of a can be alleviated.

That is, as in the fourth embodiment described above, the ferroelectric layer 6 is etched on the upper end side of the first electrode 71a.
When the eaves portion 72 is formed to overlap the surface of the first
, when a voltage is applied between the second electrodes 71a and 71b, an electric field is concentrated on the ferroelectric layer 69 of the eaves part 72 of the first electrode 71a, and the electric field applied to the ferroelectric layer 69 is unsteady. It becomes uniform. The electric field concentration on the ferroelectric layer B9 lowers the withstand voltage of the capacitor, and the unevenness of the electric field makes the threshold voltage at which the spontaneous polarization of the ferroelectric capacitor is reversed as described above unstable, which makes it difficult to use as a memory. It becomes an obstacle. In the fifth embodiment, the ferroelectric layer 69 is further coated with a low dielectric constant insulating layer 75, and the eaves portion 72 of the first electrode 71a is disposed on the low dielectric constant insulating layer 75. It is possible to alleviate the electric field concentration at the part of the ferroelectric layer 69 where the portion 72 is located, and to apply a uniform electric field to the ferroelectric layer 69. You can get body memory. According to experiments conducted by the present inventors, the withstand voltage of the ferroelectric capacitor configured in Example 5 can be improved by approximately 1.3 to 6, compared to the same capacitor in Example 4 described above. was confirmed.

Embodiment 6 This embodiment 6 is applied to a ferroelectric memory having a ferroelectric capacitor, and this memory is shown in FIGS.
This will be explained with reference to the manufacturing process shown in (i).

First, for example, a p-type silicon substrate 61 is selectively oxidized to form a field oxide film 62 on the surface of the substrate 61 for electrically isolating device regions. Subsequently, the surface of the substrate 61 surrounded by the field oxide film 62 is thermally oxidized to form a thin oxide film, and a polycrystalline silicon film containing impurities such as arsenic is deposited on the entire surface. A gate electrode 66 is formed on the substrate 61 via the gate oxide film 65 by patterning the film and the oxide film.

Subsequently, using the field oxide film 62 and gate electrode 66 as a mask, an n-type impurity such as arsenic is applied to the substrate 61.
Ion implantation is performed to form n''' type source and drain regions 63 and 64 which are activated and electrically isolated from each other.

After this, the field oxide film 62 and the gate electrode 66 are
For example, a 5i film is applied to the entire surface of the substrate 61 including the
An interlayer insulating film 67 made of n2 is deposited, and a buffer layer 68 made of MgO, which is a low dielectric constant insulating layer, is further deposited by RF magnetron sputtering (as shown in FIG. 14(a)).

Next, a resist pattern 7 is formed on the buffer layer 68 by photolithography in which a portion corresponding to a portion of the drain region 64 (a portion where a groove portion for filling the first electrode is planned) is opened.
After forming B, the buffer layer 68 is selectively etched away using the resist pattern 76 as a mask to form an opening 77 (as shown in FIG. 3B). Subsequently, after removing the resist pattern 76, a ferroelectric layer 69 made of lead zirconate titanate, for example, is deposited on the buffer layer 68 by RF magnetron sputtering, and then another layer 69 made of MgO is deposited by RF magnetron sputtering. A low dielectric constant insulating layer 75 is deposited (as shown in FIG. 3(c)).

Next, as shown in the same figure (d), the low dielectric constant insulating layer 7
A resist pattern 78 is formed on the resist pattern 5 in which a portion corresponding to the opening 77 and a portion corresponding to a portion of the field oxide film 62 (a portion where a groove portion for filling the second electrode is to be formed) are opened. Subsequently, ion beam etching is performed using a chlorine-based reactive gas using the resist pattern 78 as a mask. At this time, since an opening 77 is previously formed in the buffer layer 68 located below the portion of the low dielectric constant insulating layer 75 exposed through one of the openings in the resist pattern 78, the insulating layer 75 is Etching is performed through the dielectric layer 69, the opening 77 of the buffer layer 68, and the interlayer insulating film 67, and the drain region 6 of the substrate 61 is etched.
A rectangular columnar groove 70a reaching four points is formed. Further, in the low dielectric constant insulating layer 75 exposed from the opening hole corresponding to a part of the field oxide film 62, a buffer layer 6 which acts as an etching stopper is provided below the low dielectric constant insulating layer 75.
8 exists, etching is performed only up to the insulating layer 75 and the ferroelectric layer 69, and a rectangular columnar groove 70b with the buffer layer 68 at the bottom is formed (as shown in FIG. 3(e)).

Next, a resist pattern 78 is formed as shown in FIG.
The groove portions 70a, 7 are formed by a CVD method in which tungsten hexafluoride gas is reduced with hydrogen gas while the tungsten hexafluoride gas remains.
A metal tungsten film 79 is deposited on the resist pattern 78 including 0b. Next, the resist pattern 7
8 and selectively remove the metal tungsten film 79 portion on the resist pattern 78, or use a lift-off method to leave tungsten in each of the grooves 70a and 70b, and form the first and second electrodes 71a and 71b. (Illustrated in FIG. 2(g)). Subsequently, an A.9 film 80 is deposited on the entire surface by sputtering, and the Al film 80 is patterned using a resist pattern (not shown) formed by photolithography as a mask.
A ferroelectric memory in which a ferroelectric capacitor is formed on a silicon substrate 61 is manufactured (as shown in FIG. 11(i) and FIG. 15). Note that FIG. 15 is a plan view of FIG. 14(i).

According to the method of Example 6, by forming an opening 77 in the buffer layer 68 in advance and allowing the buffer layer 68 to act as an etching stopper, ions can be etched using one resist pattern as a mask. Two grooves 70a having different depths by beam etching,
70b can be formed. As a result, the subsequent formation of the first and second electrodes 71a and 71b can be performed by a single process such as vapor deposition of a metal tungsten film and lift-off method, thereby simplifying the process. Moreover, the first
Since the thickness of the ferroelectric layer 69 sandwiched between the second electrodes 71a and 71b can be adjusted to the designed dimensions and variations in thickness can be eliminated, the first and second electrodes 71a and 71
When a plurality of sets of ferroelectric capacitors b are formed in the ferroelectric layer 69, a ferroelectric memory having a ferroelectric capacitor with excellent ferroelectric properties can be realized.

That is, in the structure like the embodiment 4.5 described above, the groove portion 70
It is necessary to form electrodes a and 70b in separate steps, and along with this, the first electrode 71a and second electrode 71b also need to be formed separately by vapor deposition and buttering of a metal tungsten film, which makes the process complicated. do.

Furthermore, since the grooves 70a and 70b filled with the first and second electrodes 71a and 71b are formed separately, the mask misalignment causes the portion of the ferroelectric layer 69 to be formed between the first and second electrodes. There is a risk that the thickness will deviate from the design dimension. As a result, the first and second electrodes 71a.

When a ferroelectric memory is realized by forming a plurality of sets of capacitors 71b in the ferroelectric layer 69, a problem arises in that the ferroelectric characteristics vary among the ferroelectric capacitors.

On the other hand, by employing the method of the sixth embodiment, a ferroelectric memory having a ferroelectric capacitor with excellent ferroelectric properties can be manufactured through simple steps as described above.

Further, according to the configuration of the sixth embodiment, the upper end surface of the second electrode 71b is coated with the low dielectric insulating film 75, and the second electrode 71b is coated with the low dielectric insulating film 75.
Ail wiring 81 connected to 1b is covered with a low dielectric insulating film 75.
By forming the ferroelectric layer 69, it is possible to alleviate the electric field concentration on the ferroelectric layer 69 at the portion of the Ap wiring 81 near the protrusion of the second electrode 71b, and also to apply a uniform electric field to the ferroelectric layer 69, thereby increasing the withstand voltage. A ferroelectric memory having a ferroelectric capacitor with excellent ferroelectric properties and ferroelectric properties can be realized.

In the sixth embodiment, the buffer layer 68 is used as an etching stopper, but the present invention is not limited thereto. For example, as shown in FIGS. 16(A) and 16(B), the interlayer insulating film 6
By forming the wiring 81 made of polycrystalline silicon on the upper surface of 7 and depositing the buffer layer 88 and the ferroelectric layer 69 thereon, the wiring 8I made of polycrystalline silicon can act as an etching stopper. By performing ion beam etching once using a resist pattern (not shown) as a mask, it is possible to form grooves 70a with different depths, that is, grooves 70a that reach as far as the drain region 64 of the silicon substrate 6I and grooves 7 (lb) that stop at the surface of the AI wiring 81.

According to this method, a ferroelectric memory having a ferroelectric capacitor with excellent ferroelectric properties similar to that of Example 6 can be manufactured through simple steps.

Furthermore, by connecting the second electrode 71b to the AI wiring 81 placed on the interlayer insulating film 67 below the ferroelectric layer 69, another wiring can be placed on the surface side of the ferroelectric layer 69. It becomes possible. Furthermore, Fig. 16 (A) and (B)
), it is also possible to arrange another wiring 82 on the field oxide film 62.

Example 7 FIG. 17 (A) is a plan view showing a ferroelectric memory having a ferroelectric capacitor according to Example 7, and FIG. 17 (B) is a cross section taken along line BB in FIG. 17 (A). It is a diagram. Reference numeral 101 in the figure is, for example, a p-type silicon substrate, and a field oxide film 102 is formed on the surface of the substrate 101 to electrically isolate element regions. The field oxide film 1
On the surface of the multiple element region of the substrate 101 surrounded by 02, a plurality of n+ type source and drain regions 103 and 104 are formed to be electrically isolated from each other. These sources,
A gate electrode 106 made of, for example, polycrystalline silicon is formed on the substrate 101 including the channel region between the drain regions 103 and 104 with a gate oxide film 105 interposed therebetween. The field oxide film 102 and the gate electrode 10
The entire surface of the substrate 101 containing B is coated with a first interlayer insulating film 107 made of, for example, SiO2. A plurality of contact holes 108 are opened in the interlayer insulating film 27 corresponding to parts of the source and drain regions 103 and 104. A source electrode 109 made of Ajl is provided on the interlayer insulating film 107 and is connected to the source region 103 through the contact hole 108, respectively.

The interlayer insulating film 107 including the source electrode 109 is covered with a second interlayer insulating film 110 made of, for example, 5 in 2 . On this interlayer insulating film 110, for example, MgO, which is a low dielectric constant insulating layer deposited by the CVD method.
A buffer layer Ill consisting of is coated. The buffer layer 111 is coated with a ferroelectric layer 112 made of, for example, lead zirconate titanate. A plurality of rectangular columnar grooves 113a are opened from the surface of the ferroelectric layer 112, penetrating the buffer layer 111, the second and first interlayer insulating films 107 and 110, and reaching the surface of the drain region 104 of the substrate lot, A first electrode 114a made of tungsten metal, for example, is filled in these grooves 113a. On the ferroelectric layer 112, 5i02
A third interlayer insulating film 115 consisting of is coated.

Also, a plurality of grooves 113b extend from the surface portion of the third interlayer insulating film 115 located between the grooves 113a to the surface of the buffer layer 111, penetrating the ferroelectric layer 112.
are opened, and a second electrode 114b made of, for example, metal tungsten is filled in these grooves 113b. That is, the first and second electrodes 114a.

114b are alternately arranged on the ferroelectric layer 112.

Further, on the third interlayer insulating film 115, an Ag wiring 11B is provided which is commonly connected to the upper end of each of the second electrodes 114b.

According to the ferroelectric memory of Example 7, the first and second
Since the electrodes 114a% 114b are arranged alternately on the ferroelectric layer 112, and the second electrodes 114b are commonly connected by the Ag wiring 11B, the equivalent circuit shown in FIG. 18 is obtained.
Two ferroelectric capacitors C5 are connected to the drain side of one transistor Tr. Note that the Tr has source and drain regions 103 and 104, and gate oxide film 1.
05 and a gate electrode 106, the two 05's are composed of a ferroelectric layer 112 sandwiched between adjacent second electrodes 114b, 114b centered on the first electrode 114a. A ferroelectric capacitor, B is a bit line connected to the source electrode 109, W is a word line connected to the gate electrode 106 of the field effect transistor Tr, and D is a plate line (electrode) made of the All wiring 116. Therefore, in the seventh embodiment, a plurality of ferroelectric capacitors having a large capacity are formed in a small occupied area, and a highly integrated ferroelectric memory can be realized.

Further, according to the configuration of the seventh embodiment, the plurality of first electrodes 114
A plurality of second electrodes 114b adjacent to center a
Even if the position of the transistor Tr is shifted, the capacitance fluctuation of the two capacitors connected to one transistor Tr can be suppressed. This will be explained with reference to the equivalent circuits of FIGS. 19(A) and 20(B) and FIG.

In FIGS. 19(A) and 19(B), the first electrode 114. It is assumed that the commonly connected second electrode 114b adjacent to a is shifted by ΔL in the arrangement direction due to a positional shift. Note that the electrode 114a in the case where no positional shift occurs
, 114b, and the capacitance between the first electrode 114a and the second electrode 114b adjacent on one side is C8°.

At this time, the capacitance C9O can be expressed by the following equation.

C3O-εA/L...(1) Here, ε is the dielectric constant and A is the electrode area. Assuming that L is slightly shifted by ΔL, if we expand the previous Ha Cs around L, then Cs = C5o+ (d Cso/ d L) ・
ΔL+ 1/2 (d 2 Cs / d
L2) ・ΔL... (2) Ignoring higher-order terms of second order or higher, C6~C5°+(d cs./d L) φΔLm C
5(, -εAΔL/L2 ” c so−ΔCs −(3) On the other hand, the capacitance when the distance between the electrodes shifts by −ΔL due to positional shift is expressed by the following equation.

Cs ~ Cso+ (d Cso/ d L) (
-ΔL)# (: 5.)+e AΔL/L240,
. +ΔC5...(4) By the way, as shown in FIG. 19, the distance between the first electrode 114a and the adjacent second electrode 114b on one side (left side) is L+ΔL, and the capacitance is this. Accordingly, it becomes C3-ΔC5. The distance between the first electrode 114a and the adjacent second electrode 114b on the other side (right side) is L.
-ΔL, and the capacitance accordingly becomes C5+ΔC5. Therefore, unless ΔL is extremely large, the first electrode 1
Two second electrodes 11 adjacent to center 14a
The capacitance between 4b is the sum of C5-ΔC3 and C5+ΔC5, and even if a positional shift occurs, it becomes 2C5 and remains unchanged, which has the effect of suppressing capacitance fluctuations.

In addition, as shown in FIGS. 17(A) and (B), the first and second
By alternately arranging the electrodes 114a and 114b on the ferroelectric layer 112, cross talk between the first electrodes 114a can be suppressed through the interposition of the second electrode 114b. In this case, the cross talk can be suppressed more effectively by making the planar area of the second electrode larger than that of the first electrode.

Example 8 FIG. 21 (A) is a plan view showing a ferroelectric memory having a ferroelectric capacitor according to Example 8, and FIG. 21 (B) is a cross section taken along line BB in FIG. 21 (A). It is a diagram. Note that the same members as those shown in FIG. 17 described above are designated by the same reference numerals and their explanations will be omitted. As shown in FIG. 21, the ferroelectric memory of Example 8 has a plurality of grooves 113a having different depths in the ferroelectric layer 112.
, 113b are two-dimensionally opened, and these grooves 113
a, 113b, first and second electrodes 114a, 11
4b are filled so as to be arranged alternately in the XSY direction, and each second electrode LL4b is arranged on the third interlayer insulating film 115.Aj) A plurality of ferroelectric capacitors are commonly connected by wiring 116. It has a structure.

The ferroelectric memory of Example 8 has an equivalent circuit shown in FIG. 22, in which four ferroelectric capacitors C5 are connected to the drain side of one transistor Tr. In addition,
The Tr is a field effect transistor composed of source and drain regions 103 and 104, a gate oxide film 105, and a gate electrode 106, and the four C5 are field effect transistors composed of the first electrode 114a.
Four second electrodes 114 adjacent in the XY force direction centering on
B is a bit line connected to the source electrode 109; W is a word line connected to the gate electrode 106 of the field effect transistor Tr; is a plate line (electrode) made of the AN wiring 11B. Therefore, in the eighth embodiment, a plurality of ferroelectric capacitors with a larger capacity are formed in a smaller occupied area than in the seventh embodiment,
A ferroelectric memory that is highly integrated can be realized.

Example 9 FIG. 23 (A) is a plan view showing a ferroelectric memory having a ferroelectric capacitor according to Example 9, and FIG. 23 (B) is a cross section taken along line BB in FIG. 23 (A). It is a diagram. Note that the same members as those shown in FIG. 17 described above are designated by the same reference numerals and their explanations will be omitted. As shown in FIG. 23, the ferroelectric memory of this embodiment 9 includes a buffer layer Ill, a buffer layer Ill, a second layer,
the substrate 1 through the first interlayer insulating film 107, 110;
A plurality of rectangular columnar grooves 113a are opened that reach the surface of the drain region 104 of No. A lattice-shaped groove 113 that penetrates the ferroelectric layer 112 and reaches the surface of the buffer layer 111 is formed in each groove 113a.
The lattice-shaped grooves 113 are filled with a second electrode 114b made of, for example, metal tungsten, and the second electrode 114b is connected to the third interlayer insulating film 11.
Af placed on 5! It has a structure in which a plurality of ferroelectric capacitors are commonly connected by wiring 116.

The ferroelectric memory of this embodiment 9 has an equivalent circuit shown in FIG. 22, similar to the above-mentioned embodiment 8, and has a configuration in which four ferroelectric capacitors C5 are connected to the drain side of one transistor Tr. Therefore, in this embodiment 9, a plurality of ferroelectric capacitors with a larger capacity are formed in a smaller occupied area than in the seventh embodiment, and a highly densely integrated ferroelectric memory can be realized.

Example 10 Example 1O is applied to the manufacture of a ferroelectric memory having a ferroelectric capacitor, and the process is shown in FIG.
This will be explained with reference to a) to (f) and FIGS. 25 to 32.

First, for example, a p-type silicon substrate 201 is selectively oxidized to form a field oxide film 202 on the surface of the substrate 201 for electrically isolating device regions.

Subsequently, the surface of the substrate 201 surrounded by the field oxide film 202 is thermally oxidized to form a thin oxide film, a polycrystalline silicon film containing impurities such as arsenic is deposited on the entire surface, and the polycrystalline silicon film is further deposited on the entire surface. After thermally oxidizing the film to grow a silicon oxide film on the surface, the silicon oxide film, polycrystalline silicon film, and oxide film are patterned to form the substrate 2.
A gate electrode 204 is formed on 01 through a gate oxide film 203.
, a silicon oxide film pattern 205 is formed. Subsequently, the field oxide film 202 and the gate electrode 204
Using the mask as a mask, n-type impurities such as arsenic are ion-implanted into the substrate 201, activated, and electrically isolated from each other.
Form the source and drain regions 206 and 207 of the mold (as shown in FIGS. 24(a) and 25). Note that FIG. 25 is a plan view of FIG. FIG. 26 is a sectional view taken along the lines X and -X in FIG. 25;

Next, the field oxide film 202 and the gate electrode 2
For example, 5 is applied to the entire surface of the substrate 201 including the
After depositing a first interlayer insulating film 208 made of in2 and further depositing a polycrystalline silicon film containing n-type impurities such as arsenic by CVD, the polycrystalline silicon is patterned to form plate lines 209. ° This plate line 209 passes through the source and drain regions 206 and 207 and is commonly connected to the ferroelectric capacitors arranged in the two column directions, as shown in FIG. It has a separated shape. In addition, the second
Figure 6 is a plan view of the same figure (b), and the same figure (b) is a plan view of the same figure (b).
6 is a sectional view taken along the line X, -X, in FIG. 6. FIG.

Next, a second interlayer insulating film 210 made of, for example, boron phosphorus silicate (BPSG) is deposited on the first interlayer insulating film 208 including the plate line 209 by a CVD method, and then heat treated to flatten the surface. A buffer layer 211 made of MgO, which is a low dielectric constant insulating layer, is deposited by RF magnetron sputtering. Subsequently, for example, lead zirconate titanate is deposited on the buffer layer 211 by RF magnetron sputtering, and then patterned. Through this step, as shown in FIG. 27, the ferroelectric layer is removed at the source region 206 and has a shape common to the two ferroelectric capacitors arranged in the column direction. 212 is formed. Note that FIG. 27 is a plan view of FIG. 27(c), and FIG. 27(c) is a sectional view taken along the lines X and -X of FIG. 27.

Next, a third interlayer insulating film 213 of, for example, 5 in 2 is deposited on the entire surface by CVD method, and the interlayer insulating film 213 is further deposited on the entire surface.
After forming a resist pattern (not shown) in which the first and second electrode grooves are to be formed by photolithography on No. 13, a chlorine-based reactive gas was used using the resist pattern as a mask. Perform ion beam etching.

Through this step, rectangular columnar grooves 214a and 214b having different depths are opened as shown in FIG. 28(d) and FIG.

The groove 214a reaches the drain region 207, and grooves 214b are arranged on three sides around the groove 214a.

These grooves 214b have a shape with the surface of the plate line 209 as the bottom due to the etching stopper action of the plate line 209. 28 is a plan view of FIG. 28(d), and FIG. 28(d) is a sectional view taken along the line X1X1 of FIG. 28. Subsequently, the groove portion 214a is
After a metallic tungsten film is deposited on the resist pattern including the resist pattern 214b, the resist pattern is removed, and tungsten is left in each of the grooves 214a and 214b by a lift-off method that selectively removes the metallic tungsten film portion thereon. , first and second electrodes 215a, 21
5b (as shown in FIG. 5(e)).

Next, CVD is applied to the third interlayer insulating film 213 with the upper surfaces of the first and second electrodes 215a and 215b exposed.
For example, a fourth interlayer insulating film 21 of 5 in 2 is formed by a method.
6 is deposited and selectively etched over the fourth and third interlayer insulating films 213.21B, the buffer layer 211, and the second and first interlayer insulating films 210.208 corresponding to the source region 206. After opening the contact hole 217,
An Al film is deposited on the entire surface and patterned to form an Al wiring 218 connected to the source region 206 through the contact hole 217. Thereafter, a protective film (not shown) is deposited over the entire surface to produce a ferroelectric capacitor array (as shown in FIG. 3(f) and FIGS. 30 to 32). 29 is a plan view of FIG. 29(f), and FIG. 29(f) is a sectional view taken along the lines X and -X of FIG. 29. In addition, FIGS. 30 to 32 are respectively
2-X2 line, Y, -Y, line, and Y2-Y2 line. FIG.

According to the method of Example 10, the first interlayer insulating film 208
Above is a plate line 209 made of polycrystalline silicon or the like with holes corresponding to the source and drain regions 206 and 207.
By providing the plate line 209 as an etching stopper, grooves 214a and 214b with different depths and the drain region 207 are formed by one ion beam etching using the resist pattern as a mask.
A groove 214a that reaches up to the plate line 209 and a groove 214b that has the plate line 209 as the bottom can be opened. As a result, the subsequent formation of the first and second electrodes 215a and 215b can be performed by a single process such as vapor deposition of a metal tungsten film and a lift-off method, thereby simplifying the process. Moreover, since the thickness of the ferroelectric layer 212 sandwiched between the first and second electrodes 215a and 2L5b can be adjusted to the designed dimensions, the capacitance can be stabilized and multiple ferroelectric layers with excellent ferroelectric properties can be used. A ferroelectric memory equipped with a physical capacitor can be realized.

In addition, according to the structure of the tenth embodiment, as shown in FIG. 24(f) and FIGS. 29 to 32, there is a strong Since the second electrode 215b commonly connected to the plate line 209 can be placed across the dielectric layer 212, three ferroelectric capacitors can be connected to the drain region 207 of the transistor. A dielectric memory can be realized.

Furthermore, by commonly connecting the second electrodes with a plate line 209 disposed below the ferroelectric layer 212, the Ag wiring 218 used as a bit line is connected to the fourth interlayer insulating film on the upper surface side of the ferroelectric layer 212. 216, the degree of freedom in design can be increased, and a ferroelectric memory that is highly integrated can be realized.

Note that a ferroelectric layer having a spontaneous polarization axis in the plane direction (for example, a barium strontium niobate layer having a tetragonal tungsten bronze type crystal structure) is provided in the buffer layer as in Examples 1 to 10, and a groove is formed. , the first to these grooves
It was confirmed that a ferroelectric capacitor having a structure in which the second electrode is filled exhibits a hysteresis curve specific to ferroelectric characteristics.

[Effects of the Invention] As detailed above, the ferroelectric capacitor of the present invention has a large electrode area with a small occupied area, and can store a large amount of charge. Further, according to the ferroelectric capacitor of the present invention, good ferroelectricity can be exhibited even when using a ferroelectric layer in which the spontaneous polarization axis is oriented only in the in-plane direction. Furthermore,
According to the ferroelectric capacitor of the present invention, by electrically separating capacitors and between capacitors and wiring using a low dielectric constant insulating film, it is possible to reduce malfunctions and reduce delay time caused by stray capacitance. This makes it possible to realize highly integrated DRAMs and ferroelectric memories. Furthermore,
By improving the connection form between the first and second electrodes and external wiring, etc., or by adopting a form in which the first and second electrodes are arranged alternately and one electrode is commonly connected, multiple A ferroelectric memory in which ferroelectric capacitors and the like are densely integrated can be realized. .

[Brief explanation of drawings]

FIG. 1(A) is a plan view showing a ferroelectric capacitor array in Example 1 of the present invention, and FIG. 1(B) is a plan view of the same FIG. 1(A).
FIG. 2 is a diagram showing the voltage and charge hysteresis characteristics of the ferroelectric capacitor of Example 1, and FIG. 3 is a diagram showing the hysteresis characteristics of the ferroelectric capacitor of Example 1. A diagram showing switching characteristics, FIG. 4 is a partial cross-sectional perspective view for explaining the action of the ferroelectric capacitor of the present invention,
FIG. 5 is a sectional view showing a ferroelectric memory according to a second embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram of the ferroelectric memory shown in FIG. Figure 7 (A), (B) to Figure 10 (A), C
B) is the ferroelectric capacitor in Example 3 of the present invention.
The manufacturing process of the array is shown, and (A) in each figure is a plan view, and (B) in each figure is a corresponding partially sectional perspective view taken along line BB in (A). FIG. 11(A) is a plan view showing a ferroelectric memory in Example 4 of the present invention, and FIG. 11(B)
is a sectional view taken along the line B-B of the same figure (A), and FIG.
FIG. 1 is an equivalent circuit diagram of the ferroelectric memory shown in FIG. 1, FIG.
4 (a) to (i) are I of the ferroelectric memory of Example 6.
15 is a plan view of FIG. 14(i), FIG. 16(A) is a plan view of a ferroelectric memory showing a modification of the sixth embodiment of the present invention, and FIG. B) is a cross-sectional view taken along line B-B in FIG. 17(A), FIG. 17(A) is a plan view showing a ferroelectric memory in Example 7 of the present invention, and FIG.
is a cross-sectional view taken along the line B-B of the same figure (A), and FIG.
7 is an equivalent circuit diagram of the ferroelectric memory, FIG. ), FIG. 20 is an equivalent circuit diagram of the ferroelectric memory in FIG. 19, and FIG. 21(A) is a plan view showing the ferroelectric memory in Example 8 of the present invention. , the same figure (B) is the same figure (A
), FIG. 22 is an equivalent circuit diagram of the ferroelectric memory in FIG. 21, and FIG. 23(A) is a plan view showing the ferroelectric memory in Example 9 of the present invention. , the same figure (B
) is a sectional view taken along the line B-B in Figure (A), and Figure 24 (a
) to (f) are cross-sectional views showing the manufacturing process of the ferroelectric memory in Example 10 of the present invention, and FIG. 25 is the cross-sectional view shown in FIG. 24 (a).
), Fig. 26 is the plan view of Fig. 24(b), and Fig. 26 is the plan view of Fig.
Fig. 7 is a plan view of Fig. 24(c), and Fig. 28 is a plan view of Fig. 24(c).
d), FIG. 29 is a plan view of FIG. 24(f), and FIGS. 30 to 32 are X 2-X of FIG. 29, respectively.
2 line, Yl-Y line, cross-sectional view along Y2-Y2 line, 3rd line
Figure 3 is a diagram showing the relationship between the electric field and polarization of the ferroelectric phase.
The figure is a diagram showing the relationship between the electric field and polarization of the paraelectric phase, Figure 35 (A) is a plan view showing a conventional Brehner type capacitor, and Figure 35 (B) is a line BB in Figure 35 (A). Cross-sectional view, No. 36
The figure is an equivalent circuit diagram of the Brehner type capacitor shown in FIG. 35. 1111.21.41.61.101.201...Silicon substrate, 2.14.33.44.69.112.2
12... Ferroelectric layer, 13.32.43.68.11
1.211... buffer layer, 13a, 13b,
34a, 34b, 48a, 48b,
70a. 70b, 113a, 113b, 113.21
4a, 214b-=groove, 15a, 15b,
35a s 35b % 49a, 49b, 7
1a. 71b, 114a, 114b, 215a, 21
5b--electrode, 17a117b, 3B, 50a
, 50b, 74.81.82.109.11B,
218...Wiring, 23.63.103.20[i...
・N-type source region, 24.64.104207,...
・n''' type drain region, 26.66.105.204
... Gate electrode, 46 ... Rectangular column made of ferroelectric material, 47 ... Plasma 5in2, Tr ... Field effect transistor, C, cs ... Ferroelectric capacitor, B.
... Bit line, W... Word line, D... Plate line (electrode). (A) Voltage: 2V/div Charge fil: 200pc/div Figure (B) Figure 1 t (ns) 1 Figure Figure Figure Figure Figure (A) Figure (A) (B) Figure 6 5 1 0 Figure 49b Figure 12 Figure 13 (A) (B) (a) 7 (b) Figure 14 (C) 77 (d) (9) Figure 14 (e) (f) (i) Figure 14 Figure 15 (A) (B) (a) (b) Figure 24 Figure 24 Figure 30 Figure 32 Figure 33 Figure 34

Claims (9)

[Claims] (1) A ferroelectric layer provided on a substrate, and electrodes that are opened in this ferroelectric layer and are formed to face each other along the thickness direction of the ferroelectric layer with the ferroelectric interposed therebetween. 1. A ferroelectric capacitor comprising: a groove filled with a ferroelectric substance; and first and second electrodes filled in the groove so as to face each other with the ferroelectric material interposed therebetween. (2) The ferroelectric capacitor according to claim 1, wherein the first and second electrodes are filled in the groove portion with an insulating material interposed in a portion other than the contact portion with the ferroelectric material. . (3) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; and first and second electrodes filled in these grooves so as to face each other with the ferroelectric layer interposed therebetween, and the bottom of one of the grooves is connected to the substrate. A first electrode filled in the groove is connected to the diffusion layer, and a second electrode filled in the other groove is placed on the surface side of the ferroelectric layer. A ferroelectric capacitor characterized by being connected to arranged wiring. (4) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; comprising a columnar groove facing each other with the ferroelectric material interposed therebetween, and first and second electrodes filled in the groove so as to face each other with the ferroelectric material interposed therebetween;
The bottom of one of the grooves reaches a wiring located between the substrate and the low dielectric constant insulating layer and connected to a diffusion layer of the substrate, and a first electrode filled in the groove is connected to the wiring. A ferroelectric capacitor, characterized in that the second electrode filled in the other groove is connected to the wiring arranged on the surface side of the ferroelectric layer. (5) The bottom of the other groove is located in the low dielectric constant insulating layer, and the bottom surface of the second electrode filled in the groove is stopped at the surface of the low dielectric constant insulating layer. Or the ferroelectric capacitor according to 4. (6) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; a columnar groove facing each other through the ferroelectric material, and first and second electrodes filled in the grooves so as to face each other with the ferroelectric material interposed therebetween; A wiring that reaches a diffusion layer formed on the substrate, connects a first electrode filled in the groove to the diffusion layer, and connects the bottom of the other groove between the substrate and the low dielectric constant insulating layer. A ferroelectric capacitor characterized in that a second electrode filled in the groove is connected to the wiring. (7) The surface of the ferroelectric layer is coated with another low dielectric constant insulating layer, and the ferroelectric layers are opposed to each other along the thickness direction of the ferroelectric layer through the low dielectric constant insulating layer. 7. The method according to claim 3, wherein columnar grooves are opened and first and second electrodes are filled in these grooves so that their upper ends protrude from the low dielectric constant insulating layer. ferroelectric capacitor. (8) A ferroelectric layer provided on a semiconductor substrate with a low dielectric constant insulating layer interposed therebetween; a plurality of columnar grooves facing each other through the ferroelectric material, and first and second electrodes filled in the grooves so as to face each other with the ferroelectric material interposed therebetween; The first and second electrodes are arranged so that the second electrode is interposed therebetween, and the bottom of the groove filled with each first electrode is made to reach the diffusion layer formed on the substrate to separate each first electrode. A ferroelectric capacitor characterized in that each second electrode is connected to a diffusion layer, and each second electrode is commonly connected to a wiring arranged on a surface side of the ferroelectric layer. (9) The bottom of the groove filled with each of the second electrodes reaches a wiring disposed between the semiconductor substrate and the low dielectric constant insulating layer, and each of the second electrodes is commonly connected to the wiring. 9. The ferroelectric capacitor according to claim 8.