JPH05343615A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH05343615A JPH05343615A JP4149519A JP14951992A JPH05343615A JP H05343615 A JPH05343615 A JP H05343615A JP 4149519 A JP4149519 A JP 4149519A JP 14951992 A JP14951992 A JP 14951992A JP H05343615 A JPH05343615 A JP H05343615A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- dielectric
- electrodes
- semiconductor device
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims description 8
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims description 5
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims 1
- 229910052746 lanthanum Inorganic materials 0.000 claims 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 1
- 239000000126 substance Substances 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 48
- 239000011229 interlayer Substances 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 239000010410 layer Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000002161 passivation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- -1 for example Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 238000003980 solgel method Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主に、キャパシタを有
する半導体装置、特に半導体記憶装置の構造、及びその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a semiconductor device having a capacitor, and more particularly to a structure of a semiconductor memory device and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来のキャパシタが半導体基板上に集積
された半導体装置としては、ダイナミック・ランダム・
アクセス・メモリ（ＤＲＡＭ）等が実用化されており、
また、最近ではＭＯＳ型半導体装置に、強誘電体膜を積
層した構造の不揮発性メモリがインターナショナル・エ
レクトロン・デバイセズ・ミーティング（ＩＥＤＭ）’
８７、８５０頁−８５１頁に提案されている。2. Description of the Related Art A conventional semiconductor device in which capacitors are integrated on a semiconductor substrate is a dynamic random
Access memory (DRAM) has been put to practical use,
In addition, recently, a non-volatile memory having a structure in which a ferroelectric film is laminated on a MOS semiconductor device has been used in International Electron Devices Meeting (IEDM) '.
87, p.850-851.
【０００３】図５にＭＯＳ型半導体装置に強誘電体膜を
積層した構造の、不揮発性半導体メモリの一例を示す。
図５において、５０１はＰ型シリコン基板であり、５０
２は素子分離用のＬＯＣＯＳ酸化膜、５０３はソースと
なるＮ型拡散層であり、５０４はドレインとなるＮ型拡
散層である。５０５はゲート電極であり、５０６は層間
絶縁膜である。５０７が強誘電体を用いた誘電体膜であ
り、下部電極５０８と上部電極５０９により挟まれ、キ
ャパシタを構成している。５１０は第２層間絶縁膜であ
り、５１１が配線電極である。FIG. 5 shows an example of a non-volatile semiconductor memory having a structure in which a ferroelectric film is laminated on a MOS semiconductor device.
In FIG. 5, 501 is a P-type silicon substrate,
Reference numeral 2 is a LOCOS oxide film for element isolation, 503 is an N-type diffusion layer that serves as a source, and 504 is an N-type diffusion layer that serves as a drain. Reference numeral 505 is a gate electrode, and 506 is an interlayer insulating film. Reference numeral 507 denotes a dielectric film using a ferroelectric substance, which is sandwiched by a lower electrode 508 and an upper electrode 509 to form a capacitor. Reference numeral 510 is a second interlayer insulating film, and 511 is a wiring electrode.
【０００４】[0004]
【発明が解決しようとする課題】このように能動素子の
形成された半導体基板上に、能動素子と隣接するように
平面的なキャパシタを形成した構造では、最低でもひと
つのキャパシタをひとつのメモリセル内におさめなけれ
ばならず、キャパシタの面積がメモリセルの面積で決定
される。また、キャパシタの下部電極５０８、誘電体膜
５０７、上部電極５０９をそれぞれ形成するための工程
が追加され、コスト増大を招く。In a structure in which a planar capacitor is formed so as to be adjacent to an active element on a semiconductor substrate on which an active element is thus formed, at least one capacitor corresponds to one memory cell. The area of the capacitor is determined by the area of the memory cell. In addition, a step for forming each of the lower electrode 508, the dielectric film 507, and the upper electrode 509 of the capacitor is added, which causes an increase in cost.
【０００５】また、下部電極５０８と上部電極５０９は
別個に形成されるので、下部電極５０８と誘電体５０７
との界面状態と、上部電極５０９と誘電体５０７との界
面状態とが異なり、電極にかける電圧の方向による、分
極等のキャパシタ特性の差異、すなわちキャパシタ特性
の非対称性が生じる。Since the lower electrode 508 and the upper electrode 509 are formed separately, the lower electrode 508 and the dielectric 507 are formed.
And the interface state between the upper electrode 509 and the dielectric 507 are different, and a difference in capacitor characteristics such as polarization depending on the direction of the voltage applied to the electrodes, that is, an asymmetry of the capacitor characteristics occurs.
【０００６】そこで本発明はこのような課題を解決する
もので、その目的とするところは、キャパシタの占有面
積を、同一容量を確保したまま縮小させ、あるいはメモ
リセル以外の領域をキャパシタとして使用してキャパシ
タの有効面積を稼ぐとともに、キャパシタ形成に伴う工
程増を削減し、また、キャパシタ特性の非対称性をなく
すことによって、高性能・高密度な半導体装置を低コス
トに提供することにある。Therefore, the present invention solves such a problem. An object of the present invention is to reduce the occupied area of the capacitor while ensuring the same capacitance, or to use a region other than the memory cell as a capacitor. By increasing the effective area of the capacitor, reducing the number of steps required for forming the capacitor, and eliminating the asymmetry of the capacitor characteristics, it is possible to provide a high-performance and high-density semiconductor device at low cost.
【０００７】[0007]
【課題を解決するための手段】誘電体が二つの電極によ
って挟まれた構造を有するキャパシタが、能動素子の形
成された同一半導体基板上に集積された半導体装置にお
いて、前記二つの電極の有するキャパシタンスに寄与す
る面のうち全て、もしくは一部が、半導体基板の主面と
垂直、もしくは垂直に近く配置されていることを特徴と
する。In a semiconductor device in which a capacitor having a structure in which a dielectric is sandwiched between two electrodes is integrated on the same semiconductor substrate on which an active element is formed, the capacitance of the two electrodes is All or part of the surface that contributes to the above is arranged perpendicularly or nearly perpendicularly to the main surface of the semiconductor substrate.
【０００８】また、誘電体が二つの電極によって挟まれ
た構造を有するキャパシタが、能動素子の形成された同
一半導体基板上に集積された半導体装置の製造方法にお
いて、前記二つの電極となる薄膜を形成する工程と、前
記二つの電極を同時にエッチングする工程と、その後、
前記誘電体を形成する工程とを含むことを特徴とする。Further, in a method of manufacturing a semiconductor device in which a capacitor having a structure in which a dielectric is sandwiched between two electrodes is integrated on the same semiconductor substrate on which an active element is formed, a thin film serving as the two electrodes is formed. A step of forming, a step of simultaneously etching the two electrodes, and then,
And a step of forming the dielectric.
【０００９】また、誘電体が二つの電極によって挟まれ
た構造を有するキャパシタが、能動素子の形成された同
一半導体基板上に集積された半導体装置において、前記
誘電体の全部、もしくは一部が、前記半導体基板上に形
成された配線層の、ボンディング・パッド以外の領域の
全部、もしくは一部を覆うことを特徴とする。In a semiconductor device in which a capacitor having a structure in which a dielectric is sandwiched between two electrodes is integrated on the same semiconductor substrate on which active elements are formed, all or part of the dielectric is It is characterized in that the wiring layer formed on the semiconductor substrate covers all or part of a region other than the bonding pad.
【００１０】[0010]
【実施例】図１（ａ）〜（ｄ）は本発明による半導体装
置の第１の実施例を示す主要工程断面図である。図１
（ｅ）および（ｆ）は本発明による半導体装置の第１の
実施例を示す主要平面図である。まず、図１にしたが
い、本発明の第１の実施例について説明する。ここでは
説明の都合上シリコン基板を用い、Ｎチャンネルトラン
ジスタを用いた例につき説明する。1 (a) to 1 (d) are sectional views showing main steps of a semiconductor device according to a first embodiment of the present invention. Figure 1
(E) and (f) are principal plan views showing the first embodiment of the semiconductor device according to the present invention. First, a first embodiment of the present invention will be described with reference to FIG. Here, for convenience of explanation, an example in which a silicon substrate is used and an N-channel transistor is used will be described.
【００１１】（図１（ａ））１０１はＰ型シリコン基板
であり、例えば２０Ω・ｃｍの比抵抗のウェハを用い
る。１０２は素子分離用の絶縁膜であり、例えば、従来
技術であるＬＯＣＯＳ法により二酸化シリコン膜を６０
００Å形成する。１０３はトランジスタのソースとなる
Ｎ型拡散層であり、例えばリンを８０ｋｅＶ、５×１０
15ｃｍー2イオン注入することによって形成する。１０４
はドレインとなるＮ型拡散層であり、１０３と同時に形
成する。１０５はゲート電極であり、例えばリンでドー
プされたポリシリコンを用いる。１０６は第１層間絶縁
膜であり、例えば化学的気相成長（以下、ＣＶＤとす
る）法によりリンガラスを４０００Å形成する。１０７
は配線電極であり、例えばタングステンを５０００Åス
パッタする。１０８は第２層間絶縁膜であり、例えばＣ
ＶＤ法により二酸化シリコンを８０００Å形成する。こ
の時、スピン・オン・グラス等を併用して十分に平坦化
することが望ましい。１０９はスルーホールの埋め込み
プラグであり、例えばタングステンをＣＶＤ法によって
形成する。(FIG. 1A) 101 is a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm is used. Reference numeral 102 denotes an insulating film for element isolation. For example, a silicon dioxide film 60 is formed by the conventional LOCOS method.
00Å Form. Reference numeral 103 is an N-type diffusion layer that serves as a source of the transistor, and is made of, for example, phosphorus at 80 keV and 5 × 10 5.
It is formed by implanting 15 cm −2 ions. 104
Is an N-type diffusion layer serving as a drain, and is formed simultaneously with 103. Reference numeral 105 denotes a gate electrode, which uses, for example, polysilicon doped with phosphorus. Reference numeral 106 denotes a first interlayer insulating film, which is formed by a chemical vapor deposition (hereinafter referred to as CVD) method to form phosphorous glass at a thickness of 4000 liters. 107
Is a wiring electrode, for example, tungsten is sputtered at 5000 Å. 108 is a second interlayer insulating film, for example, C
8000Å of silicon dioxide is formed by the VD method. At this time, it is desirable to use a spin-on-glass or the like together to sufficiently flatten the surface. Reference numeral 109 denotes an embedded plug of a through hole, which is made of, for example, tungsten by the CVD method.
【００１２】１１０は本発明の趣旨による誘電体であ
り、例えばチタン酸ジルコン酸鉛（Pb(Ti0.6Zr0.4)O3）
を２μｍスパッタ法により形成し、フォト・リソグラフ
ィにより所定のパターンに形成する。この時、誘電体１
１０の側壁がキャパシタの電極と接する面となるので、
誘電体１１０の高さ、すなわち膜形成時の膜厚が大きい
方がキャパシタの有効面積が大きくなる。また、誘電体
１１０の幅がキャパシタの電極間隔となるので、できる
だけ小さくすることが望ましい。また、キャパシタの電
極は誘電体１１０の側壁にのみ形成するので、誘電体１
１０はキャパシタの電極と配線層、あるいは拡散層とを
接続する埋め込みプラグの近傍に形成されるのが望まし
い。Reference numeral 110 denotes a dielectric substance according to the gist of the present invention, for example, lead zirconate titanate (Pb (Ti 0.6 Zr 0.4 ) O 3 ).
Is formed by a 2 μm sputtering method and formed into a predetermined pattern by photolithography. At this time, dielectric 1
Since the side wall of 10 is the surface in contact with the electrode of the capacitor,
The larger the height of the dielectric 110, that is, the larger the film thickness at the time of film formation, the larger the effective area of the capacitor. Further, since the width of the dielectric 110 becomes the electrode interval of the capacitor, it is desirable to make it as small as possible. In addition, since the capacitor electrodes are formed only on the side walls of the dielectric 110, the dielectric 1
It is desirable that 10 is formed in the vicinity of a buried plug that connects the electrode of the capacitor and the wiring layer or the diffusion layer.
【００１３】（図１（ｂ））次に、キャパシタの電極と
なる膜１１１として、例えば白金をスパッタ法により２
０００Å形成する。(FIG. 1 (b)) Next, as the film 111 to be the electrode of the capacitor, for example, platinum is sputtered to form a film 2.
000Å form.
【００１４】（図１（ｃ））次に、異方性エッチングに
よって、全面エッチングを行なう。本実施例において
は、例えば不活性ガスであるアルゴンをイオン・ソース
として用いたイオン・ビーム・エッチングを用いて、半
導体基板１０１と垂直方向にビームを入射させ全面エッ
チングする。すると、異方性エッチングであるので、誘
電体１１０の側壁はエッチングされずに電極１１２、及
び１１３が残り、誘電体１１０近傍の埋め込みプラグ１
０９とは自己整合的に接続される。また、本実施例にお
いては不活性ガスを用いてエッチングしたので、キャパ
シタの電極となる膜１１１のうち第２層間絶縁膜１０８
上の部位はエッチングされた後誘電体１１０の側壁に再
付着する。したがって、キャパシタの電極となる膜１１
１の付きまわりが悪く、誘電体１１０の側壁部に十分に
堆積されていなかったとしても、再付着によって補填さ
れるので、キャパシタの電極１１２、及び１１３は十分
な厚みをもって形成することができる。また、この時誘
電体１１０を、図１（ｅ）や図１（ｆ）に示すように、
閉曲線をもったパターンとしておけば、二つのキャパシ
タ電極１１２、及び１１３を分離する工程は必要ない。
図１（ｅ）および図１（ｆ）において１１５は一方の電
極と配線層とを接続する埋め込みプラグである。(FIG. 1 (c)) Next, the entire surface is etched by anisotropic etching. In this embodiment, ion beam etching using, for example, an inert gas, argon, as an ion source is used, and a beam is incident in the direction perpendicular to the semiconductor substrate 101 to etch the entire surface. Then, since the etching is anisotropic etching, the sidewalls of the dielectric 110 are not etched and the electrodes 112 and 113 remain, and the embedded plug 1 near the dielectric 110 is etched.
09 are connected in a self-aligned manner. In addition, since the etching is performed using an inert gas in the present embodiment, the second interlayer insulating film 108 of the film 111 that will be the electrode of the capacitor is used.
The upper portion is redeposited on the sidewall of the dielectric 110 after being etched. Therefore, the film 11 serving as the capacitor electrode
Even if 1 is not attached well and is not sufficiently deposited on the side wall of the dielectric 110, it is compensated by redeposition, so that the electrodes 112 and 113 of the capacitor can be formed with a sufficient thickness. Further, at this time, as shown in FIG. 1E and FIG.
If the pattern has a closed curve, the step of separating the two capacitor electrodes 112 and 113 is not necessary.
In FIGS. 1E and 1F, 115 is a buried plug that connects one electrode to the wiring layer.
【００１５】（図１（ｄ））最後にパッシベーション１
１４として例えば窒化シリコン（SiNx）をＣＶＤ法によ
り１μｍ形成する。(FIG. 1 (d)) Finally, passivation 1
As 14, for example, silicon nitride (SiN x ) is formed to a thickness of 1 μm by the CVD method.
【００１６】以上をもって本発明の第１の実施例とす
る。The above is the first embodiment of the present invention.
【００１７】このように、キャパシタの誘電体１１１を
半導体基板１０１に垂直に形成し、その両側に二つの電
極を形成すれば、図５の従来の技術で示したような、半
導体基板に平行に配置した場合と比較して、同一の電極
面積、同一の電極間隔を取った場合、キャパシタの占有
面積を小さくすることができる。本実施例では、誘電体
１０７の高さを２μｍとしたが、更に高くすることによ
って、キャパシタの占有面積を大きくすることなく、キ
ャパシタの容量を大きくすることができる。また、キャ
パシタの電極１１２と１１３を同時に、しかもフォトリ
ソグラフィ工程を必要とせずに形成するので、工程数を
削減することができ、また、電極と誘電体１１１との界
面状態は対称的であり、電極にかける電圧の方向によ
る、分極、誘電率、誘電正接等のキャパシタ特性に差異
はなかった。As described above, if the dielectric 111 of the capacitor is formed vertically on the semiconductor substrate 101 and two electrodes are formed on both sides thereof, it becomes parallel to the semiconductor substrate as shown in the prior art of FIG. When the same electrode area and the same electrode interval are provided, the occupied area of the capacitor can be reduced as compared with the case where they are arranged. In this embodiment, the height of the dielectric 107 is set to 2 μm, but by further increasing the height, the capacitance of the capacitor can be increased without increasing the occupied area of the capacitor. Further, since the electrodes 112 and 113 of the capacitor are formed at the same time and without requiring a photolithography process, the number of processes can be reduced, and the interface state between the electrode and the dielectric 111 is symmetrical. There was no difference in the capacitor characteristics such as polarization, dielectric constant and dielectric loss tangent depending on the direction of the voltage applied to the electrodes.
【００１８】図２は本発明による半導体装置の第２の実
施例を示す主要断面図である。図２にしたがい、本発明
の第２の実施例について説明する。ここでも説明の都合
上シリコン基板を用い、Ｎチャンネルトランジスタを用
いた例につき説明する。FIG. 2 is a main sectional view showing a second embodiment of the semiconductor device according to the present invention. A second embodiment of the present invention will be described with reference to FIG. Here, for convenience of explanation, an example using a silicon substrate and an N-channel transistor will be described.
【００１９】２０１はＰ型シリコン基板であり、例えば
２０Ω・ｃｍの比抵抗のウェハを用いる。２０２は素子
分離用の絶縁膜であり、例えば、従来技術であるＬＯＣ
ＯＳ法により二酸化シリコン（SiO2）膜を６０００Å形
成する。２０３はトランジスタのソースとなるＮ型拡散
層であり、例えばリンを８０ｋｅＶ５×１０15ｃｍー2イ
オン注入することによって形成する。２０４はドレイン
となるＮ型拡散層であり、２０３と同時に形成する。２
０５はゲート電極であり、例えばリンでドープされたポ
リシリコンを用いる。２０６は第１層間絶縁膜であり、
例えばＣＶＤ法によりリンガラスを４０００Å形成す
る。Reference numeral 201 denotes a P-type silicon substrate, which uses a wafer having a specific resistance of 20 Ω · cm, for example. Reference numeral 202 denotes an insulating film for element isolation, for example, LOC which is a conventional technique.
A silicon dioxide (SiO 2 ) film of 6000Å is formed by the OS method. 203 is an N-type diffusion layer serving as the source of the transistor, for example, is formed by phosphorus 80keV5 × 10 15 cm -2 ion implantation. Reference numeral 204 is an N-type diffusion layer that serves as a drain, and is formed simultaneously with 203. Two
Reference numeral 05 denotes a gate electrode, which uses, for example, polysilicon doped with phosphorus. 206 is a first interlayer insulating film,
For example, phosphorous glass of 4000 Å is formed by the CVD method.
【００２０】２０７は本発明の趣旨によるキャパシタの
誘電体であり、例えば高誘電率のチタン酸ストロンチウ
ム（SrTiO3）を幅０．５μｍ、高さ２μｍに形成する。
２０８及び２０９は本発明の趣旨によるキャパシタの電
極であり、例えば白金を２０００Åスパッタした後、従
来のフォト・リソグラフィ技術によって２０８と２０９
を所望のパターンに形成する。Reference numeral 207 is a dielectric of a capacitor according to the present invention. For example, strontium titanate (SrTiO 3 ) having a high dielectric constant is formed to have a width of 0.5 μm and a height of 2 μm.
Numerals 208 and 209 are electrodes of a capacitor according to the gist of the present invention.
Are formed into a desired pattern.
【００２１】２１０は第２の層間絶縁膜であり、例え
ば、ＣＶＤ法によって、二酸化シリコンを２０００Å形
成する。２１１は配線電極であり、例えばアルミニウム
を５０００Åスパッタする。Reference numeral 210 denotes a second interlayer insulating film, which is formed with 2000 Å of silicon dioxide by the CVD method, for example. Reference numeral 211 is a wiring electrode, for example, aluminum is sputtered at 5000 Å.
【００２２】以上をもって、本発明の第２の実施例とす
る。The above is the second embodiment of the present invention.
【００２３】このように、キャパシタの誘電体２０７を
半導体基板２０１に垂直に形成し、その両側に二つの電
極を形成すれば、図５の従来の技術で示したような、半
導体基板に平行に配置した場合と比較して、同一の電極
面積、同一の電極間隔を取った場合、キャパシタの占有
面積を小さくすることができる。本実施例では、誘電体
２０７の高さを２μｍとしたが、更に高くすることによ
って、キャパシタの占有面積を大きくすることなく、キ
ャパシタの容量を大きくすることができる。また、キャ
パシタの電極２０８と２０９を同時に形成するので、電
極と誘電体２０７との界面状態は対称的であり、電極に
かける電圧の方向による、分極、誘電率、誘電正接等の
キャパシタ特性に差異はなかった。As described above, when the capacitor dielectric 207 is formed vertically on the semiconductor substrate 201 and two electrodes are formed on both sides thereof, the capacitor dielectric 207 is formed parallel to the semiconductor substrate as shown in the prior art of FIG. When the same electrode area and the same electrode interval are provided, the occupied area of the capacitor can be reduced as compared with the case where they are arranged. In the present embodiment, the height of the dielectric 207 is set to 2 μm, but by further increasing the height, the capacitance of the capacitor can be increased without increasing the occupied area of the capacitor. Further, since the electrodes 208 and 209 of the capacitor are formed at the same time, the interface state between the electrode and the dielectric 207 is symmetrical, and the capacitor characteristics such as polarization, dielectric constant, and dielectric loss tangent differ depending on the direction of the voltage applied to the electrode. There was no.
【００２４】図３（ａ）〜（ｄ）は本発明による半導体
装置の製造方法の実施例（以下、第３の実施例とす
る。）を示す主要工程断面図である。図３にしたがい、
本発明の第３の実施例について説明する。ここでも説明
の都合上シリコン基板を用い、Ｎチャンネルトランジス
タを用いた例につき説明する。FIGS. 3A to 3D are cross-sectional views of main steps showing an embodiment (hereinafter, referred to as a third embodiment) of the method for manufacturing a semiconductor device according to the present invention. According to FIG.
A third embodiment of the present invention will be described. Here, for convenience of explanation, an example using a silicon substrate and an N-channel transistor will be described.
【００２５】（図３（ａ））３０１はＰ型シリコン基板
であり、例えば２０Ω・ｃｍの比抵抗のウェハを用い
る。３０２は素子分離用の絶縁膜であり、例えば、従来
技術であるＬＯＣＯＳ法により二酸化シリコン膜を６０
００Å形成する。３０３はトランジスタのソースとなる
Ｎ型拡散層であり、例えばリンを８０ｋｅＶ、５×１０
15ｃｍー2イオン注入することによって形成する。３０４
はドレインとなるＮ型拡散層であり、３０３と同時に形
成する。３０５はゲート電極であり、例えばリンでドー
プされたポリシリコンを用いる。３０６は第１層間絶縁
膜であり、例えばＣＶＤ法によりリンガラスを４０００
Å形成する。(FIG. 3A) 301 is a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm is used. Reference numeral 302 is an insulating film for element isolation. For example, a silicon dioxide film 60 is formed by the conventional LOCOS method.
00Å Form. Reference numeral 303 denotes an N-type diffusion layer which serves as a source of the transistor, and is made of phosphorus, for example, at 80 keV and 5 × 10 5.
It is formed by implanting 15 cm −2 ions. 304
Is an N-type diffusion layer serving as a drain, and is formed simultaneously with 303. A gate electrode 305 is made of, for example, polysilicon doped with phosphorus. Reference numeral 306 denotes a first interlayer insulating film, which is made of phosphorus glass, for example, by a CVD method.
Å Form.
【００２６】（図３（ｂ））次に、キャパシタの電極と
して、例えば白金をスパッタ法により３μｍ形成し、フ
ォトリソグラフィ技術によって、所望のパターンに形成
する。(FIG. 3 (b)) Next, for example, platinum is formed to a thickness of 3 μm as a capacitor electrode by a sputtering method, and is formed into a desired pattern by a photolithography technique.
【００２７】この時、電極３０７と３０８との間の距離
がキャパシタの電極間隔となるので、キャパシタ容量を
大きくするにはなるべく小さくすることが望ましい。本
実施例においては、電極３０７と３０８との間隔を１μ
ｍとした。また、電極３０７および３０８の膜厚がキャ
パシタの容量に寄与する面の一辺となるので、なるべく
厚くすることが望ましい。At this time, since the distance between the electrodes 307 and 308 becomes the electrode interval of the capacitor, it is desirable to make it as small as possible in order to increase the capacitance of the capacitor. In this embodiment, the distance between the electrodes 307 and 308 is 1 μm.
m. Further, since the film thickness of the electrodes 307 and 308 is one side of the surface that contributes to the capacitance of the capacitor, it is desirable to make it as thick as possible.
【００２８】（図３（ｃ））次に、誘電体３０９とし
て、例えばチタン酸ジルコン酸鉛（Pb(Ti0.6Zr0.4)O3）
をゾル−ゲル法により形成する。この時、電極３０７と
３０８との狭い隙間に誘電体３０９を充填する必要があ
るので、誘電体３０９の形成方法としては、ゾル−ゲル
法やＣＶＤ法等によることが望ましい。その後、誘電体
３０９を６００℃で焼結し、フォトリソグラフィ技術を
用いて、所望のパターンに形成する。フォトリソグラフ
ィを用いずに、全面エッチバックによって電極３０７及
び３０８との隙間にのみ、誘電体３０９を残すことも可
能である。(FIG. 3C) Next, as the dielectric 309, for example, lead zirconate titanate (Pb (Ti 0.6 Zr 0.4 ) O 3 ) is used.
Are formed by the sol-gel method. At this time, since it is necessary to fill the narrow gap between the electrodes 307 and 308 with the dielectric 309, the method of forming the dielectric 309 is preferably a sol-gel method, a CVD method, or the like. After that, the dielectric 309 is sintered at 600 ° C. and formed into a desired pattern by using the photolithography technique. It is also possible to leave the dielectric 309 only in the gaps between the electrodes 307 and 308 by etching back the entire surface without using photolithography.
【００２９】（図３（ｄ））次に、第２の層間絶縁膜３
１０として、例えば二酸化シリコンをＣＶＤ法により２
０００Å形成し、必要な箇所に開孔する。その後、配線
電極３１１として例えばアルミニウムを１μｍ形成し、
所望のパターンに形成する。(FIG. 3D) Next, the second interlayer insulating film 3 is formed.
10 is, for example, 2 using silicon dioxide by the CVD method.
Form 000Å and open holes where necessary. After that, for example, aluminum is formed to a thickness of 1 μm as the wiring electrode 311.
Form into a desired pattern.
【００３０】以上をもって、本発明の第３の実施例とす
る。The above is the third embodiment of the present invention.
【００３１】このように、電極３０７と３０８を同時に
形成することによって、キャパシタに必要な二つの電極
を、一度のフォトリソグラフィによって形成することが
できるので、製造工程を短縮することができる。また、
電極３０７と３０８を形成した後に誘電体３０９を形成
するので、誘電体３０９の配向性を、電極の配向性によ
って制御することが可能である。By thus forming the electrodes 307 and 308 at the same time, the two electrodes required for the capacitor can be formed by one-time photolithography, so that the manufacturing process can be shortened. Also,
Since the dielectric 309 is formed after forming the electrodes 307 and 308, the orientation of the dielectric 309 can be controlled by the orientation of the electrodes.
【００３２】図４は本発明による半導体装置の実施例
（以下、第４の実施例とする。）を示す主要断面図であ
る。図４にしたがい、本発明の第４の実施例について説
明する。ここでも説明の都合上シリコン基板を用い、Ｎ
チャンネルトランジスタを用いた例につき説明する。FIG. 4 is a main sectional view showing an embodiment (hereinafter, referred to as a fourth embodiment) of a semiconductor device according to the present invention. A fourth embodiment of the present invention will be described with reference to FIG. Again, for convenience of explanation, a silicon substrate is used, and N
An example using a channel transistor will be described.
【００３３】４０１はＰ型シリコン基板であり、例えば
２０Ω・ｃｍの比抵抗のウェハを用いる。４０２は素子
分離用の絶縁膜であり、例えば、従来技術であるＬＯＣ
ＯＳ法により二酸化シリコン膜を６０００Å形成する。
４０３はトランジスタのソースとなるＮ型拡散層であ
り、例えばリンを８０ｋｅＶ５×１０15ｃｍー2イオン注
入することによって形成する。４０４はドレインとなる
Ｎ型拡散層であり、４０３と同時に形成する。４０５は
ゲート電極であり、例えばリンでドープされたポリシリ
コンを用いる。４０６は第１層間絶縁膜であり、例えば
ＣＶＤ法によりリンガラスを４０００Å形成する。４０
７は配線電極であり、例えばタングステンを５０００Å
スパッタする。４０８は第２層間絶縁膜であり、例えば
ＣＶＤ法により二酸化シリコンを８０００Å形成する。
この時、スピン・オン・グラス等を併用して十分に平坦
化することが望ましい。４０９はスルーホールの埋め込
みプラグであり、例えばタングステンをＣＶＤ法によっ
て形成する。Reference numeral 401 denotes a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm is used. Reference numeral 402 is an insulating film for element isolation, for example, LOC which is a conventional technique.
A 6000Å silicon dioxide film is formed by the OS method.
403 is an N-type diffusion layer serving as the source of the transistor, for example, is formed by phosphorus 80keV5 × 10 15 cm -2 ion implantation. Reference numeral 404 is an N-type diffusion layer that serves as a drain, and is formed simultaneously with 403. A gate electrode 405 is made of, for example, polysilicon doped with phosphorus. 406 is a first interlayer insulating film, for example, phosphorus glass is formed in a thickness of 4000 Å by a CVD method. 40
Reference numeral 7 is a wiring electrode, for example, tungsten of 5000 Å
Sputter. Reference numeral 408 denotes a second interlayer insulating film, which is formed with silicon dioxide of 8000 Å by, for example, a CVD method.
At this time, it is desirable to use a spin-on-glass or the like together to sufficiently flatten the surface. Reference numeral 409 is a plug for filling a through hole, and tungsten is formed by a CVD method, for example.
【００３４】４１０及び４１１は本発明の趣旨による、
キャパシタの二つの電極であり、例えば白金をスパッタ
法により４μｍ形成した後、４１０及び４１１を同時
に、所望のパターンに形成する。４１２は本発明の趣旨
によるキャパシタの誘電体であり、例えばチタン酸ジル
コン酸鉛（Pb(Ti0.6Zr0.4)O3）をゾル−ゲル法により形
成し、５００℃で焼結する。Reference numerals 410 and 411 represent the gist of the present invention.
Two electrodes of a capacitor, for example, platinum is formed to a thickness of 4 μm by a sputtering method, and then 410 and 411 are simultaneously formed into a desired pattern. Reference numeral 412 is a capacitor dielectric according to the gist of the present invention. For example, lead zirconate titanate (Pb (Ti 0.6 Zr 0.4 ) O 3 ) is formed by a sol-gel method and sintered at 500 ° C.
【００３５】以上をもって本発明の第４の実施例とす
る。The above is the fourth embodiment of the present invention.
【００３６】このように、誘電体４１２のキャパシタン
スに寄与する部分を半導体基板４０１に垂直に形成した
ことによって、第１の実施例と同様に、キャパシタの占
有面積を小さくすることができる。またさらに、誘電体
４１２をキャパシタ部分だけでなく素子全体を覆うよう
に形成したことによって、パッシベーションとしての効
果が得られるので、パッシベーション形成にともなう工
程を削減することができる。Since the portion of the dielectric 412 that contributes to the capacitance is formed perpendicularly to the semiconductor substrate 401 in this manner, the occupied area of the capacitor can be reduced as in the first embodiment. Furthermore, since the dielectric 412 is formed so as to cover not only the capacitor portion but also the entire element, an effect as passivation can be obtained, so that the steps involved in passivation formation can be reduced.
【００３７】[0037]
【発明の効果】本発明によれば、キャパシタの誘電体の
キャパシタンスに寄与する面を、半導体基板と垂直とし
たことにより、キャパシタの占有面積を小さくできると
いう効果を有する。According to the present invention, since the surface of the capacitor that contributes to the capacitance of the capacitor is perpendicular to the semiconductor substrate, the area occupied by the capacitor can be reduced.
【００３８】また、本発明によれば、キャパシタの二つ
の電極を、誘電体形成の前に、しかも同時に形成したこ
とにより、キャパシタ形成に関する工程増を抑制でき、
また、誘電体の結晶配向性を電極の配向性によって制御
することができ、さらに、キャパシタの誘電率などの特
性の印加電圧の方向による差異、すなわち非対称性を無
くすことができるという効果を有する。Further, according to the present invention, since the two electrodes of the capacitor are formed at the same time before the dielectric is formed, it is possible to suppress an increase in the number of steps for forming the capacitor.
Further, the crystal orientation of the dielectric can be controlled by the orientation of the electrodes, and further, the difference in characteristics such as the dielectric constant of the capacitor depending on the direction of the applied voltage, that is, the asymmetry can be eliminated.
【００３９】また、本発明によれば、キャパシタの誘電
体の一部をパッシベーションとしたことにより、工程数
の削減を図ることができるという効果を有する。Further, according to the present invention, since a part of the dielectric of the capacitor is passivated, the number of steps can be reduced.
【図１】 本発明の第１の実施例の半導体装置の、主要
工程断面図、及び平面図。FIG. 1 is a sectional view showing a main step and a plan view of a semiconductor device according to a first example of the present invention.
【図２】 本発明の第２の実施例の半導体装置の、主要
断面図。FIG. 2 is a main sectional view of a semiconductor device according to a second embodiment of the present invention.
【図３】 本発明の第３の実施例の半導体装置の製造方
法の、主要工程断面図。FIG. 3 is a sectional view showing main steps in a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
【図４】 本発明の第４の実施例の半導体装置の、主要
断面図。FIG. 4 is a main sectional view of a semiconductor device according to a fourth embodiment of the present invention.
【図５】 従来の技術による、半導体装置の主要断面
図。FIG. 5 is a main cross-sectional view of a semiconductor device according to a conventional technique.
１０１ 半導体基板 １０２ 素子分離膜 １０３ ソース領域 １０４ ドレイン領域 １０５ ゲート電極 １０６ 第１層間絶縁膜 １０７ 配線電極 １０８ 第２層間絶縁膜 １０９ 埋め込みプラグ １１０ 誘電体 １１１ キャパシタ電極となる膜 １１２ キャパシタ電極 １１３ キャパシタ電極 １１４ パッシベーション １１５ 埋め込みプラグ ２０１ 半導体基板 ２０２ 素子分離膜 ２０３ ソース領域 ２０４ ドレイン領域 ２０５ ゲート電極 ２０６ 第１層間絶縁膜 ２０７ 誘電体 ２０８ キャパシタ電極 ２０９ キャパシタ電極 ２１０ 第２層間絶縁膜 ２１１ 配線電極 ３０１ 半導体基板 ３０２ 素子分離膜 ３０３ ソース領域 ３０４ ドレイン領域 ３０５ ゲート電極 ３０６ 第１層間絶縁膜 ３０７ キャパシタ電極 ３０８ キャパシタ電極 ３０９ 誘電体 ３１０ 第２層間絶縁膜 ３１１ 配線電極 ４０１ 半導体基板 ４０２ 素子分離膜 ４０３ ソース領域 ４０４ ドレイン領域 ４０５ ゲート電極 ４０６ 第１層間絶縁膜 ４０７ 配線電極 ４０８ 第２層間絶縁膜 ４０９ 埋め込みプラグ ４１０ キャパシタ電極 ４１１ キャパシタ電極 ４１２ 誘電体 ５０１ 半導体基板 ５０２ 素子分離膜 ５０３ ソース領域 ５０４ ドレイン領域 ５０５ ゲート電極 ５０６ 第１層間絶縁膜 ５０７ 強誘電体膜 ５０８ 下部電極 ５０９ 上部電極 ５１０ 第２層間絶縁膜 ５１１ 配線電極 Reference Signs List 101 semiconductor substrate 102 element isolation film 103 source region 104 drain region 105 gate electrode 106 first interlayer insulating film 107 wiring electrode 108 second interlayer insulating film 109 embedded plug 110 dielectric 111 film to be a capacitor electrode 112 capacitor electrode 113 capacitor electrode 114 Passivation 115 embedded plug 201 semiconductor substrate 202 element isolation film 203 source region 204 drain region 205 gate electrode 206 first interlayer insulating film 207 dielectric 208 capacitor electrode 209 capacitor electrode 210 second interlayer insulating film 211 wiring electrode 301 semiconductor substrate 302 device isolation Film 303 Source region 304 Drain region 305 Gate electrode 306 First interlayer insulating film 307 Capacitor electrode 308 Capacitor electrode 309 Dielectric 310 second interlayer insulating film 311 wiring electrode 401 semiconductor substrate 402 element isolation film 403 source region 404 drain region 405 gate electrode 406 first interlayer insulating film 407 wiring electrode 408 second interlayer insulating film 409 embedded plug 410 capacitor electrode 411 capacitor electrode 412 Dielectric 501 Semiconductor substrate 502 Element isolation film 503 Source region 504 Drain region 505 Gate electrode 506 First interlayer insulating film 507 Ferroelectric film 508 Lower electrode 509 Upper electrode 510 Second interlayer insulating film 511 Wiring electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/792 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 29/792
Claims (5)
造を有するキャパシタが、能動素子の形成された同一半
導体基板上に集積された半導体装置において、前記二つ
の電極の有するキャパシタンスに寄与する面のうち全
て、もしくは一部が、半導体基板の主面と垂直、もしく
は４５度以上の角をなして配置されていることを特徴と
する半導体装置。1. In a semiconductor device in which a capacitor having a structure in which a dielectric is sandwiched between two electrodes is integrated on the same semiconductor substrate on which an active element is formed, a surface that contributes to the capacitance of the two electrodes. A semiconductor device, characterized in that all or part of them is arranged perpendicular to the main surface of the semiconductor substrate or at an angle of 45 degrees or more.
造を有するキャパシタが、能動素子の形成された同一半
導体基板上に集積された半導体装置の製造方法におい
て、前記二つの電極となる薄膜を形成する工程と、前記
薄膜をエッチングして前記二つの電極を同時に形成する
工程と、その後、前記誘電体を形成する工程とを含むこ
とを特徴とする半導体装置の製造方法。2. In a method of manufacturing a semiconductor device, wherein a capacitor having a structure in which a dielectric is sandwiched between two electrodes is integrated on the same semiconductor substrate on which an active element is formed, a thin film serving as the two electrodes is formed. A method of manufacturing a semiconductor device, comprising: a step of forming, a step of simultaneously etching the thin film to form the two electrodes, and a step of forming the dielectric.
造を有するキャパシタが、能動素子の形成された同一半
導体基板上に集積された半導体装置において、前記誘電
体の全部、もしくは一部が、前記半導体基板上に形成さ
れた配線層の、ボンディング・パッド以外の領域の全
部、もしくは一部を覆うことを特徴とする半導体装置。3. In a semiconductor device in which a capacitor having a structure in which a dielectric is sandwiched between two electrodes is integrated on the same semiconductor substrate on which an active element is formed, all or part of the dielectric is A semiconductor device, characterized in that the wiring layer formed on the semiconductor substrate covers all or part of a region other than a bonding pad.
構造を持つセラミックスであることを特徴とする請求項
１及び請求項３記載の半導体装置。4. The semiconductor device according to claim 1, wherein the dielectric is a ceramic having a perovskite type crystal structure.
セラミックスが、チタン酸ジルコン酸鉛（Pb(TixZr1-x)
O3）、ランタン含有のチタン酸ジルコン酸鉛（(Pb1-yLa
y)(TixZr1-x)O3）、チタン酸ストロンチウム（SrTi
O3）、チタン酸ストロンチウムバリウム（(Sr1-yBay)Ti
O3）のうち何れかを主たる成分とすることを特徴とする
請求項１及び請求項３記載の半導体装置。5. The ceramic having a perovskite type crystal structure is lead zirconate titanate (Pb (Ti x Zr 1-x ).
O 3 ), lanthanum-containing lead zirconate titanate ((Pb 1-y La
y ) (Ti x Zr 1-x ) O 3 ), strontium titanate (SrTi
O 3), barium strontium titanate ((Sr 1-y Ba y ) Ti
4. The semiconductor device according to claim 1, wherein any one of O 3 ) is a main component.
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|---|---|---|---|
| JP14951992A JP3250257B2 (en) | 1992-06-09 | 1992-06-09 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14951992A JP3250257B2 (en) | 1992-06-09 | 1992-06-09 | Semiconductor device and manufacturing method thereof |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11163061A Division JP2000004006A (en) | 1999-06-09 | 1999-06-09 | Semiconductor device |
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| JPH05343615A true JPH05343615A (en) | 1993-12-24 |
| JP3250257B2 JP3250257B2 (en) | 2002-01-28 |
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| Country | Link |
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| JP (1) | JP3250257B2 (en) |
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