JPH0328473U - - Google Patents
Info
- Publication number
- JPH0328473U JPH0328473U JP8876589U JP8876589U JPH0328473U JP H0328473 U JPH0328473 U JP H0328473U JP 8876589 U JP8876589 U JP 8876589U JP 8876589 U JP8876589 U JP 8876589U JP H0328473 U JPH0328473 U JP H0328473U
- Authority
- JP
- Japan
- Prior art keywords
- dut
- output
- adjustment dac
- full
- linearity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
第1図は本考案に係るDA変換器の直線性試験
装置の一実施例を示す図、第2図はDUTに与え
るデータとエンコーダの出力関係を示す図である
。
1……DUT、2……ゼロ調整用DAC、3…
…フルスケール調整用DAC、C1〜Cn……コ
ンパレータ、4……エンコーダ、5……CPU。
FIG. 1 is a diagram showing an embodiment of a linearity testing device for a DA converter according to the present invention, and FIG. 2 is a diagram showing the relationship between data given to a DUT and the output of an encoder. 1...DUT, 2...Zero adjustment DAC, 3...
...Full scale adjustment DAC, C1 to Cn ...Comparator, 4...Encoder, 5...CPU.
Claims (1)
スケール調整用DACの出力端子の間に接続され
、等しい抵抗値の抵抗が多数段直列に接続された
抵抗分圧器と、 前記抵抗分圧器の各段の分圧電圧と、被測定対
象のDA変換器(以下、DUTと言う)の出力S
1との大小とをそれぞれ比較する複数個のコンパ
レータと、 前記各コンパレータの出力信号を並列に導入し
これをコード信号へ変換するエンコーダと、 DUTにゼロ入力を加えた際に出力されるオフ
セツト電圧と同値のアナログ信号を出力するゼロ
調整用DACと、 DUTにフルスケール入力を加えた際のDUT
の出力電圧と同値のアナログ信号を出力するフル
スケール調整用DACと、 理想直線性のデータを格納し、このデータとエ
ンコーダの出力値を比較することでDUTの直線
性誤差を演算するコンピユータと、 を備えたDA変換器の直線性試験装置。[Claims for Utility Model Registration] A resistor voltage divider connected between the output terminal of a zero adjustment DAC and the output terminal of a full scale adjustment DAC, which will be described later, and in which multiple stages of resistors with equal resistance values are connected in series. , the divided voltages of each stage of the resistive voltage divider and the output S of the DA converter (hereinafter referred to as DUT) to be measured.
1, an encoder that introduces the output signal of each comparator in parallel and converts it into a code signal, and an offset voltage that is output when zero input is applied to the DUT. A zero adjustment DAC that outputs an analog signal with the same value as the DUT when full-scale input is applied to the DUT.
A full-scale adjustment DAC that outputs an analog signal with the same value as the output voltage of the DUT; a computer that stores ideal linearity data and calculates the linearity error of the DUT by comparing this data with the encoder output value; A linearity testing device for DA converters.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8876589U JPH0328473U (en) | 1989-07-28 | 1989-07-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8876589U JPH0328473U (en) | 1989-07-28 | 1989-07-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0328473U true JPH0328473U (en) | 1991-03-20 |
Family
ID=31638358
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8876589U Pending JPH0328473U (en) | 1989-07-28 | 1989-07-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0328473U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130100508A (en) * | 2012-03-02 | 2013-09-11 | 주식회사 두원공조 | Air conditioner for vehicle |
-
1989
- 1989-07-28 JP JP8876589U patent/JPH0328473U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130100508A (en) * | 2012-03-02 | 2013-09-11 | 주식회사 두원공조 | Air conditioner for vehicle |
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