JPH03283588A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH03283588A
JPH03283588A JP2083859A JP8385990A JPH03283588A JP H03283588 A JPH03283588 A JP H03283588A JP 2083859 A JP2083859 A JP 2083859A JP 8385990 A JP8385990 A JP 8385990A JP H03283588 A JPH03283588 A JP H03283588A
Authority
JP
Japan
Prior art keywords
resistors
resistor
conductor
trimming
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2083859A
Other languages
Japanese (ja)
Inventor
Mitsuru Murata
満 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Lighting and Technology Corp
Original Assignee
Toshiba Lighting and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Lighting and Technology Corp filed Critical Toshiba Lighting and Technology Corp
Priority to JP2083859A priority Critical patent/JPH03283588A/en
Publication of JPH03283588A publication Critical patent/JPH03283588A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To easily perform a trimming work in short time by laminating first, second resistors through an insulting layer in a partly overlapping manner, simultaneously trimming the overlapped resistors to vary the ratio of resistances of both the resistors, and deciding a base voltage. CONSTITUTION:A second resistor 29 is connected in parallel with a conductor 24 together with a first resistor 27. Both the resistors 27, 29 are linearly symmetrical as seen in plane, and partly overlapped. The other end of the resistor 29 is connected to a conductor 23 through a conductor 31. When the base voltage of a transistor 22 is decided, if the overlapped parts of the resistors 27, 29 are trimmed, the resistances of the resistors 27, 29 are increased, but the increasing width R1 of the resistance of the resistor 27 is larger than that R2 of the resistance of the resistor 29, and R1> R2. Thus, the ratio of the resistances of the resistor 27 to the resistor 29 can be easily decided by one trimming.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は混成集積回路に関わり、特にレーザによるトリ
ミングに適した混成集積回路に関わる。
DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION Field of Industrial Application The present invention relates to hybrid integrated circuits, and more particularly to hybrid integrated circuits suitable for laser trimming.

(従来の技術) 一般に、混成集積回路としては、絶縁基板上に抵抗ペー
ストの印刷、焼成工程を施す厚膜技術により抵抗体等を
設けた構成のものが知られている。こうした混成集積回
路では、電子部品等を実装した後、機能トリミング用抵
抗体をレーザ等によりトリミングを行い、用途に応じた
抵抗値に設定する操作を行っている。
(Prior Art) Generally, as a hybrid integrated circuit, one having a structure in which a resistor and the like are provided by a thick film technique in which a resistor paste is printed and baked on an insulating substrate is known. In such a hybrid integrated circuit, after electronic components and the like are mounted, the functional trimming resistor is trimmed using a laser or the like to set the resistance value according to the intended use.

第2図は、従来の混成集積回路の一例を示す。FIG. 2 shows an example of a conventional hybrid integrated circuit.

図中の1は、絶縁基板としてのセラミック基板である。1 in the figure is a ceramic substrate as an insulating substrate.

この基板上には、トランジスタ2のエミッタに接続され
た導体3.トランジスタ2のベースに接続された導体4
.トランジスタ2のコレクタに接続された導体5.及び
導体6が夫々形成されている。なお、図中の8a、4a
、5aは、夫々導体3〜5のパッド部である。
On this substrate there is a conductor 3. connected to the emitter of transistor 2. conductor 4 connected to the base of transistor 2
.. A conductor 5 connected to the collector of transistor 2. and a conductor 6 are formed respectively. In addition, 8a and 4a in the figure
, 5a are pad portions of the conductors 3 to 5, respectively.

また、前記基板上には、ベースに対して並列となるよう
に第1抵抗体7.第2抵抗体8が夫々印刷により形成さ
れている。ここで、第1抵抗体7の他端は前記導体3に
、第2抵抗体8は導体61;接続されている。なお、図
中の9は導体5,6を接続する印刷抵抗である。
Further, on the substrate, a first resistor 7. is arranged in parallel with the base. The second resistors 8 are each formed by printing. Here, the other end of the first resistor 7 is connected to the conductor 3, and the second resistor 8 is connected to the conductor 61. Note that 9 in the figure is a printed resistor that connects the conductors 5 and 6.

こうした構成の混成集積回路において、トランジスタ2
のベース電圧を定めるときは、第1抵抗体7あるいは第
2抵抗体8の少なくとも一方を図中矢印A、Bの如くレ
ーザによりトリミングすることにより、両抵抗体7,8
の抵抗の比率を定めることにより行う。
In a hybrid integrated circuit having such a configuration, transistor 2
To determine the base voltage of both resistors 7 and 8, at least one of the first resistor 7 or the second resistor 8 is trimmed with a laser as shown by arrows A and B in the figure.
This is done by determining the ratio of the resistances.

しかし、前記抵抗体7.8の両方をトリミングする場合
は、夫々抵抗体7,8の位置に応じてプログラムする必
要がある。また、トリミング抵抗が決定しトリミング時
にオーバーした場合、抵抗体7.8のいずれか一方をト
リミングして補正しなければならない。従って、一連の
トリミングのプログラムが複雑になるとともに、トリミ
ング時間も多くかかり作業性が低下するという問題点を
生じる。
However, when trimming both of the resistors 7, 8, it is necessary to program the positions of the resistors 7, 8, respectively. Furthermore, if the trimming resistance is determined and exceeds the limit during trimming, it is necessary to trim either one of the resistors 7 and 8 to correct it. Therefore, problems arise in that a series of trimming programs become complicated, and the trimming time also increases, reducing work efficiency.

(発明が解決しようとする課題) 本発明は上記事情に鑑みてなされたもので、第1・第2
抵抗体を絶縁層を介して一部オーバーラップして積層し
、互いにオーバーラツプされた両抵抗体を同時にトリミ
ングして両抵抗体の夫々の抵抗の比率を変化させてベー
ス電圧を定める構成とすることにより、トリミング作業
を容易にかつ短時間になしえる混成集積回路を提供する
ことを目的とする。
(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances.
A configuration in which resistors are laminated with some overlap through an insulating layer, and both overlapped resistors are simultaneously trimmed to change the ratio of the respective resistances of both resistors to determine the base voltage. It is an object of the present invention to provide a hybrid integrated circuit that can perform trimming operations easily and in a short time.

[発明の構成] (課題を解決するための手段と作用) 本発明は、絶縁基板と、この絶縁基板に形成されたベー
ス、エミッタ及びコレクタからなるトランジスタと、前
記ベースに対して並列に接続された第1・第2抵抗体と
を具備し、第1・第2低抗体が絶縁層を介して一部オー
バラツプして積層され、かつ互いにオーバーラツプされ
た両抵抗体を同時にトリミングすることにより両抵抗体
の夫々の抵抗の比率を変化させてベース電圧を定めるこ
とを特徴とする混成集積回路である。
[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a transistor including an insulating substrate, a base, an emitter, and a collector formed on the insulating substrate, and a transistor connected in parallel to the base. The first and second resistors are laminated with an insulating layer interposed therebetween, partially overlapping each other, and both resistors are removed by simultaneously trimming the overlapped resistors. This is a hybrid integrated circuit characterized in that the base voltage is determined by changing the ratio of each resistance of the body.

本発明によれば、第1・第2抵抗体を絶縁層を介して一
部オーバーラップして積層し、互いにオーバーラツプさ
れた両抵抗体を同時にトリミングして両抵抗体の夫々の
抵抗の比率を変化させてベース電圧を定める構成とする
ことにより、トリミング作業を容易にかつ短時間に行う
事ができる。
According to the present invention, the first and second resistors are laminated so as to partially overlap with each other through an insulating layer, and both overlapped resistors are simultaneously trimmed to adjust the ratio of the respective resistances of both resistors. By adopting a configuration in which the base voltage is determined by changing the base voltage, trimming work can be performed easily and in a short time.

(実施例) 以下、本発明の一実施例に係る混成集積回路を第1図を
参照して説明する。
(Embodiment) A hybrid integrated circuit according to an embodiment of the present invention will be described below with reference to FIG.

図中の21は、絶縁基板としてのセラミック基板である
。この基板上には、トランジスタ22のエミッタに接続
された導体23.トランジスタ22のベースに接続され
た導体24.トランジスタ22のコレクタに接続された
導体25.及び導体26が夫々形成されている。なお、
図中の23a、 24a、 25aは、夫々導体23〜
25のパッド部である。
21 in the figure is a ceramic substrate as an insulating substrate. On this substrate there is a conductor 23 . connected to the emitter of transistor 22 . A conductor 24 connected to the base of transistor 22. A conductor 25 connected to the collector of transistor 22. and a conductor 26 are formed, respectively. In addition,
23a, 24a, and 25a in the figure are conductors 23 to 25a, respectively.
This is the pad portion of No. 25.

また、前記基板上には、両端部が前記導体24゜26に
夫々接続したL字型の第1抵抗体(斜線部)27が形成
されている。前記基板上には、前記導体25、26に接
続した印刷抵抗28が形成されている。
Furthermore, an L-shaped first resistor (shaded portion) 27 is formed on the substrate, and both ends thereof are connected to the conductor 24 and 26, respectively. A printed resistor 28 connected to the conductors 25 and 26 is formed on the substrate.

前記基板上には、逆り字型の第2抵抗体29が絶縁層(
2点鎖線内)30を介して形成されている。前記第2抵
抗体29は前記第1抵抗体27とともに前記導体24に
対して並列に接続されている。また、両抵抗体27.2
9は互いに平面的に見て線対称で、一部でオーバーラツ
プして形成されている。前記第2抵抗体29の他端は、
導体31を介して前記導体23に接続されている。
On the substrate, an inverted-shaped second resistor 29 is provided with an insulating layer (
(within the two-dot chain line) 30. The second resistor 29 and the first resistor 27 are connected in parallel to the conductor 24 . In addition, both resistors 27.2
9 are line-symmetrical to each other when viewed in plan, and are formed with some overlap. The other end of the second resistor 29 is
It is connected to the conductor 23 via a conductor 31.

こうした構成の混成集積回路において、トランジスタ2
2のベース電圧を定めるときは、第1抵抗体27及び第
2抵抗体29のオーバーラツプ部分(斜線が交差する個
所)を、例えば矢印A−Hに示す如くトリミングするこ
とにより行う。このように矢印A方向へのトリミング後
矢印B方向へのトリミングを行うと、抵抗体27.29
の抵抗は夫々増大するが、第1抵抗体27の抵抗の増大
幅ΔR,は第2抵抗体29の抵抗の増大幅ΔR2より大
きく、ΔR,>ΔR2である。このように、上記実施例
に係る混成集積回路によれば、第1・第2抵抗体。
In a hybrid integrated circuit having such a configuration, transistor 2
2 is determined by trimming the overlapping portion (where the diagonal lines intersect) of the first resistor 27 and the second resistor 29, for example, as shown by arrows A-H. In this way, when trimming in the direction of arrow A and then trimming in the direction of arrow B, the resistor 27.29
The resistance of the first resistor 27 increases ΔR, which is larger than the resistance increase ΔR2 of the second resistor 29, and ΔR>ΔR2. Thus, according to the hybrid integrated circuit according to the above embodiment, the first and second resistors.

27、29を絶縁層30を介して一部オーバラツプして
積層し、互いにオーバーラツプされた両抵抗体を同時に
トリミングして両抵抗体の夫々の抵抗の比率を変化させ
てベース電圧を定める構成とすることにより、1度のト
リミングで第1抵抗体27の抵抗と第2抵抗体29の抵
抗の比率を容易に定めることができる。また、仮に両抵
抗体27.29の抵抗の比率がオーバーした場合、トリ
ミングを矢印Bとは反対方向に行うことにより目的を達
成できる。
27 and 29 are laminated in a partially overlapping manner via an insulating layer 30, and both overlapped resistors are simultaneously trimmed to change the ratio of the respective resistances of both resistors to determine the base voltage. Thereby, the ratio of the resistance of the first resistor 27 and the resistance of the second resistor 29 can be easily determined by one-time trimming. Furthermore, if the ratio of the resistances of both resistors 27 and 29 exceeds the desired value, the purpose can be achieved by performing trimming in the direction opposite to arrow B.

なお、上記実施例では、第1・第2抵抗体の形状が夫々
L字型、逆り字型で線対称である場合について述べたが
、これに限定されない。例えば、両抵抗体が単にオーバ
ーラツプしているだけでもよく、線対称である必要もな
い。
In the above embodiments, the shapes of the first and second resistors are L-shaped and inverted-shaped, respectively, and are line symmetrical, but the present invention is not limited thereto. For example, both resistors may simply overlap, and do not need to be line symmetrical.

また、トリミングの仕方も上記実施例のような方向に限
定されず、両抵抗体の抵抗の比率を変えるような方向で
あればなんでもよい。
Further, the method of trimming is not limited to the direction as in the above embodiment, but may be any direction as long as it changes the ratio of the resistances of both resistors.

[発明の効果] 以上詳述した如く本発明によれば、第1・第2抵抗体を
絶縁層を介して一部オーバラップして積層し、互いにオ
ーバーラツプされた両抵抗体を同時にトリミングして両
抵抗体の夫々の抵抗の比率を変化させてベース電圧を定
める構成とすることにより、トリミング作業を容品にか
つ短時間になしえる混成集積回路を提供できる。
[Effects of the Invention] As detailed above, according to the present invention, the first and second resistors are laminated so as to partially overlap each other with an insulating layer interposed therebetween, and both of the overlapping resistors are simultaneously trimmed. By adopting a configuration in which the base voltage is determined by changing the ratio of the respective resistances of both resistors, it is possible to provide a hybrid integrated circuit that can be trimmed easily and in a short time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係る混成集積回路の平面図
、第2図は従来の混成集積回路の平面図である。 21・・・セラミック基板、22・・・トランジスタ、
23゜24、25.26.31・・・導体、27・・・
第1抵抗体、29・・・第2抵抗体、30・・・絶縁層
FIG. 1 is a plan view of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 2 is a plan view of a conventional hybrid integrated circuit. 21... Ceramic substrate, 22... Transistor,
23゜24, 25.26.31...Conductor, 27...
First resistor, 29... second resistor, 30... insulating layer.

Claims (1)

【特許請求の範囲】[Claims]  絶縁基板と、この絶縁基板に形成されたベース,エミ
ッタ及びコレクタからなるトランジスタと、前記ベース
に対して並列に接続された第1・第2抵抗体とを具備し
、第1・第2抵抗体が絶縁層を介して一部オーバーラッ
プして積層され、かつ互いにオーバーラップされた両抵
抗体を同時にトリミングすることにより両抵抗体の夫々
の抵抗の比率を変化させてベース電圧を定めることを特
徴とする混成集積回路。
The transistor includes an insulating substrate, a transistor including a base, an emitter, and a collector formed on the insulating substrate, and first and second resistors connected in parallel to the base. The base voltage is determined by changing the ratio of the respective resistances of both resistors by simultaneously trimming both resistors overlapped with each other with an insulating layer in between. Hybrid integrated circuit.
JP2083859A 1990-03-30 1990-03-30 Hybrid integrated circuit Pending JPH03283588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2083859A JPH03283588A (en) 1990-03-30 1990-03-30 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2083859A JPH03283588A (en) 1990-03-30 1990-03-30 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH03283588A true JPH03283588A (en) 1991-12-13

Family

ID=13814409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2083859A Pending JPH03283588A (en) 1990-03-30 1990-03-30 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH03283588A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000182811A (en) * 1998-12-21 2000-06-30 Alps Electric Co Ltd Resistance attenuator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000182811A (en) * 1998-12-21 2000-06-30 Alps Electric Co Ltd Resistance attenuator

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