JPH03283464A - Thin film laminated type electronic device - Google Patents

Thin film laminated type electronic device

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Publication number
JPH03283464A
JPH03283464A JP2081351A JP8135190A JPH03283464A JP H03283464 A JPH03283464 A JP H03283464A JP 2081351 A JP2081351 A JP 2081351A JP 8135190 A JP8135190 A JP 8135190A JP H03283464 A JPH03283464 A JP H03283464A
Authority
JP
Japan
Prior art keywords
film
thin film
amorphous silicon
density
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2081351A
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Japanese (ja)
Other versions
JP2983243B2 (en
Inventor
Hidetoshi Nozaki
野崎 秀俊
Masahito Hiramatsu
雅人 平松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Priority to JP2081351A priority Critical patent/JP2983243B2/en
Publication of JPH03283464A publication Critical patent/JPH03283464A/en
Application granted granted Critical
Publication of JP2983243B2 publication Critical patent/JP2983243B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To prevent a thin film formed on a board from being separated off from the board due to the inner stress induced in the film concerned so as to improve a device in characteristics and reliability by a method wherein the inner stress is absorbed by a part of the thin film where the main component elements of the film are small in number per unit area or which is small in density. CONSTITUTION:An amorphous silicon hydride film 2 is deposited as thick as 1mum or so on a glass board 1, an amorphous silicon hydride film small in silicon density is formed as thick as required but 200Angstrom or below, and an amorphous silicon hydride film 4 is deposited thereon as thick as 1mum or so under the same conditions with the silicon film 2. When the amorphous silicon films 2 and 4 are formed in succession, the films are separated off, since they are formed under the conditions where inner stress exceeds 4X10<9>dyne/cm<2>, but in this case, as the structure 3 small in silicon density absorbs inner stress, films are prevented from being separated off.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、基板上に薄膜を形成した構造を有する薄膜積
層型電子装置に係わり、特に薄膜の内部応力の低減をは
かった薄膜積層型電子装置に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a thin film laminated electronic device having a structure in which a thin film is formed on a substrate, and in particular aims to reduce the internal stress of the thin film. The present invention relates to a thin film stacked electronic device.

(従来の技術) 近年、非晶質シリコン等の非単結晶薄膜を活性層に用い
た密着型イメージセンサ、固体撮像素子及び薄膜トラン
ジスタ等の研究開発か進められている。これらのうち、
密着型イメージセンサや固体撮像素子は非単結晶薄膜中
で光によって生成したキャリアを利用するデバイスであ
り、一方薄膜トランジスタは電界効果により非単結晶薄
膜中を流れる電流を制御するデバイスである。いずれの
デバイスも活性層の非単結晶薄膜、代表的には水素化非
晶質シリコン膜を高品質にすることが良好なデバイス特
性を得るために不可欠であり、特に該薄膜におけるキャ
リアの移動度を大きくすることか重要である。
(Prior Art) In recent years, research and development has been progressing on contact image sensors, solid-state image sensors, thin film transistors, etc. that use non-single crystal thin films such as amorphous silicon as active layers. Of these,
Contact image sensors and solid-state imaging devices are devices that utilize carriers generated by light in non-single-crystal thin films, while thin-film transistors are devices that control current flowing in non-single-crystal thin films using electric field effects. In any device, it is essential to improve the quality of the active layer's non-single-crystal thin film, typically a hydrogenated amorphous silicon film, in order to obtain good device characteristics, especially the carrier mobility in the thin film. It is important to make the

ところで、水素化非晶質シリコン膜は5t−H結合と5
r−H2結合を有しているが、水素化非晶質シリコン膜
における電子移動度はこれらの結合の割合に依存するこ
とが知られている。具体的には、5i−H結合の割合を
増やし5i−H2結合の割合を減らすことにより、水素
化非晶質シリコン膜における電子移動度が大きくなる。
By the way, hydrogenated amorphous silicon film has 5t-H bonds and 5
Although it has r-H2 bonds, it is known that the electron mobility in a hydrogenated amorphous silicon film depends on the ratio of these bonds. Specifically, by increasing the proportion of 5i-H bonds and decreasing the proportion of 5i-H2 bonds, the electron mobility in the hydrogenated amorphous silicon film is increased.

しかしながら、S+−H結合の割合を増やし5t−1(
2結合の割合を減らすと、一般に薄膜の内部応力が増大
する。即ち、第9図に一例として示すように、水素化非
晶質シリコン膜の電子移動度が増加すると、必然的に膜
の内部応力も増加してしまう。このため、高電子移動度
を有する薄膜を堆積してデバイス特性を向上させようと
すると、基板から膜が剥離し易くなるという不都合があ
った。
However, by increasing the proportion of S+-H bonds, 5t-1(
Reducing the proportion of 2 bonds generally increases the internal stress of the thin film. That is, as shown as an example in FIG. 9, when the electron mobility of the hydrogenated amorphous silicon film increases, the internal stress of the film inevitably increases. For this reason, when attempting to improve device characteristics by depositing a thin film having high electron mobility, there is a problem in that the film tends to peel off from the substrate.

(発明か解決しようとする課題) このように従来、非晶質シリコン等の非単結晶薄膜を活
性層に用いた密着型イメージセンサ。
(Problem to be solved by the invention) As described above, conventional contact image sensors have used a non-single crystal thin film such as amorphous silicon as an active layer.

固体撮像素子及び薄膜トランジスタ等の電子装置におい
ては、高電子移動度の薄膜を堆積させた場合、固有の内
部応力が大きいために、薄膜が剥離し易くなるという問
題があった。その結果、内部応力を低減するため、電子
移動度か所望の値よりも小さい薄膜を堆積せざるを得す
、良好なデバイス特性が得られないという問題かあった
BACKGROUND ART In electronic devices such as solid-state imaging devices and thin film transistors, when a thin film with high electron mobility is deposited, there is a problem that the thin film easily peels off due to the large inherent internal stress. As a result, in order to reduce the internal stress, it is necessary to deposit a thin film whose electron mobility is smaller than the desired value, resulting in the problem that good device characteristics cannot be obtained.

なお、上記問題は非単結晶薄膜を用いた電子装置に限る
ものではなく、基板上に薄膜を堆積した構造を有する電
子装置において、薄膜の内部応力により基板から薄膜が
剥離する虞れがあり、これが電子装置の信頼性を低下さ
せる要因となっていた。
Note that the above problem is not limited to electronic devices using non-single crystal thin films, but in electronic devices having a structure in which a thin film is deposited on a substrate, there is a risk that the thin film will peel off from the substrate due to internal stress of the thin film. This has been a factor in reducing the reliability of electronic devices.

本発明は、上記事情を考慮してなされたものであり、そ
の目的とするところは、基板上に堆積した薄膜の内部応
力に起因する薄膜の剥がれを防止することができ、デバ
イス特性及び信頼性の向上をはかり得る薄膜積層型電子
装置を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to prevent peeling of a thin film deposited on a substrate due to internal stress, and improve device characteristics and reliability. An object of the present invention is to provide a thin film stacked electronic device that can improve the performance.

特に本発明は、高電子移動度を有する非単結晶薄膜を堆
積した場合においても、膜の剥離か生じず、電子や正孔
の走行性に優れた密着型イメージセンサ、固体撮像素子
或いは薄膜トランジスタ等の薄膜積層型電子装置を提供
することを目的とする。
In particular, the present invention can be applied to contact image sensors, solid-state image sensors, thin film transistors, etc. that do not cause peeling of the film even when depositing a non-single-crystal thin film with high electron mobility, and have excellent transport properties for electrons and holes. The purpose of the present invention is to provide a thin film stacked electronic device.

[発明の構成] (課題を解決するための手段) 本発明の骨子は、薄膜層の内部に薄膜の主要構成元素の
単位体積中の数、即ち密度が小さい部分を設け、この部
分で応力を吸収させることにある。
[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to provide a portion in which the number of main constituent elements of the thin film per unit volume, that is, density is small, inside the thin film layer, and to apply stress in this portion. The purpose is to absorb it.

即ち本発明は、段差を有する基板上に非晶質シリコン等
の薄膜を形成してなる薄膜積層型電子装置において、前
記薄膜の内部に該薄膜の主要構成元素の密度が他の部分
より小さい構造部を、所望の幅を持った線状若しくは面
状に配置するようにしたものである。
That is, the present invention provides a thin film stacked electronic device in which a thin film of amorphous silicon or the like is formed on a substrate having steps, and a structure in which the density of the main constituent elements of the thin film is lower than that in other parts of the thin film. The parts are arranged in a linear or planar shape with a desired width.

(作用) 本発明によれば、薄膜層内部に配置した密度の小さい構
造部が応力を吸収する役割を果たすので、高電子移動度
を有する非晶質シリコン等の非単結晶薄膜を膜か剥離す
ることなしに堆積させることができる。線状又は面状の
密度の小さい部分の幅を所望の範囲に適切に選ぶことに
より、この部分がデバイス特性に与える悪影響は問題な
い。従って、従来よりも電子や正孔等のキャリアの走行
性に優れた良好な特性の薄膜積層型電子装置を、膜剥離
等のプロセス上の問題がない状態で形成することかでき
る。
(Function) According to the present invention, since the low-density structure arranged inside the thin film layer plays the role of absorbing stress, a non-single crystal thin film such as amorphous silicon having high electron mobility can be peeled off from the film. can be deposited without any By appropriately selecting the width of the linear or planar low-density portion within a desired range, there is no problem with the adverse effect this portion has on device characteristics. Therefore, it is possible to form a thin film laminated type electronic device with good characteristics, in which the mobility of carriers such as electrons and holes is better than in the past, without any process problems such as film peeling.

以上主に非晶質シリコン系薄膜について作用を述べてき
たが、本発明はこれに限らす、金属層、さらに窒化シリ
コン膜や酸化シリコン膜等の絶縁層にも同様な作用を有
し、内部応力の大きな条件で薄膜を形成しても、薄膜の
剥離を生じ難くすることが可能となる。
Although the effect has been mainly described above on amorphous silicon-based thin films, the present invention is not limited to this, but has similar effects on metal layers, and furthermore, insulating layers such as silicon nitride films and silicon oxide films. Even if the thin film is formed under conditions of high stress, it is possible to make it difficult for the thin film to peel off.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

まず、内部応力の大きい非晶質シリコン膜をガラス基板
上に形成した場合に膜の剥離か生じない実施例を第1図
と第2図に示す。両図とも密度の大小が明瞭に判るよう
に断面透過電子顕微鏡写真の模式図を示した。
First, FIGS. 1 and 2 show examples in which peeling of the film does not occur when an amorphous silicon film with a large internal stress is formed on a glass substrate. In both figures, schematic diagrams of cross-sectional transmission electron micrographs are shown so that the magnitude of density can be clearly seen.

第1図において、1のガラス基板上に水素化非晶質シリ
コン膜2を約1μm堆積した後に、シリコン密度が小さ
い水素化非晶質シリコン膜3を200Å以下の所望の膜
厚で形成し、その後にシリコン膜2と同様の条件で水素
化非晶質シリコン膜4を約1μm堆積させた。なお、実
際の写真では図の3の部分は2,4の薄膜と比較して、
密度が小さく電子を透過し易いために白っぽく観察され
る。
In FIG. 1, after depositing a hydrogenated amorphous silicon film 2 of about 1 μm on a glass substrate 1, a hydrogenated amorphous silicon film 3 having a low silicon density is formed to a desired thickness of 200 Å or less, Thereafter, a hydrogenated amorphous silicon film 4 of about 1 μm was deposited under the same conditions as the silicon film 2. In addition, in the actual photograph, the part 3 in the figure is compared to the thin film 2 and 4.
It appears whitish because its density is low and electrons can easily pass through it.

非晶質シリコン膜2.4を連続的に形成した場合には、
内部応力が4 X 1(19dyn/Cll12以上と
なる条件を用いて形成したために膜の剥離が生じたが、
第1図の実施例ではシリコン密度の小さい構造部3が応
力を吸収するために膜の剥離は生しなかった。
When the amorphous silicon film 2.4 is formed continuously,
The film peeled off because it was formed using conditions where the internal stress was 4 x 1 (19 dyn/Cll12 or more), but
In the embodiment shown in FIG. 1, the structure 3 having a low silicon density absorbs the stress, so that no peeling of the film occurs.

ここで、水素化非晶質シリコン膜の形成方法としては、
従来より良く知られているシランガスをプラズマにより
分割するプラズマCVD法や光エネルギーにより分解す
る光CVD法を用いればよい。また、シリコン密度が小
さい水素化非晶質シリコン膜を形成するためには、例え
ば形成基板温度Tsを低くして薄膜中に含まれる水素量
を増やせばよい。この実施例では2と4はTs=250
℃で形成し、シリコン密度の小さい構造部3はTs=1
50℃で形成した。
Here, the method for forming the hydrogenated amorphous silicon film is as follows:
The conventionally well-known plasma CVD method in which silane gas is divided by plasma or the photoCVD method in which it is decomposed by light energy may be used. Furthermore, in order to form a hydrogenated amorphous silicon film with a low silicon density, for example, the formation substrate temperature Ts may be lowered to increase the amount of hydrogen contained in the thin film. In this example, 2 and 4 are Ts=250
℃, the structure 3 with low silicon density has Ts=1
Formed at 50°C.

第2図は、ガラス基板1に対して平行ではなく斜めにシ
リコン密度の小さい水素化非晶質シリコン膜の構造部3
を面状に形成した例である。
FIG. 2 shows a structural part 3 of a hydrogenated amorphous silicon film with a low silicon density that is not parallel to the glass substrate 1 but oblique.
This is an example in which it is formed into a planar shape.

この図において、2は水素化非晶質シリコン膜であり、
2を堆積中に意図的に構造部3を形成配置した。なお、
3は図では線状であるが、実際は面状に配置しである。
In this figure, 2 is a hydrogenated amorphous silicon film,
Structures 3 were intentionally formed and placed during the deposition of 2. In addition,
3 is linear in the figure, but in reality it is arranged in a planar manner.

シリコン密度の小さい構造部3は10〜200人の範囲
の所望の値に線幅を設定したか、一定にする必要はない
。また、構造部3を2本以上の線或いは2個以上の面に
より構成しても構わない。構造部3を任意に形成するた
めには、基板1の表面の3次元的な構造を適切に選ぶこ
とにより実現できる。
In the structure 3 having a low silicon density, the line width is set to a desired value in the range of 10 to 200 people, or does not need to be constant. Furthermore, the structural portion 3 may be constructed of two or more lines or two or more surfaces. The structure portion 3 can be formed arbitrarily by appropriately selecting the three-dimensional structure of the surface of the substrate 1.

実際に構造部3か小さいシリコン密度を実現しているこ
とを確認するために、本発明者らはエネルギー分散型X
線分析法(EDX法)を用いて評価した。直径10人φ
に絞った電子線を5の方向に走査して断面に照射し、試
料の断面部から放射されるシリコン特性X線量(X線ピ
ーク強度)を測定した。その結果、第3図に示すように
構造部3では明らかにシリコン密度が減少していること
が判明した。同様に、エネルギー損失分光法(EELS
法)によっても構造部3におけるシリコン密度の減少を
確認できた。
In order to confirm that structure 3 actually achieves a small silicon density, the present inventors conducted an energy-dispersive
Evaluation was performed using a line analysis method (EDX method). Diameter 10 people φ
An electron beam focused on the sample was scanned in the direction 5 and irradiated onto the cross section, and the amount of silicon characteristic X-rays (X-ray peak intensity) emitted from the cross section of the sample was measured. As a result, as shown in FIG. 3, it was found that the silicon density in structure portion 3 was clearly reduced. Similarly, energy loss spectroscopy (EELS)
It was also confirmed that the silicon density in the structure 3 was reduced by the method (method).

本実施例の効果としては、構造部3を形成しない場合に
は、水素化非晶質シリコン膜2が基板1から剥離したが
、構造部3を形成したこの実施例においては膜の剥離が
起こらないことが判った。
As an effect of this example, when the structure part 3 was not formed, the hydrogenated amorphous silicon film 2 peeled off from the substrate 1, but in this example where the structure part 3 was formed, no peeling of the film occurred. It turns out there isn't.

次に、本発明を実際の電子装置に適用した第2の実施例
を説明する。
Next, a second embodiment in which the present invention is applied to an actual electronic device will be described.

第4図は水素化非晶質シリコン薄膜系の光電変換層を、
走査回路と集電電極を集積させたCCD基板上に積層さ
せた構造の固体撮像素子の断面構造を示す図である。図
において、10はSi基板、11は蓄積ダイオード、1
2は垂直CCD、13は転送電極、14.16は絶縁膜
、15は引出し電極、17は画素電極であり、これら1
0〜17からCCD撮像素子基板が形成されている。
Figure 4 shows a hydrogenated amorphous silicon thin film photoelectric conversion layer.
FIG. 2 is a diagram showing a cross-sectional structure of a solid-state image sensor having a structure in which a scanning circuit and a current collecting electrode are stacked on a CCD substrate. In the figure, 10 is a Si substrate, 11 is a storage diode, 1
2 is a vertical CCD, 13 is a transfer electrode, 14.16 is an insulating film, 15 is an extraction electrode, and 17 is a pixel electrode.
A CCD image sensor substrate is formed from 0 to 17.

また、21は正孔ブロックキング層で例えば水素化非晶
質カーバイド層、22は主たる光導電層である水素化非
晶質シリコン膜、23は電子ブロッキング層で例えばp
型の非晶質シリコンカーバイド層であり、21〜23で
水素化非晶質シリコン薄膜系の光電変換層をなす。この
光電変換層の膜厚は総合して1〜2μm程度である。最
後に、光を透過できる透明電極24が形成されている。
Further, 21 is a hole blocking layer, for example, a hydrogenated amorphous carbide layer, 22 is a hydrogenated amorphous silicon film, which is the main photoconductive layer, and 23 is an electron blocking layer, for example, a hydrogenated amorphous carbide layer.
21 to 23 form a hydrogenated amorphous silicon thin film type photoelectric conversion layer. The total film thickness of this photoelectric conversion layer is about 1 to 2 μm. Finally, a transparent electrode 24 that can transmit light is formed.

さらに、水素化非晶質シリコン膜22は固有の内部応力
を吸収させるため、シリコン密度の小さい面状(図では
線状)の構造部25を光電変換層内に配置した。
Furthermore, in order to absorb the inherent internal stress of the hydrogenated amorphous silicon film 22, a planar (linear in the figure) structural part 25 having a low silicon density is arranged in the photoelectric conversion layer.

この実施例では、水素化非晶質シリコン膜2には内部応
力が4 X 1(19dyn/cm2以上と大きく且つ
電子移動度も0.45cm2/V、S以上と太き(値を
有する薄膜を用いたが、構造部25にょZ応力吸収の効
果により膜の剥離も生じず、高鶏光応答性を有する良好
な素子を形成することカできた。
In this example, the hydrogenated amorphous silicon film 2 has a thin film having a large internal stress of 4×1 (19 dyn/cm2 or more) and a large electron mobility of 0.45 cm2/V or more. However, due to the effect of Z stress absorption in the structure portion 25, no peeling of the film occurred, and a good element with high optical response could be formed.

これに対し、画素電極17の形成により表面に段差を有
したCCD撮像素子基板の3次元的構造が適切でなく、
構造部25を配置しなかった場合には同様な積層を行う
と容易に膜の剥離が生じ、素子を形成するに至らながっ
た。なお構造部25は断面から見て線幅が200Å以下
であることが望ましく、典型的には20−100人の範
囲の値を用いれば本発明の効果を得るに十分である。ま
た、構造部25は面状に限らず、線状であっても効果的
であることは言うまでもない。
On the other hand, the three-dimensional structure of the CCD image sensor substrate, which has a step on the surface due to the formation of the pixel electrode 17, is not appropriate;
In the case where the structural portion 25 was not provided, the film easily peeled off when similar lamination was performed, and no element was formed. Note that it is desirable that the line width of the structural portion 25 is 200 Å or less when viewed in cross section, and typically a value in the range of 20 to 100 is sufficient to obtain the effects of the present invention. Furthermore, it goes without saying that the structural portion 25 is not limited to a planar shape, but may be effective even if it is linear.

次に、第4図に示す水素化非晶質シリコン系薄膜を積層
させた2階建て構造の高感度固体撮像素子において、水
素化非晶質シリコン膜中にシリコン密度の小さい構造部
25を配置する種々な方法について詳細に説明する。
Next, in a two-story high-sensitivity solid-state imaging device in which hydrogenated amorphous silicon-based thin films are laminated as shown in FIG. Various methods for doing so will be explained in detail.

第1の方法は、画素電極17の厚さを変える方法である
。画素電極17の厚さをそれぞれ500人、 1000
人、 2000人と変えた場合のシリコン密度の小さい
構造部25の配置のされ方の概要を第5図(a)〜(c
)に模式的に示す。
The first method is to change the thickness of the pixel electrode 17. The thickness of the pixel electrode 17 is 500 and 1000, respectively.
Figures 5(a) to 5(c) outline the layout of the structure 25 with low silicon density when the number of people is changed to 2,000.
) is schematically shown.

第5図(a)の場合には、シリコン密度の小さい構造部
25は断面TEM写真で観察する限り殆ど形成されてい
ない。第5図(b)から(C)へと、画素電極17の厚
みを厚くするに従って、構造部25は明瞭に観察できる
ようになった。
In the case of FIG. 5(a), the structure 25 having a low silicon density is hardly formed as observed in the cross-sectional TEM photograph. As the thickness of the pixel electrode 17 increases from FIG. 5(b) to FIG. 5(C), the structure portion 25 can be clearly observed.

即ち、この実施例の範囲では、画素電極17を厚くする
に従い密度の小さい構造部25をより確実に配置するこ
とができた。その結果、この積層型固体撮像素子100
チップ当りの膜剥がれノ生シタチップ数は、下記表に示
す結果となった。
That is, within the scope of this example, as the pixel electrode 17 becomes thicker, the structure portions 25 with lower density can be arranged more reliably. As a result, this stacked solid-state image sensor 100
The number of raw chips with film peeling per chip was as shown in the table below.

ここで、画素電極17の膜厚を厚くするほど膜剥がれの
生じたチップが減少したのは、密度の小さい構造部25
が確実に配置され、膜の内部応力が構造部25で吸収さ
れた効果であることは言うまでもない。この例では、非
晶質シリコン系薄膜による光電変換膜21,22.23
の膜厚は総合で2μm形成したが、水素化非晶質シリコ
ン膜22は内部応力が4 x 109dyn/cm2の
値を有するものを用いた。また、この例では、紫外光源
に低圧水銀ランプを用い、原料ガスにシランガスを用い
た水銀増感光CVD法により光電変換膜を形成したが、
プラズマCVD等の他の成膜法で形成しても同様の効果
を得ることができる。例えば、水銀増感光CVD法にお
いて、内部応力が4 X 109dyn/cm2以上の
水素化非晶質シリコン膜を得るには、基板温度230℃
以上、シランガス圧力0.2Torr以下の条件を用い
、さらにはシランの流量、シランガスに含有させる水銀
量、また低圧水銀ランプの紫外光強度を適切な条件に設
定すればよい。
Here, as the film thickness of the pixel electrode 17 becomes thicker, the number of chips with film peeling decreases.
It goes without saying that this is an effect of ensuring that the structure 25 is placed and that the internal stress of the film is absorbed by the structure 25. In this example, photoelectric conversion films 21, 22, 23 made of amorphous silicon-based thin films are used.
The hydrogenated amorphous silicon film 22 used had an internal stress of 4 x 10<9>dyn/cm<2>. In addition, in this example, a photoelectric conversion film was formed by a mercury-sensitized photoCVD method using a low-pressure mercury lamp as an ultraviolet light source and silane gas as a raw material gas.
Similar effects can be obtained even if the film is formed by other film forming methods such as plasma CVD. For example, in the mercury-sensitized photoCVD method, in order to obtain a hydrogenated amorphous silicon film with an internal stress of 4 x 109 dyn/cm2 or more, the substrate temperature must be 230°C.
As described above, the silane gas pressure is set to 0.2 Torr or less, and the flow rate of silane, the amount of mercury contained in the silane gas, and the ultraviolet light intensity of the low-pressure mercury lamp may be set to appropriate conditions.

本実施例では画素電極17として、Ti電極を用いるこ
とができるが、この場合にはTi電極のバターニング方
法にリアクティブイオンエツチング(RIE)法やウェ
ットエツチング法等を用いることができる。望ましくは
Ti画素電極にアンダーカットが生じる心配の少ない、
異方性エツチングの特徴を有するRIE法を用いる方が
よい。
In this embodiment, a Ti electrode can be used as the pixel electrode 17, and in this case, a reactive ion etching (RIE) method, a wet etching method, or the like can be used as a patterning method for the Ti electrode. Preferably, there is less worry of undercutting the Ti pixel electrode.
It is better to use the RIE method, which has the characteristics of anisotropic etching.

Ti電極のRIEエツチング条件としては、代表的に下
記の条件を用いることができる。エツチングガスはCO
が20〜50scc11.  B C13が30〜60
scca+、 Cl 2が20〜5osccI111希
釈Heが1000〜SOOOsccm、そしてトータル
ガス圧力を0.5〜2Torrとし、放電パワーを20
0〜500 Wの範囲に設定すればよい。以上のエツチ
ング条件を調整することにより、エツチングされたTi
画素電極の側壁部のテーバ角を制御できると共に、該側
壁部とSiO2が接する電極端部26に曲率を付けるこ
ともできる。
As the RIE etching conditions for the Ti electrode, the following conditions can typically be used. Etching gas is CO
is 20-50scc11. B C13 is 30-60
scca+, Cl2 is 20~5osccI111 diluted He is 1000~SOOOsccm, the total gas pressure is 0.5~2Torr, and the discharge power is 20
What is necessary is just to set it in the range of 0-500W. By adjusting the above etching conditions, etched Ti
The Taber angle of the side wall portion of the pixel electrode can be controlled, and the electrode end portion 26 where the side wall portion and SiO2 are in contact can be provided with a curvature.

ここで、シリコン密度の小さい構造部25は一種の結晶
欠陥であり、この結晶欠陥部分25が場合によっては画
素電極17に接することがある。この場合、画素電極1
7と透明電極24間、又は隣接する画素電極17間で結
晶欠陥部分25を介してリーク電流が流れることになり
、望ましくない。そこで、画素電極17の端部26を滑
らかな連続曲線で形成することにより、結晶欠陥が端部
から発生することがなくなり、上記のリーク電流を防止
することができる。この端部を滑らかに形成する方法と
しては、画素電極形成の際のエツチング、即ちウエット
エ・ンチング又はドライエツチングにおける工・ソチン
グ条件を適宜選択すればよい。
Here, the structure portion 25 having a low silicon density is a type of crystal defect, and this crystal defect portion 25 may come into contact with the pixel electrode 17 depending on the case. In this case, pixel electrode 1
7 and the transparent electrode 24 or between the adjacent pixel electrodes 17 via the crystal defect portion 25, which is undesirable. Therefore, by forming the end portion 26 of the pixel electrode 17 with a smooth continuous curve, crystal defects will not occur from the end portion, and the above leakage current can be prevented. As a method for forming this end portion smoothly, it is sufficient to appropriately select etching and sowing conditions in the etching, ie, wet etching or dry etching, when forming the pixel electrode.

シリコン密度の小さい構造部25を配置する他の方法に
ついて説明する。これは、水素化非晶質シリコン膜22
を異なる成膜法で順次形成する方法である。
Another method of arranging the structure 25 with low silicon density will be described. This is a hydrogenated amorphous silicon film 22
This is a method in which the layers are sequentially formed using different film formation methods.

第6図は、水素化非晶質シリコン膜22をプラズマCV
D法で形成した下層の部分と、水銀増感光CVD法で形
成した上層の部分の組み合わせで構成した例である。第
6図において、221はプラズマCVD法により形成し
た水素化非晶質シリコン膜、22□は水銀増感光CVD
法により形成した水素化非晶質シリコン膜である。
FIG. 6 shows a hydrogenated amorphous silicon film 22 formed by plasma CVD.
This is an example of a combination of a lower layer formed by the D method and an upper layer formed by the mercury-sensitized CVD method. In FIG. 6, 221 is a hydrogenated amorphous silicon film formed by plasma CVD, and 22□ is a mercury-sensitized CVD film.
This is a hydrogenated amorphous silicon film formed by a method.

この例では、プラズマCVD法として13.56MHz
の高周波放電によりシランガスを分解、成膜する方法を
用いた。−船釣には、接地電極に設置した基板の温度を
200〜300℃、高周波電力を5〜100W、ガス圧
力を’0.1〜2 Torr、導入シラン流量を5〜1
00 secmとして薄膜の形成をすればよい。
In this example, 13.56MHz is used as the plasma CVD method.
A method of decomposing silane gas and forming a film using high-frequency discharge was used. - For boat fishing, the temperature of the board installed on the ground electrode should be 200 to 300℃, the high frequency power should be 5 to 100W, the gas pressure should be 0.1 to 2 Torr, and the flow rate of silane introduced should be 5 to 1
A thin film may be formed at a speed of 0.00 sec.

水銀増感光CVD法としては、この例では、微量水銀を
含んだシランガスに、低圧水銀ランプから紫外光を石英
窓を通してチャンバ内に導入し、シランガスを分解する
ことにより薄膜を堆積させた、例えば形成条件として基
板温度は100〜300℃、導入シラン流量は5〜20
0secm 。
In this example, the mercury-sensitized photoCVD method involves introducing ultraviolet light from a low-pressure mercury lamp into a silane gas containing a trace amount of mercury through a quartz window into a chamber, and decomposing the silane gas to deposit a thin film. The conditions are that the substrate temperature is 100 to 300℃, and the silane flow rate is 5 to 20℃.
0sec.

ガス圧力は0.05〜2 Torr等の条件を用いれば
よい。第6図において、25.はプラズマCVD法で形
成した薄膜221内に配置したシリコン密度の小さい構
造部であり、252は水銀増感光CVD法により形成し
た薄膜222内に配置したシリコン密度の小さい構造部
である。−点鎖線で示した27は、薄膜22.と222
の境界面に当たるが、必ずしもその境界面でシリコン密
度が小さくなるとは限らない。この図に示されるように
境界面27を境にして、シリコン密度の小さい構造部2
5の配置のされ方が異なる。この理由を以下に説明する
The gas pressure may be set to 0.05 to 2 Torr. In FIG. 6, 25. 252 is a structure with a low silicon density disposed within the thin film 221 formed by plasma CVD, and 252 is a structure with low silicon density disposed within the thin film 222 formed by mercury-sensitized CVD. - 27 indicated by a dotted chain line is a thin film 22. and 222
However, the silicon density does not necessarily decrease at that interface. As shown in this figure, with the boundary surface 27 as a boundary, a structure portion 2 with a low silicon density
5 is arranged differently. The reason for this will be explained below.

一般に、プラズマCVD法によると、中性種の他にイオ
ン主が成膜に関与し、基板上にシーズ電位の分布が生し
ることから、成長の異方性が存在し、積層方向には堆積
速度が大きいが、堆積方向に垂直な方向、つまり基板に
平行な方向には堆積速度が小さいという特徴を有する。
In general, according to the plasma CVD method, in addition to neutral species, ions mainly participate in film formation, and a distribution of seed potential occurs on the substrate, so there is anisotropy in growth, and the layering direction is It has a characteristic that the deposition rate is high, but the deposition rate is low in the direction perpendicular to the deposition direction, that is, in the direction parallel to the substrate.

このため、基板に水平な方向に対して45°以上の角度
でシリコン密度の小さい構造部25.が配置される。一
方、低圧水銀ランプを用いた水銀増感光CVD法は中性
種が成膜に関与するので、成膜は略等方性になるという
特徴を有する。
For this reason, structures 25. with low silicon density are formed at an angle of 45° or more with respect to the horizontal direction of the substrate. is placed. On the other hand, the mercury-sensitized photoCVD method using a low-pressure mercury lamp is characterized in that the film formation is approximately isotropic because neutral species are involved in film formation.

従って、基板の水平面に対して略45″の角度でシリコ
ン密度の小さい構造部252が配置できる。
Therefore, the structure 252 having a low silicon density can be arranged at an angle of approximately 45'' with respect to the horizontal plane of the substrate.

次に、第7図に水銀増感光CVD法により形成した水素
化非晶質シリコン膜222を下層に形成し、上層にプラ
ズマCVD法により形成した水素化非晶質シリコン膜2
2、を形成した場合の例を示す。上記の原理から、第7
図では構造部25の形成のされ方が第6図とは逆の関係
になっている。
Next, as shown in FIG. 7, a hydrogenated amorphous silicon film 222 formed by mercury-sensitized photoCVD is formed as a lower layer, and a hydrogenated amorphous silicon film 222 formed by plasma CVD is formed as an upper layer.
An example of forming 2 is shown below. From the above principle, the seventh
In the figure, the manner in which the structural portion 25 is formed is reversed from that in FIG.

以上のべた通り、第6図及び第7図に示すように、異な
る成膜法や異なる成膜法の組み合わせによって、シリコ
ン密度の小さい構造部の配置を所望のように変えること
ができる。これらの例では2種の異なる成膜法で2層を
積層させた例を示したが、これに限らず2種以上の成膜
法で、例えば前述の成膜法の他、ECRプラズマCVD
法やマグネトロンスパッタリンク法。
As described above, as shown in FIGS. 6 and 7, the arrangement of the structures with low silicon density can be changed as desired by using different film forming methods or a combination of different film forming methods. In these examples, two layers are laminated using two different film-forming methods, but the method is not limited to this, and two or more film-forming methods may be used, for example, in addition to the above-mentioned film-forming method, ECR plasma CVD
method and magnetron sputter link method.

イオンブレーティング法、イオンガンCVD法、直接励
起光CVD法等の組み合わせで、2層を積層させても、
同様にシリコン密度の小さい部分の配置をそれぞれの場
合において所望のように変えることができる。さらに、
配置を変えることにより、薄膜内の内部応力の吸収のさ
れ方が異なり、膜の剥離の仕方が違ってくるのはいうま
でもない。
Even if two layers are laminated using a combination of ion blating method, ion gun CVD method, direct excitation light CVD method, etc.
Likewise, the arrangement of the low silicon density portions can be varied as desired in each case. moreover,
It goes without saying that by changing the arrangement, the way the internal stress within the thin film is absorbed differs, and the way the film peels off also changes.

本発明者らの研究によれば、等しい内部応力を有する薄
膜を積層する場合を比べる。と、シリコン密度の小さい
部分を基板面に水平な方向に対して45″に近い角度で
配置する場合の方が膜は剥離し難い。例えば、同じ4 
X 109dyn/cm2の内部応力を有する水素化非
晶質シリコン膜を形成する場合、水銀増感光CVD法で
形成した方がプラズマCVD法で形成するよりも膜の剥
離は生じ難かった。この他、密度の小さい部分の配置方
法を変えたり、或いはその部分の密度自体を変えるため
には、薄膜の成長速度を変える方法も有効である。
According to the research conducted by the present inventors, a case where thin films having the same internal stress are laminated is compared. The film is more difficult to peel off when the part with low silicon density is placed at an angle close to 45'' with respect to the horizontal direction of the substrate surface.For example, the same 4
When forming a hydrogenated amorphous silicon film having an internal stress of X 109 dyn/cm2, peeling of the film was less likely to occur when formed by mercury-sensitized photoCVD than by plasma CVD. In addition, a method of changing the growth rate of the thin film is also effective in order to change the arrangement method of a low-density portion, or to change the density itself of that portion.

次に、本発明を薄膜トランジスタに適用した第3の実施
例を説明する。第8図は逆スタツガ−型TPTの概略構
成を示す断面図であり、これまでと同様に断面TEM写
真を模式的に示している。ガラス基板30上にゲート電
極31を形成し、3000人程度0シリコン酸化膜やシ
リコン窒化膜等の絶縁膜32を形成した後に、活性層で
ある水素化非晶質シリコン膜33を例えば500人、オ
ーミックコンタクト用のn+型氷水素化非晶質シリコン
834例えば500人堆積させ、ソース電極とドレイン
電極を35と36に設けた構成である。
Next, a third embodiment in which the present invention is applied to a thin film transistor will be described. FIG. 8 is a cross-sectional view showing a schematic structure of an inverted staggered TPT, and similarly to the previous example, a cross-sectional TEM photograph is schematically shown. After forming a gate electrode 31 on a glass substrate 30 and forming an insulating film 32 such as a silicon oxide film or a silicon nitride film by about 3,000 people, a hydrogenated amorphous silicon film 33 as an active layer is formed by, for example, 500 people. For example, 500 n+ type ice-hydrogenated amorphous silicon 834 for ohmic contacts are deposited, and source electrodes and drain electrodes are provided at 35 and 36.

本実施例ではこの構造に加えては、図中37で示すシリ
コン密度の小さい構造部を面状(図では線状)に配置し
た。構造部37は必ずしも全堆積部32,33.34及
び36に配置するに及ばず、この実施例では積層部32
.33及び34に配置した。
In this embodiment, in addition to this structure, a structure with a low silicon density, indicated by 37 in the figure, is arranged in a plane (in a line in the figure). The structural parts 37 are not necessarily arranged in all the stack parts 32, 33, 34 and 36; in this embodiment, the structure part 37 is
.. 33 and 34.

この実施例でも先の実施例と同様に、水素化非晶質シリ
コン膜33には内部応力が4 X 109dyn/cm
2以上と大きく、且つ電子移動度も0,45C麿2/ 
V、S以上と大きな値を有する薄膜を用いたが、膜の剥
離が生じず、電界効果移動度も十分大きな値を有する良
好な素子特性を得ることができた。即ち、オン電流が大
きく且つ高速なスイッチング特性を実現することができ
た。これに対し、構造部37を配置しなかった場合には
、膜が剥離し易くなったことはいうまでもない。勿論、
構造部37を配置することにより、絶縁膜32の剥離を
防止することができる。
In this example, as in the previous example, the hydrogenated amorphous silicon film 33 has an internal stress of 4 x 109 dyn/cm.
2 or more, and the electron mobility is also 0.45Cmaro2/
Although a thin film having a large value of V, S or more was used, it was possible to obtain good device characteristics without peeling of the film and having a sufficiently large value of field effect mobility. That is, it was possible to realize high-speed switching characteristics with a large on-current. On the other hand, it goes without saying that when the structural portion 37 was not provided, the film was more likely to peel off. Of course,
By arranging the structure portion 37, peeling of the insulating film 32 can be prevented.

なお、本発明は上述した実施例に限定されるものではな
い。実施例では薄膜として非晶質シリコン膜の場合の例
について述べたが、これに限らず基板上に形成される非
単結晶薄膜に適用することができ、さらに絶縁層や金属
層についても同様に適用することができる。また、酸化
物超電導体薄膜の形成に適用することも可能である。ま
た、固体撮像素子、薄膜トランジスタに限らず、密着型
イメージセンサに適用することができ、さらに段差を有
する基板上に薄膜を堆積した構造の電子装置に適用する
ことができる。その他、本発明の要旨を逸脱しない範囲
で、種々変形して実施することができる。
Note that the present invention is not limited to the embodiments described above. In the example, an example was described in which an amorphous silicon film was used as the thin film, but the present invention is not limited to this and can be applied to non-single crystal thin films formed on a substrate, and can also be applied to insulating layers and metal layers. Can be applied. Moreover, it is also possible to apply it to the formation of an oxide superconductor thin film. Further, the present invention is not limited to solid-state image sensors and thin film transistors, but can be applied to contact type image sensors, and furthermore, can be applied to electronic devices having a structure in which a thin film is deposited on a substrate having steps. In addition, various modifications can be made without departing from the gist of the present invention.

[発明の効果] 以上詳述したように本発明によれば、段差を有する基板
上に堆積する薄膜の内部に薄膜の主要構成元素の単位体
積中の数、即ち密度が小さい構造部を設けているので、
この構造部で応力を吸収させることができる。従って、
基板上に堆積した薄膜の内部応力に起因する薄膜の剥が
れを防止することとができ、デバイス特性及び信頼性の
向上をはかり得る薄膜積層型電子装置を実現することが
できる。特に、固体撮像素子に適用した場合は光応答特
性が高速化をはかることができ、薄膜トランジスタに適
用した場合はオン電流が大きく且つ高速なスイッチング
特性を実現することができる。
[Effects of the Invention] As detailed above, according to the present invention, a structure having a small number of main constituent elements of the thin film per unit volume, that is, a small density, is provided inside a thin film deposited on a substrate having steps. Because there are
This structure can absorb stress. Therefore,
It is possible to prevent peeling of a thin film deposited on a substrate due to internal stress, and it is possible to realize a thin film stacked electronic device that can improve device characteristics and reliability. In particular, when applied to a solid-state image sensor, it is possible to achieve high-speed photoresponse characteristics, and when applied to a thin film transistor, it is possible to achieve high-speed switching characteristics with a large on-current.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の第1の実施例を示す構造断
面図、第3図は走査位置とピーク強度との関係を示す特
性図、第4図は本発明の第2の実施例を説明するための
もので積層型固体撮像素子の概略構成を示す断面図、第
5図は画素電極厚さと構造部形成状態との関係を示す断
面図、第6図及び第7図は非晶質シリコン膜を2層に形
成した例を示す断面図、第8図は本発明の第3の実施例
を説明するためのもので薄膜トランジスタの概略構成を
示す断面図、第9図は従来の問題点を説明するためのも
ので水素化非晶質シリコン膜の内部応力と電子移動度と
の関係を示す特性図である。 1・・・ガラス基板、 2.4・・水素化非晶質シリコン膜、 3.25.37・・・構造部、 17・・・画素電極、 21.23・・・水素化非晶質カーバイド層、22・・
・水素化非晶質シリコン膜、 24・・・透明電極、 26・・・電極端部、 27・・・境界面、 30・・・ガラス基板、 31・・・ゲート電極、 32・・・絶縁膜、 33.34・・・水素化非晶質シリコン膜。
1 and 2 are structural cross-sectional views showing a first embodiment of the present invention, FIG. 3 is a characteristic diagram showing the relationship between scanning position and peak intensity, and FIG. 4 is a structural cross-sectional view showing a first embodiment of the present invention. This is a cross-sectional view showing the schematic structure of a stacked solid-state image sensor, which is for explaining an example. FIG. 5 is a cross-sectional view showing the relationship between the pixel electrode thickness and the state of structure formation. FIG. 8 is a cross-sectional view showing an example in which a crystalline silicon film is formed in two layers. FIG. 8 is a cross-sectional view for explaining the third embodiment of the present invention and shows a schematic structure of a thin film transistor. FIG. FIG. 2 is a characteristic diagram showing the relationship between internal stress and electron mobility of a hydrogenated amorphous silicon film for explaining the problem. 1...Glass substrate, 2.4...Hydrogenated amorphous silicon film, 3.25.37...Structure section, 17...Pixel electrode, 21.23...Hydrogenated amorphous carbide Layer, 22...
- Hydrogenated amorphous silicon film, 24... Transparent electrode, 26... Electrode end, 27... Boundary surface, 30... Glass substrate, 31... Gate electrode, 32... Insulation Film, 33.34...Hydrogenated amorphous silicon film.

Claims (3)

【特許請求の範囲】[Claims] (1)段差を有する基板上に薄膜を形成してなる薄膜積
層型電子装置において、前記薄膜の内部に該薄膜の主要
構成元素の密度が他の部分より小さい構造部を、所望の
幅を持った線状若しくは面状に配置してなることを特徴
とする薄膜積層型電子装置。
(1) In a thin film stacked electronic device formed by forming a thin film on a substrate having steps, a structure portion having a desired width is formed inside the thin film in which the density of the main constituent elements of the thin film is lower than in other parts. 1. A thin film stacked electronic device characterized by being arranged in a linear or planar manner.
(2)前記薄膜は、非晶質シリコン膜であることを特徴
とする請求項1記載の薄膜積層型電子装置。
(2) The thin film stacked electronic device according to claim 1, wherein the thin film is an amorphous silicon film.
(3)前記基板表面は導電層の有無により段差が形成さ
れ、前記主要構成元素の密度が他より小さい構造部は基
板表面の段差により前記薄膜の厚み方向に形成され、且
つ該構造部の基板側は基板表面の導電層とは非接触であ
ることを特徴とする請求項1記載の薄膜積層型電子装置
(3) Steps are formed on the surface of the substrate depending on the presence or absence of a conductive layer, and the structure portion in which the density of the main constituent elements is smaller than others is formed in the thickness direction of the thin film due to the step difference on the substrate surface, and 2. The thin film stacked electronic device according to claim 1, wherein the side is not in contact with the conductive layer on the surface of the substrate.
JP2081351A 1990-03-30 1990-03-30 Thin film type electronic device Expired - Fee Related JP2983243B2 (en)

Priority Applications (1)

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JP2081351A JP2983243B2 (en) 1990-03-30 1990-03-30 Thin film type electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2081351A JP2983243B2 (en) 1990-03-30 1990-03-30 Thin film type electronic device

Publications (2)

Publication Number Publication Date
JPH03283464A true JPH03283464A (en) 1991-12-13
JP2983243B2 JP2983243B2 (en) 1999-11-29

Family

ID=13743946

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP2983243B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002371494A (en) * 2002-03-11 2002-12-26 Daiki:Kk Sanitary paper

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002371494A (en) * 2002-03-11 2002-12-26 Daiki:Kk Sanitary paper

Also Published As

Publication number Publication date
JP2983243B2 (en) 1999-11-29

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