JPH03280569A - Input circuit of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a highly reliable semiconductor device excellent in performance, by providing a bias circuit which divides a voltage generated between the input of a level shift circuit and a reference potential, and applies a voltage on the gate of a field effect transistor(EFT). CONSTITUTION:One end of a resistor 12 is connected with a pad 11, and the other end is connected with the input of a level shift circuit 13, which is a circuit for making the logic amplitude level of a signal inputted from the outside coincide with the logic amplitude level of a semiconductor device. The drain of an FET 14 is connected with the connection point of the input of the circuit 13 and the resistor 12, and the source is connected with the earth potential. Three diodes connected in series are connected with the connection point of the input of the circuit 13 and the resistor 12, and further a resistor 16 is connected. The gate of the FET 14 is connected with the connection point of the diodes 15 and the resistor 16. A voltage generated between the input of the level shift circuit 13 and the earth potential is divided by the diodes 15 and the resistor 16, and this divided voltage is applied on the gate of the FET 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input circuit of a semiconductor device provided between an external terminal and an internal circuit of various semiconductor devices.

(Conventional technology) ICs (integrated circuits) formed under different technologies
When connecting two ICs, since each IC has a different logic level, these must be matched. In this case, by performing level conversion at the input section of the IC, each IC
Match logical levels.

For example, when connecting a TTL (transistor transistor logic) IC and a GaAs (gallium arsenide) IC, it is necessary to convert a TTL level signal with a large logic amplitude to a GaAs level signal with a small logic amplitude. . This conversion is performed on the GaAs IC side, for example in the circuit shown in FIG. A resistor 3 is connected between the pad 1 and the level shift circuit 2, and three diodes 4 are connected in series at a connection point between the resistor 3 and the bell shift circuit 2. TT with large logic amplitude
The L level signal is clamped by the diode 4 and applied to the level shift circuit 2, and its logic amplitude is limited to match the signal level of the GaAs IC.

[Problem to be solved by the invention]

However, the TTL signal with large logic amplitude is
If applied, a large forward current will flow through the diode 4, so there is a risk that the performance of the diode 4 will deteriorate during long-term use of the semiconductor device. An input circuit with such a conventional configuration cannot provide a highly reliable semiconductor device.

It is also possible to prevent performance deterioration by forming the diode 4 with a large area and reducing the amount of current flowing per unit area.

However, if the area of the diode 4 is increased, the input circuit will also become larger, which goes against the desire to miniaturize the device. Furthermore, if the area is increased, a large stray capacitance will be generated between the input terminal and the internal circuit, and performance such as the operating speed of the semiconductor device will deteriorate.

[Means to solve the problem]

The present invention has been made to solve these problems, and has one end connected to the input terminal of the semiconductor device and the other end connected to the input of the level shift circuit, and the drain thereof is connected to the input terminal of the level shift circuit. A field effect transistor (FET) whose source is connected to a reference potential and a bias circuit which divides the voltage generated between the input of the level shift circuit and the reference potential and applies a voltage to the gate of the FET. It is something that

[Effect]

When the voltage level of the level shift circuit input signal increases, the voltage applied to the gate of the FET by the bias circuit increases, and when it reaches a predetermined bias voltage level, the FET turns on and the input signal voltage is clamped, preventing excessive current. The current is shunted to the FET.

【Example〕

FIG. 1 is a circuit diagram showing an input circuit of a semiconductor device according to an embodiment of the present invention.

The pad 11 is an input terminal of the semiconductor device, or is electrically connected to a single pin, and a signal from outside the semiconductor device is transmitted thereto. One end of a resistor 12 is connected to this pad 11, and the other end of the resistor 12 is connected to a level shift circuit 13.
is connected to the input of This level shift circuit 13 is a circuit that matches the logic amplitude level of a signal input from the outside with the logic amplitude level of the semiconductor device, and its output is connected to an internal circuit. The level shift circuit 1
The drain of the FET 14 is connected to the connection point between the input of the FET 3 and the resistor 12, and the source of the FET 14 is connected to the ground potential which is a reference potential.

Further, three diodes 15 connected in series are connected to the connection point between the input of the level shift circuit 13 and the resistor 12, and a resistor 16 is further connected to the diodes 15. The gate of the FET 14 is connected to the connection point between the diode 15 and the resistor 16, and the voltage generated between the input of the level shift circuit 13 and the ground potential is divided by the diode 15 and the resistor 16. A voltage is applied to the gate of FET 14.

In such a configuration, the logic amplitude level of a signal input to the lead pin from outside the semiconductor device with a large logic amplitude level is temporarily limited by the voltage drop across the resistor 12.

Then, this signal whose logic amplitude level is limited is further applied to a level shift circuit 13, where its logic amplitude level is made to match the logic amplitude level of the semiconductor device.

Further, when the input signal level from the outside is higher than a predetermined voltage, the voltage divided by the diode 15 and the resistor 16 exceeds the threshold voltage of the FET 14, and the FET 14 is turned on and conducts between the drain and source. do. Therefore, the input signal voltage having a large amplitude level is clamped, and furthermore, the current due to the excessive voltage is shunted between the drain and source of the FET 14. Therefore, the current flowing through the diode 15 is limited and its value becomes small.

Therefore, even if the semiconductor device is used for a long period of time, its performance will not deteriorate.

In addition, in the description of the above embodiment, the bias circuit for applying voltage to the gate of the FET 14 was constructed by the diode 15 and the resistor 16, but a resistor may be used instead of the diode 15.

In other words, when a signal of a predetermined voltage value or higher is input, F
By appropriately selecting the voltage division ratio between the new resistor and the resistor 16 so that the gate voltage of the ET14 exceeds the threshold voltage, the excessive voltage is clamped as in the above embodiment, and the excessive current is shunted to the FET14 and absorbed. be done. For this reason,
The input voltage of the level shift circuit 13 is appropriately limited, and problems such as performance deterioration that occur when using conventional diodes do not occur. However, when the bias circuit is configured using two resistors, the input voltage change of the level shift circuit 13 becomes steeper than when the diode 15 is used. On the other hand, in the case of the above embodiment, the input voltage change of the level shift circuit 13 is gradual.

〔Effect of the invention〕

As explained above, according to the present invention, when the voltage level of the input signal increases, the voltage applied to the gate of the FET by the bias circuit increases, and when it reaches a predetermined bias voltage level, the FET turns on and the input signal increases. The voltage is clamped and excess current is shunted to the FET.

Therefore, even when the semiconductor device is used for a long period of time, there is no risk that the performance of the diode will deteriorate, and unlike a large-area diode, the performance such as the operating speed of the semiconductor device will not deteriorate. Therefore, it is possible to provide a semiconductor device with good performance and high reliability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an input circuit of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an input circuit of a semiconductor device having a conventional configuration. 11... Pad, 12.16... Resistor, 13...
Level shift circuit, 4...FET. 5...Diode.

Claims (1)

[Claims] A resistor whose one end is connected to the input terminal of the semiconductor device and whose other end is connected to the input of a level shift circuit that matches the logic amplitude level of the signal input to the input terminal with the logic amplitude level of the semiconductor device, and the drain thereof is connected to the input terminal of the semiconductor device. A field effect transistor is connected to the input of the level shift circuit and has its source connected to a reference potential, and the voltage generated between the input of the level shift circuit and the reference potential is divided and a voltage is applied to the gate of the field effect transistor. An input circuit for a semiconductor device, comprising: a bias circuit for applying voltage.