JPH03278612A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To eliminate the production of undesired overflow and to reduce a circuit scale by using a signal subjected to a clip processing at a clip circuit so as to apply processing for code inversion. CONSTITUTION:A signal converted into a digital signal at an A/D converter circuit 104 is inputted to the clip circuit 10, in which the signal is clipped to a value larger by one digit than a minimum value. A signal subjected to amplitude limit in the clip circuit 10 is delayed by one line respectively in line memories 110, 111 and outputs are inputted respectively to rounding-off circuits 20-22 via BPFs 120-122, and the output of the round-off circuit 21 is inverted by a code inversion circuit 130 and the result is inputted to a logic circuit 140. Thus, no carry due to overflow is caused even with the code inversion and the circuit scale is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing circuit suitable for reducing the circuit scale.

[Conventional technology]

An A/D conversion circuit converts analog signals into digital signals, and a D/A conversion circuit performs the reverse conversion.

2. Description of the Related Art Digitalization of signal processing is being promoted due to lower prices and larger scale of digital memories, digital signal processing LSIs, etc.

Digital signal processing methods are described in various documents, but for example, digital signal processing methods,
How to represent negative numbers is described on pages 73 to 75 of Digital Signal Processing (Part 2), translated by Gen Date, published by Corona Publishing (October 1978). Table 1 is positive when expressed as two's complement.

12 is a table showing an example of how to represent a negative number.

In the following margin binary numbers, the most significant bit represents a positive or negative sign; in the example in Table 1, when the most significant bit is 1, it represents positive or 0, and when it is 0, it represents negative.

Also, with the dotted line in Table 1 as the border, 0 and -1, 1 and -2,
There is a complementary relationship between... Therefore, for a certain number n, -n can be found by finding the complement of n and adding 1 to it.

In the example of Table 1, if we reverse the sign of the smallest number (-8 in decimal notation) that can be represented by 4 bits.

10,000, which cannot be expressed with 4 bits and is a 5-bit number. Therefore, when sign inversion is performed by signal processing, calculations for one finger are required in the subsequent circuit.

As an example, a Y/C separation circuit that separates a luminance signal and a color signal from a composite video signal will be described. For Y/C separation circuits, please refer to IE Transactions on Consumer Electronics, CEE3
1, No. 3, (August 1985), pp. 244-2
Page 49 (IEEE, Trans.

on Consumer Electronics,
Vol, CE-31, ~0.3° August 198
5. pp. 244-249).

FIG. 2 is a block diagram showing the Y/C separation circuit. In FIG. 2, 101 is an input terminal for a composite video signal VSB, 102 is an output terminal for a luminance signal Y, 103 is an output terminal for a carrier color signal, 104 is an A/D converter, 105, 10
6 is a D/A converter.

110 and 111 are line memories that delay the signal by one line, 120 to 122 are band pass filters (hereinafter referred to as BPF), 130 and 131 are sign inversion circuits, 140 is the logic circuit discussed in the above paper, and 150 is an arithmetic operation. 160 is a delay circuit for delay adjustment, and 160 is an adder circuit.

The composite video signal VSB input from terminal 101 is A/D
The conversion circuit 104 converts the m-bit digital signal tJsB1.
is converted to Signal VSBI is delayed by one line in m-bit line memories 110 and 111, respectively. The output of line memory 11.0.111 is signal VSB2 respectively.
．． Set it to VSB3.

Signal VSB2. VSB3 is an m-bit digital signal.

Signals VSBI, VSB2. VSB3 is BPF1 each
The output of the BPF 121 is further input into the rear wheel processing circuit 140 whose sign is inverted by the sign inverting circuit.

It is assumed that the output signal of the BPF 120 is 81, the output signal of the sign inversion circuit 130 is BN2, and the output signal of the BPF 122 is B3.

The logic circuit 140 uses the correlation of the carrier color signals to
The signal BN2, the average value of the signal B1 and the signal BN2, or the average value of the signal BN2 and the signal B3 is selected and output.

The polarity of the output signal of the logic circuit 140 is determined by the sign inversion circuit 130.
Since the sign is inverted at , an inverted carrier color signal is output. Therefore, after the sign is inverted again by the sign inverting circuit 131, it is converted into an analog signal by the D/A converting circuit 106, and the separated carrier color signal C is outputted from the terminal 103.

Further, the composite video signal delayed by one line in the line memory 110 is input to the addition circuit [160] via the delay circuit 150. The delay time of the delay circuit 150 is BPF120~
122, the sign inversion circuit 130, and the delay time delayed by the logic circuit 140. The sign-inverted and separated carrier color signal output from the logic circuit 140 is added as another input to the adder circuit 160, and the signal is added to the D/A converter circuit 105.
The luminance signal is converted into an analog signal to obtain a nine-separated luminance signal, and is output from the terminal 102.

The BPFs 120 to 122 can be realized, for example, by the configuration shown in FIG. In Fig. 3, 170 is the input terminal of BPF, 171
is an output terminal of the BPF, 180 to 183 are m-bit D flip-flops, 190° and 191 are adder circuits, ]92 is a 7x coefficient circuit, 193 is a 1x coefficient circuit, and 194 is a sign inversion circuit.

In this example, the sampling frequency of the A/D converter 104 is 4fsc (fsc is the carrier frequency). terminal 170
The m-bit signal BPI input from the adder circuit 190
and is latched by the D flip-flop 180. Roughly speaking, the output of the D flip-flop 180 is sequentially delayed by the D flip-flops 181, 182, and 183, and becomes the output signal BP3 of the D flip-flop 183.
is input to the other terminal of the adder circuit 190. Signal BPI
.

Since each BF2 is an m-bit signal, the adder circuit 19
0 requires an m-bit adder circuit, whose output is m+
It becomes 1 bit. The output of the addition circuit $190 is multiplied by 7 by a coefficient of 192, and the sign of the output signal BP4 is inverted by a sign inverting circuit 194. At this time, signal BP4 is OO...
- If 0, signal BPN4 has the value of m+2 bits. Signal BP2 is multiplied by a coefficient circuit 193 and added to signal BPN4 in an adder circuit 191. The adder circuit 191 consists of an m+2 bit adder circuit, and its output is m+
It becomes 3 bits.

Therefore, the subsequent circuits require m+3 bit operations.

[Problem to be solved by the invention]

The conventional technology described above has a problem in that the number of bits of data is expanded due to the sign inversion circuit and arithmetic processing, resulting in an increase in circuit scale.

An object of the present invention is to suppress the increase in circuit scale due to sign inversion, etc., and to realize equivalent functions with a smaller circuit scale.

[Means to solve the problem]

In order to achieve the above object, a clipping circuit is provided before the sign inverting circuit to clip the minimum value to a value that is one digit larger than the minimum value.

Furthermore, a clipping circuit is provided at the first stage of the signal processing circuit to limit the amplitude and then perform signal processing. In signal processing, rounding circuits are provided at positions where errors will not accumulate.

[Effect]

By providing a clipping circuit before the sign inversion circuit and clipping the minimum value to a value 1 larger than the minimum value, carryover due to overflow does not occur even when the sign is inverted, and the circuit scale can be reduced.

In addition, by providing a rounding circuit as appropriate, unnecessary calculations down to the lower order can be eliminated and the circuit scale can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an example in which the present invention is applied to a Y/C separation circuit that separates a composite video signal into a luminance signal and a carrier color signal. Parts of FIG. 1 are the same as those of FIG. 2, and the same parts are given the same reference numerals and detailed explanation thereof will be omitted.

In Figure 1, 10.11 is a clip circuit, 20-2
2 is a round circuit.

The signal converted into a digital signal by the A/D conversion circuit 104 is input to the clip circuit 10, where the amplitude is limited. The signal whose amplitude has been limited by the clip circuit 10 is sent to the line memory 1.
10 and is input to the BPF 120.

The configurations of the BPFs 420 to 122 are the same as those shown in FIG. In the BPF shown in FIG.
94, but in order to prevent this, a clip circuit 10 is provided.

In the case of the embodiment shown in FIG. 3, the value of the signal BP4 is OO...
...In the case of O, a carry occurs, so the amplitude is limited by the clip circuit 10. FIG. 4 shows an example of the clip circuit 10. The example of FIG. 4 shows the case where m=8, that is, the case of 8-bit data.

In FIG. 4, 30 to 37 indicate data input terminals, 3o indicates a least significant bit (LSB) input terminal, and 40 to 47 indicate amplitude-limited data output terminals. 40 is a least significant bit (LSB) output terminal. 50 is an AND circuit with inverted input, and terminals 30 to 37
Inverting input AND only if the input data of is all 0
The output of circuit 50 will be 1. 51 is an OR circuit.

That is, when the input data of terminals 30 to 37 are all O, the output of the OR circuit 51 is 1, which is 0O000001.
is fixed to the value of

By the clipping process shown in FIG. 4, the signal B shown in FIG.
P4 no longer becomes OO...0, no carry occurs in sign inversion circuit 194, and therefore signal BPN4 becomes m+1 bits. Therefore, the adder circuit 291 can be constructed of an m+1 bit adder circuit, and the circuit scale can be reduced.

Further, the outputs of the BPFs 120 to 122 are respectively input to rounding circuits 20 to 22, and if the first digit after the decimal point is 1, the outputs are rounded up, and if the decimal place is 0, the outputs are rounded down. As a result, the output signals of the rounding circuits 20 to 21 each have m focuses. In the case of the embodiment shown in FIG. 1, since rounding circuits 20 to 22 are used for the outputs of BPFs 120 to 122, respectively, the least significant bit of the signal BP4 can be deleted using the EPF shown in FIG. It becomes a signal. Therefore, sign inversion circuit 194. Adder circuits 191 each perform m-bit operations. This allows the number of circuits to be reduced.

Furthermore, in the embodiment shown in FIG. 1, the number of circuits can be reduced as in the embodiment shown in FIG. The components of the circuit shown in FIG. 5 are included in the components of the @ path shown in FIG. The output signal of the rounding circuit 21 becomes the input of the line memory 111, and the output of the line memory 111 becomes the logic circuit 140.
is input.

This means that BPF 122. in FIG. The rounding circuit 22 is BPF121. It is also used by the rounding circuit 21. As a result, the BPF and rounding circuit are each tL
By deleting i at a time, the circuit scale can be reduced.

Furthermore, in FIGS. 1 and 5, the clip circuit 11 is provided at the output of the adder circuit 160, but if the output of the logic circuit 140 is m bits, the output of the adder circuit 160 is m+1 bits, so The large amplitude portion is clipped to m bits.

Next, the error between the conventional example shown in FIG. 2 and the embodiment of the present invention shown in FIGS. 1 and 5 will be described. By using clipping circuit 10, the dynamic range will be reduced by one digit. When m=8, the dynamic range only decreases from 255 digits to 254 digits, a decrease of only 0.4% at most, which is at a completely acceptable level.

Next, errors in the rounding circuits 20 and 21 will be described. Table 2 shows the relationship between the output value of the BPF shown in FIG. 2 and the output value of the BPF shown in FIG.

Margin below Table 2 The maximum error is ±LSB, which is a level that does not pose a problem.

Furthermore, the logic circuit 140 can combine the rounding circuit 20 with the sign inverting circuit 130 or the sign inverting circuit 130 with the rounding circuit 2.
Since the average value of 2 is taken, the error is not magnified by the logic circuit 140.

〔Effect of the invention〕

According to the present invention, unnecessary overflow does not occur, and the circuit scale can be reduced.

Further, by using a rounding circuit as appropriate, unnecessary arithmetic circuits can be removed and the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional YlClC shunt circuit configuration, FIG. 3 is a block diagram showing an example of a conventional BPF, and FIG. 4 is a block diagram showing an example of the conventional BPF. A circuit diagram of a clip circuit according to the invention, FIG. 5 is a block diagram showing another embodiment of the invention. 10... Clip circuit. 20-22...Marume circuit. 110.111...Line memory. 120-122-BPF. 130.131... Sign inversion circuit. 140...Logic circuit. No.? Concave/2θ 5th rhyme

Claims (1)

[Claims] 1. In a signal processing circuit having a sign inverting circuit for inverting the sign of a digital signal expressed as a two's complement of m bits (m is a positive integer), the signal is input before the sign inverting circuit. A clip circuit is provided to limit the amplitude of the digital signal, and the clip circuit clips the minimum number that can be expressed by m bits so that the number is one digit larger than the minimum number, and the clip circuit performs clip processing. A digital signal processing circuit characterized in that the sign inversion circuit processing is performed using the signal obtained by the above processing. 2. In the digital signal processing circuit that separates the composite video signal into a luminance signal and a carrier color signal, the input m bits (
a first clipping circuit that limits the amplitude of a composite video signal (m is a positive integer); a first BPF that limits the band of the output signal of the first clipping circuit; and delaying the output of the first clipping circuit. a first line memory for band-limiting the output of the first line memory, a second BPF for band-limiting the output of the first line memory;
a first rounding circuit that rounds off the decimal point of the output signal of the PF, a second rounding circuit that rounds off the decimal point of the output signal of the second BPF, and a second rounding circuit that delays the output of the second rounding circuit. a line memory, a sign inverting circuit for inverting the sign of the output signal of the second rounding circuit, an output of the first rounding circuit, an output of the sign inverting circuit, and the second rounding circuit;
a logic circuit that receives as input the output of the first line memory, an adder circuit that adds the output of the logic circuit and the output of the first line memory with an appropriate delay, and converts the output of the adder circuit into an m-bit signal. a second clip circuit that limits the amplitude; and a sign inversion circuit that inverts the sign of the output of the logic circuit;
A digital signal processing circuit characterized in that the output of the second clip circuit is an output of a separated luminance signal, and the output of the sign inversion circuit is an output of a separated carrier color signal.