JPH03278201A - Protection device for control system - Google Patents

Abstract

PURPOSE:To inhibit a driving device from driving a target to be controlled, to protect plural driving devices and plural targets to be controlled and to prevent the generation of a failure by detecting the stop of a control clock signal by a stop detecting means based upon a reference clock signal. CONSTITUTION:When a control clock signal phi is stopped, a decision circuit 50 decides the stop of the control clock signal phi based upon the reference clock CLK and outputs a stop signal to a stopping circuit 52 to stop the operation of respective driving circuits 40, 42, 44, so that respective driving circuits 40, 42, 44 and the targets (a printing head 6, a CR motor 7 and an LF motor 9) to be driven are protected and the generation of parts damage or overheat can surely be prevented. Since the circuit 50 is constituted so as to be driven synchronously with the reference clock CLK, the circuit 50 can be continuously normally driven even when the control clock signal phi is stopped and an electronic control part 5 and a printing mechanism 3 can be protected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control system protection device that protects a control system that includes a central processing unit and a drive device that operates under the control of the central processing unit.

[Prior Art] Conventionally, in a control system equipped with a central processing unit (CPU) and a drive device under the control of the central processing unit (CPU), for example,
The PU determines whether or not a detection signal is input at a predetermined period from a detector that detects the operating state of the drive device, and if the detection signal is not input at a predetermined period, the PU starts the drive device after the timer has counted a predetermined time. It has a protection function that prevents the drive unit from malfunctioning by stopping it (Japanese Patent Laid-Open No. 55-1014
Publication No. 88).

In this type of control system, if an abnormality occurs in the CPU itself, the above protection function is not activated and failure of the drive unit cannot be prevented. When this occurs, a device that outputs a reset signal to the CPU to return the CPU to its initial state (
A watch dog timer (also called a watch dog timer) is often provided. For example, a control program may be configured so that the CPU executes a predetermined interrupt process and outputs a pulse signal every time an interrupt signal is input from the outside at a predetermined period, and when the period of the pulse signal exceeds a predetermined range. It has been considered to protect the control system by attaching a multivibrator circuit that outputs a reset signal to the reset terminal of the CPU when the CPU changes.
5291).

[Problems to be Solved by the Invention] However, the above-mentioned protection device can perform the protection function in the case of an asynchronous control system in which the drive device operates at its own timing without depending on the control clock signal generated by the CPU. However, in the case of a synchronous system in which the operating timing of the drive device is determined based on a control clock signal, the protection function cannot be achieved. For example, when the CPU executes an instruction to stop its own operation (for example, a HALT instruction) in order to enter a power saving mode, or when the CPU receives noise as a stop command signal of the control clock signal and malfunctions. In this case, the CPU itself stops operating and the control clock signal also stops, so not only will the drive unit become uncontrollable, but if a heat generating device, high torque motor, etc. is used as the drive unit, This will cause a malfunction.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a control system protection device that can protect the control system even if the control clock signal of the central processing unit stops.

[Means for Solving the Problems] The gist of the present invention is to provide an oscillation circuit that generates a reference clock signal, and a control clock signal that drives and controls a controlled object based on the reference clock signal from the oscillation circuit. A protection device for a control system that protects a control system including a central processing unit that generates a control clock signal and a drive device that drives a controlled object based on a control clock signal generated by the central processing unit, a stop detecting means for detecting a stop of the control clock signal based on the stop detecting means; and a drive inhibiting means for prohibiting the drive device from driving the controlled object when the stop detecting means detects the stop of the control clock signal. A control system protection device characterized by:

[Operation] According to the control system protection device of the present invention configured as described above, when the stop detection means detects the stop of the control clock signal based on the reference clock signal, the drive prohibition means prevents the drive device from controlling the control clock signal. Prohibits driving of target. That is, when the control clock signal stops, the operation timing of the drive device cannot be determined, but at this time, the drive operation of the drive device is prohibited to protect the drive device and the controlled object.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 1 is a block diagram showing the electrical configuration of a printer to which the present invention is applied.

The printer is a dot-impact type serial printer, and includes a printing mechanism section 3 and an electronic control section 5 as main parts.

The printing section 3 includes a print head 6 mounted on a carriage (path shown), a stepping motor (hereinafter referred to as CR motor) 7 that drives the carriage, and a stepping motor (hereinafter referred to as CR motor) 7 that drives the platen (path shown). 9 (hereinafter referred to as an LF motor) is provided.The mechanical configuration of the printing mechanism section 3 is well known, so the details will be omitted.

The print head 6 includes dot wires (paths shown) arranged in a matrix in the same direction of movement, and a solenoid 1 which drives each dot wire in the printing direction. Print head drive circuit 4
The energization is controlled by 0.

The electronic control unit 5 has CPUs 3 connected to each other via a bus 30.
2. It is configured as a logical operation circuit mainly including ROM 34, RAM 36, and input/output circuit 38, and the input/output circuit 38 includes a print head drive circuit 40, a CR motor drive circuit 42,
An LF motor drive circuit 44 is connected. Further, the electronic control unit 5 includes an oscillation circuit 46 that outputs a reference clock signal CLK, a determination circuit 50 that determines whether a control clock signal (described later) φ generated by the CPLI 32 has stopped, and a determination circuit 50 A stop circuit 52 is provided that stops each drive circuit 40, 42, 44 based on the determination result.

In this embodiment, the determination circuit 50 corresponds to stop detection means, and the stop circuit 52 corresponds to drive prohibition means.

The CPLI 32 is a C-MOS (complementary metal oxide semiconductor) type microprocessor that generates a control clock signal φ from the reference clock signal CLK and outputs it to the input/output circuit 3.
8. Output to print head drive circuit 40 and determination circuit 50. Furthermore, in order to reduce power consumption, the CPU 32 executes an operation stop command (for example, a HALT command).
Alternatively, it has a function (referred to as low power consumption mode or power down mode) of stopping the control clock signal φ by inputting a stop signal from the outside to the ST○P terminal.

The ROM 34 stores various processing programs as well as dot patterns corresponding to each character and figure, excitation timing data (pulse rate) of the CR momo-7, energization time data of one solenoid 11, and the like.

The print head drive circuit 40 includes a dot pattern latch 60 and an energizing circuit 62, and the energizing circuit 62 includes a power transistor 64 that energizes each solenoid 1 and an AND gate 66 connected to its base terminal. The print head drive circuit 40 is connected to one input terminal T of the AND gate 66 from the input/output circuit 38 via the stop circuit 52.
The CR module is activated based on the energization command signal Sdr inputted to the input terminal T1 and the dot pattern data inputted to the other input terminal T2 via the dot pattern data latch 60.
At each step of movement of the print head 6 in the printing direction in synchronization with the stepwise movement of step 7, the solenoid 11 is selectively energized for a predetermined period of time to record a pattern corresponding to predetermined print data. The energization command signal Sdr remains at High level for a predetermined period of time measured based on the control clock signal φ, and the solenoid 11 becomes energized, and the solenoid 11 specified by the dot pattern data is actually energized. =
8- I can do it. Characters and figures are printed on a matrix of a predetermined size by performing energization a predetermined number of times in conjunction with the above-mentioned moving step.

The dot pattern data latch 60 supplies the dot pattern data input from the input/output circuit 38 to the energization circuit 62.

The CR motor drive circuit 42 energizes each phase of the CR motor 7 in a predetermined sequence based on the pulse signal Spc input from the input/output circuit 38 via the stop circuit 52. That is, the input/output circuit 38 generates a pulse signal Sp at a predetermined rate based on the excitation timing data of the ROM 34.
c is generated and output to the CR motor drive circuit 42 in synchronization with the coarse control clock signal φ. Based on this pulse signal Spc, the CR motor drive circuit 42 drives the CR momo-7 at a predetermined speed. The LF motor drive circuit 44 also drives the motor 9 based on the pulse signal Spl input from the input/output circuit 38 via the stop circuit 52.

The oscillation circuit 46 is a well-known crystal oscillator, and outputs a reference clock signal (square wave) of a predetermined frequency to the CPU 32 and the determination circuit 50.

As shown in FIG. 2, the determination circuit 50 is integrated into one LSI chip as a gate array together with a stop circuit 52, and includes five 1-bit counters (hereinafter simply referred to as counters) 70 to 74, flip flop 75,
It is composed of logic circuit elements 76 to 80. The counter 70 and the flip-flop 75 are connected to the oscillation circuit 46.
The rising and falling timings of the reference clock signal CLK input from
The counters 72 and 74 each output a signal obtained by dividing the frequency of LK into 1/4 and the counter 7 outputs a signal obtained by dividing the frequency into 1/8.
The circuit is configured such that signals 1, 72, 73, and 74 are reset when the control clock φ is at the low level and the high level, respectively.

The determination circuit 50 determines C based on the reference clock signal CLK.
It is determined whether the control clock signal φ is input from the PU 32 at a predetermined period, and when it is determined that the control clock signal φ has stopped (when the signal level is fixed at a constant level of High or Low), the output signal Sem level of H
It switches from high to low and outputs it to the stop circuit 52.

That is, as shown in FIG. 3, when the control clock φ is normal, the counters 71, 72 and 73, 74 are reset periodically and alternately by the control clock φ.
The output levels of the counters 72 and 74 are always Low (columns (d) and (f) in the figure). Therefore, since the output of the flip-flop 75 remains latched at the Hgh level (column (1) in the figure), the level of the output signal Sem of the determination circuit 50 is at the Hgh level.

However, the control clock signal φ stops and goes low (tl).
When the level state is fixed, the counters 73 and 74 are not reset, so the control clock signal φ is stopped (tl
), at the time (t2) when the output signal of the counter 70 (column (b) in the figure) rises, the output signal of the counter 74 becomes H.
Become intense. Then, at the second fall point (t3) of the reference clock signal CLK after the High point (t2) of the counter 74, the output level of the flip-flop 75 becomes Low, so the output signal Sem of the determination circuit 50 becomes It becomes Low level. After the output signal of the counter 74 becomes High level,
At the falling edge of the fourth cycle of the reference clock signal CLK (
At t4), the output level of the flip-flop 75 becomes low again, but since the low output of the flip-flop 75 is fed back to the gate 77 (column (i) in the figure), the output level of the flip-flop 75 becomes low. The output signal Sem of the determination circuit 50 remains at the Low level.

Although not shown in FIG. 2, all the counters 70 to 74 and the flip-flop 75 are configured to be reset when the printer is started and when the CPU 32 is reset.

The stop circuit 52 includes three AND gates 52a, 52c,
52c, the input signal Sem from the 2 judgment circuit 50
When the level of is High, the level of the signal inputted from the input/output circuit 38 is output to each drive circuit 40, 42, and 44 as is.

On the other hand, when the level of the input signal Sem is Low, regardless of the level of the input signal from the determination circuit 50,
A level signal is output to each drive circuit 40, 42, 44. That is, when the level of the input signal Sem from the determination circuit 50 is Low, the energization of the solenoid 1 is stopped, and the driving of the CR motor 7 and the LF motor 9 is also stopped.

Here, in the electronic control unit 5 configured as described above, when the CPU 32 is executing processing for printing, noise (NOIsE) is generated from the 5TOP terminal for some reason.
) is input and the control clock signal φ is stopped. Or,
Assume that a CPU stop command is written in the print processing program by mistake (there is a so-called program bug), and that the control clock signal φ is stopped because this command is executed. In the print head 6, the solenoid 11 (X-
When the control clock signal φ stops while the CR momo-7 is energized and is also rotating, the control starts [-The energization time is measured by the cock φ, and when a predetermined time elapses, the solenoid] The print head drive circuit 40, which stops energizing the print head 1, continues to energize the print head 1, assuming that the predetermined time has not elapsed. The CR motor drive circuit 42 may also fail to timely energize the CR momo-7, and the CR momo-7 may remain energized. As a result, the resolenoid 1 whose power transistor was destroyed and the CR momo 7 overheat.

However, in the electronic control unit 5, when the control clock signal φ stops, the determination circuit 50 outputs a stop signal (the level of the signal Sem is High) to the stop circuit 52, and in response, the stop circuit 52 outputs a stop signal to the print head drive circuit. 40 is stopped, and the driving of the CR momo-7 by the CR motor drive circuit 42 is stopped (although the LF motor 9 is not driven,
[Prevent the F motor drive circuit 44 from operating].

As explained above, in this embodiment, when the control clock signal φ stops, the determination circuit 50 determines that the control clock φ has stopped based on the reference clock CLK, and the stop circuit 50 determines that the control clock signal φ has stopped based on the reference clock CLK.
2 and output a stop signal to each drive circuit 40, 42, 44.
Each drive circuit 40.42.44
And the objects to be driven (print head 6, CR motor 7, LF motor 9) can be reliably prevented from being damaged or overheated.

Furthermore, since the determination circuit 50 is configured to operate in synchronization with the reference clock CLK, the control clock φ
can operate normally even if the electronic control unit 5 stops.
And the printing mechanism 3 can be protected.

In this embodiment, the electronic control unit 3 of a printer has been described as an example, but the present invention can also be applied to a control system including a drive device that drives a controlled object based on a control clock signal of a central processing unit. Applicable to various types of systems.

[Effects of the Invention] As detailed above, according to the present invention, when the stop detection means detects the stop of the control clock signal based on the reference clock signal, the drive prohibition means prohibits the drive device from driving the controlled object. 15- It is possible to protect the drive device and the controlled object and prevent their failure.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the electrical configuration of the printer, Figure 2 is a block diagram showing the electrical configuration of the printer.
The figure is an electronic circuit diagram of the determination circuit, and FIG. 3 is a timing chart showing the operation of the determination circuit. 3... Printing mechanism section 5... Electronic control section 32...C
PU 40... Print head drive circuit 42... CR motor drive circuit 44... LF motor drive circuit 46... Oscillation circuit 50... Judgment circuit 52... Stop circuit

Claims (1)

[Scope of Claims] An oscillation circuit that generates a reference clock signal, a central processing unit that generates a control clock signal for driving and controlling a controlled object based on the reference clock signal from the oscillation circuit, and A drive device that drives a controlled object based on a control clock signal generated by a control system, and a stop that detects a stop of the control clock signal based on the reference clock signal. Protection of a control system, comprising: a detection means; and a drive prohibition means for prohibiting the drive device from driving a controlled object when the stop detection means detects a stop of the control clock signal. Device.