JPH03276742A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03276742A JPH03276742A JP7806590A JP7806590A JPH03276742A JP H03276742 A JPH03276742 A JP H03276742A JP 7806590 A JP7806590 A JP 7806590A JP 7806590 A JP7806590 A JP 7806590A JP H03276742 A JPH03276742 A JP H03276742A
- Authority
- JP
- Japan
- Prior art keywords
- polycell
- clock driver
- semiconductor integrated
- power supply
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ポリセル方式のマクロセルを有する半導体集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a polycell type macro cell.
従来のポリセル方式のマクロセルを有する半導体集積回
路は、接続情報を基に最適配置を考慮して行なっていた
為、クロックドライバは第３図に示すように、各ポリセ
ルの夫々に分岐されて配置されていた。Conventional semiconductor integrated circuits with polycell-type macrocells have been designed with optimal placement taken into consideration based on connection information, so the clock driver is placed separately for each polycell, as shown in Figure 3. was.
上述した従来の半導体集積回路は、入力バッファのクロ
ックドライバから各々のポリセルマクロ内のクロックド
ライバに接続される配線長及び、ポリセル内のクロック
ドライバからフリップフロップ等に接続される配線長に
ばらつきがあり、ハードマクロのクロックドライバから
フリップフロップまでの遅延がスキューとして生じる。The conventional semiconductor integrated circuit described above has variations in the length of the wiring connected from the clock driver of the input buffer to the clock driver in each polycell macro, and the length of the wiring connected from the clock driver in the polycell to the flip-flop, etc. The delay from the hard macro clock driver to the flip-flop occurs as skew.
また、ポリセル内にクロックドライバが多くある場合、
同時に動作する為、電源にノイズが乗るが、ポリセルの
高さ（列方向の幅）が一定の為、電源線幅が−律になり
、ノイズを減らす為には、全てのセルの高さを大きくす
る必要があるという欠点がある。Also, if there are many clock drivers in a polycell,
Because they operate simultaneously, noise is added to the power supply, but since the height of the polycell (width in the column direction) is constant, the width of the power supply line becomes a rule, so to reduce noise, the height of all cells must be adjusted. The disadvantage is that it needs to be large.
本発明のクロックドライバは、ポリセル内のクロックド
ライバを少くとも一つの行に集中させると共に、該クロ
ックドライバのトランジスタサイズや電源線幅を他のポ
リセルの寸法より大きくするという特徴を有している。The clock driver of the present invention is characterized in that the clock drivers in a polycell are concentrated in at least one row, and the transistor size and power line width of the clock driver are made larger than the dimensions of other polycells.
次に、本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は、本発明の第１の実施例を示す
レイアウト図及びＡ部拡大図である。FIGS. 1(a) and 1(b) are a layout diagram and an enlarged view of part A showing a first embodiment of the present invention.
一般にＬＳＩを設計する場合、論理接続情報を記述する
が、ポリセルマクロの自動配置配線を行なう時に、クロ
ックドライバのみ抽出し、−辺に集中させ（第１図の場
合は上辺）、駆動するセルの個数、周波数、ブロックサ
イズに従って、トランジスタサイズ、電源線幅の最適な
りロックトライバを配置する。Generally, when designing an LSI, logical connection information is described, but when automatically placing and routing a polycell macro, only the clock driver is extracted and concentrated on the - side (in the case of Figure 1, the upper side), and the cells to be driven are The lock driver is arranged according to the number of transistors, frequency, and block size to optimize the transistor size and power supply line width.
第２図は本発明の第２の実施例を示すレイアウト図であ
る。ここでポリセルマクロ内に配置するクロックドライ
バを、マクロの中央に配置することによって、配線長の
ばらつきを減らし、スキューを減少させることができる
という利点かある。FIG. 2 is a layout diagram showing a second embodiment of the present invention. By arranging the clock driver in the polycell macro at the center of the macro, there is an advantage that variations in wiring length and skew can be reduced.
以上説明したように、本発明は、同期式回路のポリセル
マクロ内でのクロックドライバの配置に関し、特に、論
理接続情報から、自動で配置配線する場合、マクロ内の
クロックドライバを抽出し、チップの一辺に配置すると
共に、クロックドライバ専用に、トランジスタのサイズ
、電源線幅を最適化することにより、スキュー及び電源
ノイズを低減できる効果がある。As explained above, the present invention relates to the placement of a clock driver in a polycell macro of a synchronous circuit, and in particular, when automatically placing and routing based on logical connection information, the present invention extracts the clock driver in the macro and By optimizing the transistor size and power supply line width exclusively for the clock driver, skew and power supply noise can be reduced.
第１図（ａ）、（ｂ）は本発明の第１の実施例を示すレ
イアウト図及びＡ部拡大図、第２図は本発明の第２の実
施例のレイアウト図、第３図は従来の半導体集積回路の
一例を示す１４７９１〜図である。
１・・・入力バッファ（クロックドライバ）、２・・・
ポリセルマクロ、３・・・ポリセルマクロ内のクロック
ドライバ、４・・・ポリセル部、６，６ａ・・・電源線
、７，７ａ・・・拡散層、８・・・ゲート。FIGS. 1(a) and (b) are layout diagrams and enlarged views of part A showing the first embodiment of the present invention, FIG. 2 is a layout diagram of the second embodiment of the present invention, and FIG. 3 is a conventional FIG. 14791 is a diagram illustrating an example of a semiconductor integrated circuit of FIG. 1... Input buffer (clock driver), 2...
Polycell macro, 3... Clock driver in polycell macro, 4... Polycell portion, 6, 6a... Power supply line, 7, 7a... Diffusion layer, 8... Gate.
Claims (1)
において、前記マクロセル内のポリセルを駆動するクロ
ックドライバを少くとも一つの行の前記ポリセルに集め
て設けたことを特徴とする半導体集積回路。 ２、クロックドライバを有する行のポリセルをそれ以外
のポリセルより列方向の幅を大きくした請求項１の半導
体集積回路。 ３、クロックドライバを有する行のポリセルに配置する
電源配線の線幅をそれ以外のポリセルに配置する電源配
線の線幅よりも広くした請求項１の半導体集積回路。[Scope of Claims] 1. A semiconductor integrated circuit having polycell-type macrocells, characterized in that clock drivers for driving polycells in the macrocells are provided collectively in the polycells of at least one row. circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the polycell in the row having the clock driver has a width larger in the column direction than the other polycells. 3. The semiconductor integrated circuit according to claim 1, wherein the line width of the power supply wiring arranged in the polycell in the row having the clock driver is wider than the line width of the power supply wiring arranged in the other polycells.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7806590A JPH03276742A (en) | 1990-03-27 | 1990-03-27 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7806590A JPH03276742A (en) | 1990-03-27 | 1990-03-27 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03276742A true JPH03276742A (en) | 1991-12-06 |
Family
ID=13651446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7806590A Pending JPH03276742A (en) | 1990-03-27 | 1990-03-27 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03276742A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19731714C2 (en) * | 1996-11-29 | 2001-08-09 | Mitsubishi Electric Corp | Integrated semiconductor circuit device with macro cell layout areas and clock driver circuits |
-
1990
- 1990-03-27 JP JP7806590A patent/JPH03276742A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19731714C2 (en) * | 1996-11-29 | 2001-08-09 | Mitsubishi Electric Corp | Integrated semiconductor circuit device with macro cell layout areas and clock driver circuits |
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