JPH1032261A - Designing method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control both an N-channel and a P-channel transistor in cell driving force keeping a wiring result, as it is after the transistors are arranged and wired by a method wherein both the N-channel and the P-channel transistor constituting an output driver are arranged under and above other circuits respectively making their gates lie in a lateral direction. SOLUTION: A P-channel transistor comprised in an output driver is formed in a P-type diffusion region 5A, and an N-channel transistor also comprised in the output driver is formed in an N-type diffusion region 6A. Another P- channel transistor is formed in a P-type diffusion region 5B, and another N- channel transistor is formed in an N-type diffusion region 6B. That is, the P-channel transistor and N-channel transistor of an invertor are arranged above or below a cell respectively forming a right angle with each other. The gates 7A and 7B of the transistors are arranged in a horizontal direction. By this setup, when a cell is large in a crosswise direction, a channel can be set large in width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit for designing a cell, and more particularly to a method for adjusting a driving force of a cell in a driver section without changing a wiring result of a cell once laid out. The present invention relates to a design method that enables a high-speed operation by optimizing a delay time including a wiring delay.

[0002]

2. Description of the Related Art While the performance of devices has been improved with the miniaturization of LSIs, the ratio of the wiring delay time to the delay time of the entire circuit has been increasing. LSI
When designing a cell, a set of cells that can be used for the design, which is called a cell library, is prepared in advance. They are,
In many cases, the LSI is prepared corresponding to a process technology such as the 0.8 μm rule or the 0.5 μm rule, and many types of LSIs are designed using this library. The library is prepared so that the logic function, the delay data, and the pattern are collected for each cell and can be referred to by the user.

In a library, cells having the same logical function but different driving forces are prepared. For example, even with the same logic gate, in the case of a long wiring or when it is necessary to drive many fan-outs, it is necessary to use a cell in which the channel width of the transistor in the cell is increased.

FIG. 5 is a logic diagram of a CMOS-type four-input NOR circuit that outputs an output Y to four inputs A1, A2, A3, and A4. In FIG. 5, 31 and 32 are NOR gates, 33 is a NAND gate, and 34 is an inverter as an output driver. FIG. 6 shows a specific circuit diagram. MP1 to MP7 are p-channel transistors, MN1
To MN7 are n-channel transistors.

FIG. 7 is a diagram showing a layout pattern of the circuit shown in FIGS. 41 is a power supply wiring made of a metal 1 layer, 42 is a ground wiring made of a metal 1 layer, and 43 is n
Well, 44 is a p-well, 45 is a p-diffusion region where the source and drain of a p-channel transistor are formed, 46 is an n-diffusion region where the source and drain of an n-channel transistor are formed, 47 is a gate made of polysilicon, 48
Is a contact hole or a through hole. In FIG. 7, the crossed wiring is a metal layer and polysilicon.

This layout method is described in "T. Uehara and W.
M.vanCleemput: "Optimal layout of CMOS functionl arr
ays, "IEEE Trans. Comput., vol. C-30, pp. 305-312, May 1
981. ", a pair of a p-channel transistor and an n-channel transistor connected to a common input contact so that the polysilicon gate 47 is in the vertical direction (vertical direction in FIG. 7) and The arrangement is such that the source and drain diffusion regions are arranged adjacently and can be shared, and the lateral width (width in the left-right direction in FIG. 7) of the cell is minimized. This layout method has been widely adopted in the past.

[0007] The channel width of the transistor of the cell laid out in this way is determined from the driving force on the assumption of an average wiring length. In addition, for a certain type of cell, a cell having a large channel width is prepared so that the cell can be used particularly in a place requiring a large driving force.

In a conventional LSI design, a designer determines in advance which cell of a cell library to use for each cell in a netlist. In consideration of the number of fan-outs of the nets driven by the cells and the expected wiring length, cells that are determined to require a higher driving force are replaced in advance with cells having a higher driving force. Using the netlist created in this manner, automatic layout and wiring are performed to generate an LSI layout. After automatic layout, it can be said that the wiring length cannot be kept within the limit.

After the automatic layout, the delay time is evaluated using the obtained wiring length, and as a result, a case is considered in which there is a cell that needs to increase the driving force. In this case, it is also possible to take an approach of finding a cell capable of realizing the required delay time from the cell library, replacing the cell with the cell, and performing automatic layout again. However, even with the same logical function, a cell having a large driving force is generally large in size, so that the position where the replacement cell is arranged is shifted from the original cell position, so that only the cell cannot be replaced without changing the wiring. .

[0010]

As described above, it is impossible to replace a certain cell with another cell having a different driving force while maintaining the wiring after layout. Therefore, the delay time is evaluated based on the wiring result, the necessary cells are replaced based on the result, and the layout is performed again using the new netlist after the replacement. Need to be repeated until However, there is no guarantee that a solution can be obtained by such an iteration, and the iteration itself requires an extremely large amount of design time.

On the other hand, on the other hand, there is a margin for the restriction of the delay time, and the restriction of the delay time may be satisfied even if the driving force of a certain cell is reduced. In such a case, it is also possible to reduce the power consumption by replacing the cell with a cell having a small driving force. As described above, from the great demands for higher performance and lower power consumption of LSI, it is increasingly necessary to adjust the delay time by adjusting the driving force of the cells of the LSI.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit capable of adjusting a driving force of a cell after arranging and wiring and maintaining a wiring result. It is to provide a design method.

[0013]

A first invention is a CMOS device.
In the method of designing a semiconductor integrated circuit configured by
A plurality of transistors constituting another circuit unit except the output driver unit in the cell have gates arranged vertically and in parallel to share a diffusion region corresponding to a source and a drain,
The n-channel transistor and the p-channel transistor constituting the output driver section are arranged above and below the other circuit section so that their gates are in the horizontal direction.

In a second aspect based on the first aspect, an n-channel transistor and a p-channel transistor constituting the output driver section are provided.
The channel width of the channel transistor is adjusted between a preset minimum value and a maximum value in the horizontal direction.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, for example, FIG.
Is divided into an output driver section A serving as an output driver of the cell and a circuit section B other than the output driver section. In the circuit section B, according to a conventional layout method, the source and drain diffusion regions are shared as much as possible, and are arranged adjacent to each other and laid out. Further, the channel width of the circuit section B is made sufficiently small, and its area is made small. On the other hand, the p-channel transistor of the output driver section A is arranged above the cell (above the circuit section B), the n-channel transistor is arranged below the cell (below the circuit section B), and the circuit section B
Are arranged so as to be rotated by 90 degrees with respect to the other transistors.
Therefore, the gates of the transistors of the output driver section A are arranged horizontally (horizontally), and in the case of a cell having a large width, a large channel width can be set.

In such a configuration, even if the channel width of the circuit portion B of the cell is fixed, the channel width of the transistor of the output driver portion A can be changed. Therefore, the driving force of the cell can be adjusted by changing / adjusting the channel width of the output driver section A. Therefore, a pattern laid out in advance can be used as it is, except for the diffusion pattern of the output driver unit A, and only the rectangular pattern corresponding to the diffusion pattern of the output driver unit A can be changed to obtain a pattern of cells having different driving forces.

The details will be described below. FIG. 1 shows one embodiment of the present invention.
FIG. 14 is a diagram illustrating a pattern of a cell layout according to one embodiment. Reference numeral 1 denotes a power wiring of a metal 1 layer, and reference numeral 2 denotes a ground wiring of a metal 1 layer. Have been. The cell height (the height in the vertical direction in FIG. 1) is unified to a predetermined value, and the power wiring position and the ground wiring position are also unified, so that this cell is placed adjacent to another cell in the horizontal direction. In this case, the power supply wiring 1 and the ground wiring 2 are automatically connected to other cells. 3 is n
Wells, 4 are p wells, 5A, 5B are p diffusion regions where the source and drain of a p-channel transistor are formed, 6
A and 6B are n-diffusion regions where the source and drain of an n-channel transistor are formed, 7 is a polysilicon gate,
8 is a contact hole or a through hole.

FIG. 2 shows the same circuit as the NOR circuit described with reference to FIG.
The NOR gates 31 and 32 and the NAND gate 33 are used as another circuit section B. In FIG. 1, the p-channel transistor MP7 of the output driver section A is formed in the p-diffusion region 5A, the n-channel transistor MN7 is formed in the n-diffusion region 6A, and the other p-channel transistors are formed in the p-diffusion region 5B. The n-channel transistor is formed in n diffusion region 6B. That is, the p-channel transistor MP7 of the inverter 34 is located above the cell,
The n-channel transistor MN7 is arranged below the cell so as to be rotated by 90 degrees with respect to each of the other transistors, and the gates 7 of the transistors MP7 and MN7 are arranged.
A and 7B are arranged in the horizontal direction.

In FIG. 1, the channel width of the p-channel transistor MP7 of the inverter 34 arranged in the horizontal direction in the p-diffusion region 5A is within the range of the cell width.
The channel width of the n-channel transistor MN7 arranged in the horizontal direction in the n-diffusion region 6A can be changed between a predetermined lower limit value W _{(p) min} and an upper limit value W _{(p) max.} Lower limit W _{(n) min} and upper limit W _{(n) max}
Can vary between. The contact holes of the drains indicated by reference numerals 8A and 8B are arranged close to the right side (in FIG. 1) of the diffusion regions 5A and 6A. These diffusion regions 5
A rectangular pattern showing A and 6A has a fixed right side and a left side adjustable between W _{(p) min} and W _{(p) max} , and between W _{(n) min} and W _{(n) max.} .

FIG. 3 shows a layout according to the layout method shown in FIG.
Driver cell 11 to be created and row driven by it
In the circuit in which the drain cells 12 are connected by the inter-cell wiring 13,
FIG. 9 is a diagram for explaining adjustment of delay time. Driver center
11 is a two-stage output driver unit A and other circuit unit B
Consists of Here, the output driver unit A (inverter
The channel width of the p-channel transistor of
Limit value W _{(p) min}And upper limit W_{(p) max}Between and also n-channel
Lowering the channel width of the transistor to the lower limit W_{(n) min}And upper limit W
_{(n) max}Can be freely adjusted between the two. The output driver
For the circuit section B other than the inverter section A, the MOS transistor
The channel width of the transistor is sufficiently small.

FIG. 4 shows a delay time T1 from the input section of the circuit section B to the input section of the output driver section A, a delay time T2 from the output driver section A to the input section of the load cell 12 and a delay time T2 of the driver cell 11 in FIG. Load cell 12 from input side
2 shows the relationship between the delay time T3 to the input side and the channel width of the transistor of the output driver section A. The sizing ratio on the horizontal axis in FIG. 4 represents the ratio W / W _init of the adjusted channel width W to the original value W _init of the channel width W of the transistor. Also, for simplicity, the p-channel transistor and the n-channel transistor have the same size ratio.

The delay time T1 increases in proportion to the channel width of the transistor of the output driver section A. The delay time T2 decreases in inverse proportion to the channel width. The latter is because the driving force increases as the channel width increases. Driver cell 1 to which these two delay times T1 and T2 are added
The delay time T3 from the input side of No. 1 to the input side of the load cell 12 changes as shown in FIG. Driver cell 11
It can be understood that when only the sizing ratio of the transistor of the inverter 34 of the output driver section A is changed from about 0.25 to about 1.5, the delay time can be changed by about 30%.

[0023]

As described above, according to the present invention, the n-channel transistor and the p-channel transistor constituting the output driver section in the cell are arranged above and below the other circuit sections so that the gates are in the horizontal direction. Therefore, it is possible to provide a sufficient margin for adjusting the channel width of these transistors in the cell width direction. Therefore, even after the layout and wiring of the automatic layout, only the channel width of the p-channel transistor and the n-channel transistor can be changed and adjusted. This change range is almost close to the cell width. As described above, since the driving force of the cell can be changed and adjusted, the delay time to the next stage can be adjusted. That is, it is possible to optimize the delay time only by changing a specific pattern in the cell while maintaining the wiring result by the automatic layout.

[Brief description of the drawings]

FIG. 1 is a pattern diagram showing a layout of a four-input NOR circuit according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a schematic layout of the 4-input NOR circuit.

FIG. 3 is a diagram for explaining a delay time of the 4-input NOR circuit.

FIG. 4 is a characteristic diagram of a delay time with respect to a sizing ratio of a transistor of the 4-input NOR circuit.

FIG. 5 is a logic circuit diagram of a 4-input NOR circuit.

FIG. 6 is a specific circuit diagram of the 4-input NOR circuit.

FIG. 7 is a pattern diagram showing a layout of the 4-input NOR circuit according to a conventional layout method.

[Explanation of symbols]

1: power supply wiring, 2: ground wiring, 3: n well, 4:
p well, 5A, 5B: p diffusion region, 6A, 6B: n diffusion region, 7, 7A, 7B: polysilicon gate, 8, 8
A, 8B: contact hole or through hole, 11: driver cell, 12: load cell, 13: wiring between cells, 3
1, 32: NOR gate, 33: NAND gate, 3
4: Inverter (output driver section), 41: Power supply wiring,
42: ground wiring, 43: n well, 44: p well, 45: p diffusion region, 46: n diffusion region, 47: polysilicon gate, 48: contact hole or through hole.

Claims (2)

[Claims] In a method of designing a semiconductor integrated circuit constituted by CMOS, a plurality of transistors constituting a circuit portion other than an output driver portion in a cell have a gate arranged in a vertical direction and in parallel with a source. And an n-channel transistor and a p-channel transistor forming the output driver section are arranged at upper and lower positions of the other circuit section so that the gates are in the horizontal direction. Semiconductor integrated circuit design method. 2. An n-channel transistor and a p-channel transistor constituting said output driver section adjust a channel width thereof between a predetermined minimum value and a maximum value in a horizontal direction. Design method described in.