JPH03276498A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accurately perform the defect analysis of a memory part using the redundancy by obtaining redundancy application information of the memory part even in the package state after chip assembling. CONSTITUTION:A chip 1 is provided with a circuit 4 which indicates application or non-application of redundancy in accordance with read signals SA0 to SA3 supplied from the external, a circuit 5 which outputs a bit indicating whether redundancy is applied or not correspondingly to the position of a RAM, and a circuit 6 which outputs a bit indicating the address of redundancy. That is, redundancy application information 50 indicating whether a memory part 3 uses the redundancy or not, which of macro RAMs 0 to 3 the redundancy is applied to, and which address the redundancy is applied to is obtained from this semiconductor integrated circuit device in the package state after chip assembling.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor integrated circuit device having a logic circuit section and a memory section having a redundant function, the present invention relates to a semiconductor integrated circuit device having a logic circuit section and a memory section. Application information can be obtained even in the packaged state after chip assembly,
A semiconductor integrated circuit device in which a logic circuit section and a memory section having a redundancy function are formed on the same chip, with the aim of accurately performing failure analysis of a memory section using redundancy. redundancy use output means for indicating whether or not the redundancy is being used; redundancy memory location output means for indicating the memory location where the redundancy is being performed; and redundancy address output means for outputting the address where the redundancy is being performed. and is configured to output redundant application information in response to a read signal supplied from the outside in a packaged state after chip assembly.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a logic circuit section and a memory section having a redundant function.

In recent years, logic circuit sections composed of gate arrays, etc. and RAM
LSIs equipped with memory units such as the following are provided. In such LSIs, a redundant circuit is provided in the memory section to improve the yield, but there is a demand for making it possible to recognize redundant application information in the memory section from the outside.

[Prior art] In recent years, logic circuit sections composed of gate arrays, etc. and RAM
However, the yield of such LSIs is determined by the probability that both the logic circuit section and the memory section will be good products at the same time. By the way, in general, it is difficult to use redundant circuits in the logic circuit section because there is no regularity, but since the memory section consists of identical cells arranged regularly, it is possible to prevent failures by installing extra cells. Cell rescue is relatively easy.

Therefore, in the above-described semiconductor integrated circuit device including a logic circuit section and a memory section, a redundant circuit is provided in the memory section to repair defective cells.

[Problem to be solved by the invention]

As described above, in a conventional semiconductor integrated circuit device including a logic circuit section and a memory section, the memory section has a redundant function in order to improve yield.

However, a semiconductor integrated circuit device in which such a memory section and a logic circuit section are formed on the same chip, for example, R
In LSIs in which AM and logic circuits are integrated, it is difficult to determine which RAM is redundant among the many RAMs, or which address is to be rescued if redundancy is applied. Previously, there was no way to know if they were there. For this reason, in LSIs in which redundant circuits are provided in the memory section, it is not possible to output redundancy application information in the memory section to the outside in the packaged state after the chip is assembled, and the memory section using redundancy It was difficult to perform accurate failure analysis.

In view of the problem of the conventional semiconductor integrated circuit device described above, the present invention provides a semiconductor integrated circuit device having a logic circuit section and a memory section, in which redundant application information in the memory section can be obtained even in a packaged state after chip assembly. The purpose of this invention is to accurately analyze defects in memory units using redundancy.

[Failure to solve the problem]

FIG. 1 is a block diagram showing the principle structure of a semiconductor integrated circuit device according to the present invention.

According to the present invention, in a semiconductor integrated circuit device in which a logic circuit section 2 and a memory section 3 having a redundant function are formed on the same chip, it is determined whether or not redundancy is used in the memory section 3. redundancy use output means 4 indicating the redundancy use output means 4; and redundancy memory position output means 5 indicating the memory location where the redundancy is being performed.
and redundant address output means 6 for outputting the address where the redundancy is performed, and outputs redundancy application information in response to a read signal supplied from the outside in a packaged state after chip assembly. A semiconductor integrated circuit device is provided.

[For production]

According to the semiconductor integrated circuit device of the present invention, the redundant use output means 4 outputs information as to whether redundancy is used in the memory section 3 in response to a read signal supplied from the outside, and outputs the redundant memory position. The means 5 outputs information on memory locations where redundancy has been performed, and the redundant address output means 6 outputs information on addresses where redundancy has been performed. by this,
In a packaged state after chip assembly, redundant application information can be output in response to a read signal supplied from the outside, allowing detailed failure analysis of the memory section.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram conceptually showing how redundancy is applied in an example of the semiconductor integrated circuit device of the present invention. As shown in the figure, in the semiconductor integrated circuit device of this example, a logic circuit section 2 and a memory section 3 are formed on the same chip 1.

The logic circuit section 2 is composed of a gate array, and, for example, predetermined logic gates are formed in accordance with a user's request. The memory section 3 has four macros (units) RAM0 to R.
A? Each macro (memory cell) RAM0 to RAM3 has a 4-word structure of 0 to 3, and one spare (redundant) word is provided.

As shown in FIG. 2, in the semiconductor integrated circuit device of this example, redundancy is applied to macro RA) 10, and when word 1 in macro RAM 0 is selected, it is switched to a spare word. It looks like this.

In addition, redundancy is not applied to macro RAMI and RAM2, and if word 3 in macro RAM 3 is defective and word 3 in macro RAM 0 is selected, the switch will be made to a spare word. ing.

Here, word O in each macro RAM0 to RAM3
In the addresses 1 to 3, word 1 is set to 0, 0, . . . by 2-bit signals ADO and MDI. Word 1 is 0. l, word 2
is 1.0, word 3 is 1.1, and so on.

As shown in FIG. 2, the chip 1 includes a circuit 4 that outputs a bit indicating application/non-application of redundancy according to a read signal (S^0 to 5A3) supplied from the outside, and a RAM.
A circuit 5 that outputs a bit indicating whether redundancy is applied or not corresponding to the position of , and a circuit 6 that outputs a bit indicating a redundant address are provided. That is, in the semiconductor integrated circuit device of this example, from the device in the packaged state after the chip is assembled, (1) whether the memory section 3 uses redundancy, (2) which macro RAM0 to RAM3
It is possible to obtain redundancy application information (So) such as whether redundancy is applied to the address, and (2) to which address redundancy is applied.

FIG. 3 is a circuit diagram showing a main part of a semiconductor integrated circuit device as an embodiment of the present invention in which the redundancy shown in FIG. 2 is applied. An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

The circuit 4 that outputs a bit indicating application/non-application of redundancy is
Decoder circuit 4a+fuse circuit 40. NOR game
1-4b and OR game) 4c, and the memory part (
When redundancy is used in the DRAM section 3, the fuse of the fuse circuit 40 is blown. Further, the circuit 5 that outputs a bit indicating whether or not redundancy is applied corresponding to the RAM position includes a decoder circuit 5a, fuse circuits 50 to 53 degrees NOR gate 5b
Consisting of o ~ 5 b s and an OR gate 5c,
RAM with redundancy (macro) RAM0~R
A? The fuses in the fuse circuits 50 to 53 are blown out depending on the position of the fuse circuit 13. The circuit 6 that outputs a bit indicating a redundant address includes a decoder circuit 5a, fuse circuits 60 to 63 . NOR gate 6be*+6bo+~6bso+6b++ and O
Each RAM is configured with an R gate 6c and has redundancy.
(Macro) RAM0~RA? Address within 13 (AD
The fuses of the fuse circuits 60 to 63 are blown out according to the voltage (O, ADl). Here, decoder circuits 4a, 5a and 68, and OR gates 4c, 5
c and 60 are common, for example,
Decoder circuit 4a (5a.

6a) is a NOR game with a 4-bit signal as input)
4b, 5b, ~5bi+ 6bo. , 6bo+~6bs
. , 6b3I (13 NOR gates).

Specifically, when redundancy as shown in FIG. 2 is applied, first, since the memory section 3 uses redundancy, the fuse of the fuse circuit 40 is blown using a laser or the like. . Further, fuse circuits 50 and 5 corresponding to macro RAM0 and RAl'13 which are performing redundancy
Blow out fuse No. 3. Sooto Macro RA? 10, redundancy is performed for word l, so
Fuse circuit 60 corresponding to the address to which redundancy is applied
In addition, since redundancy is provided for word 3 in macro RAM 3,
Fuse circuit 63 corresponding to the address to which redundancy is applied
fuses 630 and 631 inside. here,
The fuses blown in the fuse circuits 60 and 63 are each macro I? shown in FIG. This corresponds to addresses ADO, A[lI of words O to 3 in AMO to RAM3.

As mentioned above, for chip 1, ■Whether memory section 3 uses redundancy, ■Which macro R7MO-Ji
Redundancy application information, such as whether redundancy is applied to AM3, and which address redundancy is applied to, is set in advance by blowing the fuse (and the decoder circuit 4a (5a, 6a) Read signal SA
By supplying O to SA3, the redundant application information (SO) is read out from the packaged chip.

Specifically, for example, read signals (SAO, SA!, S
When the NOR gate 4b is selected by setting A2°S3) to (1, it i, >, that is, when only the selection signal supplied from the decoder circuit 4a to the NOR gate) 4b becomes low level, the fuse circuit 40 Since the fuse is blown, the input signals of the NOR gate 4b are both low level, the output of the NOR gate 4b is high level, and the output of the OR gate 4c is also high level. On the other hand, the second
Although this is not the case in the figure, if the fuse of the fuse circuit 40 is not blown (if redundancy is not applied to the memory section 3), the fuse circuit 40 is connected to the NOR gate) 4.
Since the signal supplied to the input of b becomes high level, the N
The output of OR gate 4b is at a low level, therefore, OR
The output of game) 4c also becomes low level. Here, the signal output from the decoder circuit 4a selects only the NOR gate 4b as a low level, and the other unselected NOR gates are supplied with a high level signal, and the unselected NOR gates are supplied with a high level signal.
The output signals of the gates are all configured to be at a low level. It goes without saying that the levels of the signals supplied to the decoder circuit 4a and the signals output from the decoder circuit 4a vary depending on the circuit configuration.

In this way, for example, when the read signal supplied to the decoder circuit 4a is (1111), the high level signal S
If O is output, it is known that redundancy is applied to the memory unit 3, and if a low level signal SO is output, it is determined that redundancy is not applied to the memory unit 3.

As mentioned above, when the read signal supplied to the decoder circuit 4a is (1111), if a high level signal SO is output and it is found that redundancy is applied to the memory section 3, which It will be checked whether redundancy is applied to macro RAM0 to RAM3. That is, in order to recognize whether each macro RAM0 to RAM3 is performing redundancy, for example, the decoder circuit 5a (
Read signal (1110) for 4a).

(1011), (1000) and (0101) are supplied to the NOR gate 5b.

A low level signal is supplied to the inputs of 5bx5bt and 5bz to sequentially select them. Specifically, the read signal (0101)
As NOI? When the OR gate 5c is selected, that is, when only the selection signal supplied from the decoder circuit 5a to the NOR gate 5bi becomes low level, the fuse of the fuse circuit 53 is blown, so the input signals of the NOR gate 5b:+ are both becomes a low level, and the NOR gate 5bz
The output signal SO of becomes high level, and the OR gate 5c (
The output of 4c) is also at a high level. Here, for example, if the read signal is (1000), the NOR gate 5bz
The selection signal supplied to the fuse circuit 52 becomes low level, but since the fuse of the fuse circuit 52 is not blown, the output of the NOR gate 5b remains at a low level, and the output signal SO of the OR gate 5c also becomes a low level. . In this way, for example,
The read signals SAO to S83 to be supplied to the decoder circuit 4a are (1110), (1011), (1000
), (0101) and the macro RA where redundancy is performed by detecting the level of the °C output signal SO.
M0-RAM3 can be recognized. When the macro RAM0-RAM3 to which redundancy is applied is recognized in this way, the address to which redundancy is applied is finally confirmed.

For example, if it is recognized that redundancy is being performed in the macro RAM 3, that is, the read signal (0101
) is supplied and the output signal SA becomes high level, in order to recognize the address to which redundancy is applied in the macro RAM 3, the decoder circuit 6a (4a
, 5a), the read signal (0100) , (
0011) to the NOR gate 6bz. ,6b2
A low level signal is supplied to the input of I to sequentially select 0. For example, the read signal is (0100) and the NOR gate 6bs. , that is, from the decoder circuit 6a to the NOR gate 6b. When the selection signal supplied to the select signal becomes low level, the fuse 630 of the fuse circuit 63 is blown, so the NOR gate), 6b,. The input signals of both become low level, and the NOR game) 6bs. The output signal of becomes high level, and as a result, OR game) 6c
The output signal SO of (4c, 5c) also becomes high level. Further, when the read signal is set to (0011) and the NOR gate 6b31 is selected, that is, the decoder circuit 6a
When the selection signal supplied to the NOR gate 6bs+ is set to a low level, the fuse 631 of the fuse circuit 63 is also blown, so the input signals of the NOR gate 6b++ both become low level, and the outputs of the NOR gates 6b and 6bs+ become low level. The signal becomes high level, and the output signal S of OR game) 6c
O is also at a high level. As a result, the address ADO is stored in the macro RAM3.

Since the MDI is (1,1), it can be seen that redundancy is applied to word 3.

In this way, by supplying the read signals SAO to SA3 from the outside to the packaged chip 1, it is possible to determine whether the memory section 3 is using redundancy or not.
Redundancy application information (SO) such as to which macro RAM0 to RAM3 redundancy is applied and (2) to which address redundancy is applied can be read out. Then, using the obtained redundant application information, it becomes possible to recognize the location of an actually defective memory cell and perform an accurate defect analysis of the memory section.

In the above, means for storing redundant application information.

It goes without saying that the format of the readout signal supplied to the decoder circuit, the configuration of the logic gate for reading out the redundant application information, etc. can be modified in various ways. Also,
In the semiconductor integrated circuit device of the present invention, it is not only necessary to add a fuse circuit, a decoder circuit, a logic gate, etc. to the conventional device, but also a terminal for supplying a read signal and a terminal for outputting redundant application information. It is necessary to create a new one. However, for example, gate arrays and the like are becoming larger in size and have more pins, so the addition of new circuits and input/output bins does not pose a problem in practice. Furthermore, the additional circuits and the like may be formed anywhere in the gate array section, even on the periphery of the chip.

〔Effect of the invention〕

As detailed above, according to the present invention, in a semiconductor integrated circuit device having a logic circuit section and a memory section, redundancy application information in the memory section can be obtained even in a packaged state after chip assembly. It is possible to accurately analyze defects in the memory section using redundancy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a semiconductor integrated circuit device according to the present invention; FIG. 2 is a diagram conceptually showing how redundancy is applied in an example of the semiconductor integrated circuit device of the present invention; This figure is a circuit diagram showing a main part of a semiconductor integrated circuit device as an embodiment of the present invention in which the redundancy shown in FIG. 2 is applied. (Explanation of symbols) 1...Chip, 2...Logic circuit section, 3...Memory section, 4...Redundant use output means, 5...Redundant memory position output means, 6...Redundancy Address output means.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which a logic circuit section (2) and a memory section (3) having a redundant function are formed on the same chip (1), wherein the memory section has a redundant function. A redundancy use output means (4) indicating whether or not the redundancy is used; a redundancy memory location output means (5) indicating the memory location where the redundancy is being performed; and a redundancy use output means (5) that outputs the address where the redundancy is being performed. 1. A semiconductor integrated circuit device comprising address output means (6) and configured to output redundant application information in response to a read signal supplied from the outside in a packaged state after chip assembly. 2. The semiconductor integrated circuit device according to claim 1, wherein the logic circuit section is composed of a gate array circuit, and the memory section is composed of a RAM. 3. The redundant use output means, the redundant memory position output means, and the redundant address output means each include a decoder circuit and a fuse circuit, and cut off the corresponding portions of the fuse circuit according to the application of redundancy in the memory section. 2. The semiconductor integrated circuit device according to claim 1, wherein the level of the output signal is defined with respect to the signal supplied from the outside via the decoder circuit.