JPH0327590A - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JPH0327590A JPH0327590A JP16198589A JP16198589A JPH0327590A JP H0327590 A JPH0327590 A JP H0327590A JP 16198589 A JP16198589 A JP 16198589A JP 16198589 A JP16198589 A JP 16198589A JP H0327590 A JPH0327590 A JP H0327590A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- opening
- conductor layer
- conductor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 31
- 239000004020 conductor Substances 0.000 claims abstract description 50
- 229910000510 noble metal Inorganic materials 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 238000007650 screen-printing Methods 0.000 abstract description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000007639 printing Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101100434911 Mus musculus Angpt1 gene Proteins 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＬＳＩペアチップ、受動素子等の電子部品が
配設されるセラミック回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ceramic circuit board on which electronic components such as LSI pair chips and passive elements are arranged.
［従来の技術］
近時、電子回路が形成される回路基板にあっては、抗折
強度、熱拡散率さらにアナログ／デジタル混戊回路にお
ける高い周波数およびパルス伝送特性に係る誘電率等の
優位性の観点からセラミック回路基板が多用される。[Prior Art] Recently, circuit boards on which electronic circuits are formed have advantages such as bending strength, thermal diffusivity, and dielectric constant related to high frequency and pulse transmission characteristics in analog/digital mixed circuits. Ceramic circuit boards are often used from this point of view.
この種のセラミック回路基板に係る好例として特公昭６
３−４６５９５号公報のセラミック多層配線基板の製造
法を挙げることが出来る。As a good example of this type of ceramic circuit board,
The method for manufacturing a ceramic multilayer wiring board disclosed in Japanese Patent No. 3-46595 can be mentioned.
当該セラミック多層配線基板の製造法では、先ず、セラ
ミック基体上にＷまたはＭｏ等の高融点金属を主戊分と
する第１の導体層を形成し、さらに前記第１導体層の一
部を開口した絶縁層をスクリーン印刷で形戒する。また
開口部に酸化防止および濡れ性を考慮してニッケルメッ
キを施し、さらにニッケルメッキ上にＡｇおよびＡｕ等
の貴金属層を溶解して形戊する。次いで、ペアチップの
ＩＣあるいはＳＡＷ，受動素子等をリフロ半田法等で接
続するために前記絶縁層上に掛かりその面積が開口部の
直径より大なる値の厚膜の第２の導体層を印刷する。続
いて酸化雰囲気で焼或を行う。このようにしてセラミッ
ク回路基板が完威される。In the method for manufacturing the ceramic multilayer wiring board, first, a first conductor layer mainly made of a high melting point metal such as W or Mo is formed on a ceramic substrate, and a part of the first conductor layer is opened. The insulating layer is printed using screen printing. Further, the openings are plated with nickel in consideration of oxidation prevention and wettability, and a noble metal layer such as Ag and Au is melted and formed on the nickel plating. Next, a thick second conductor layer is printed on the insulating layer and has an area larger than the diameter of the opening in order to connect the ICs, SAWs, passive elements, etc. of the paired chips by reflow soldering or the like. . Subsequently, annealing is performed in an oxidizing atmosphere. In this way, the ceramic circuit board is perfected.
［発明が解決しようとする課題］
然しなから、上記の従来の技術に係るセラミック回路基
板においては、焼或後の取扱等で生起し易いクラックを
阻止すべく、すなわち、所望の強度を得られるようセラ
ミック基体表面から絶縁層の表面までの厚さが、例えば
、４０乃至７０μｍに形成されている。そのため開口部
が比較的深いものとなり、以降における前記貴金属層お
よび絶縁層の形成のための印刷の作業に困難を伴う不都
合を露呈する。[Problems to be Solved by the Invention] However, in the ceramic circuit board according to the above-mentioned conventional technology, in order to prevent cracks that are likely to occur due to handling after firing, it is difficult to obtain the desired strength. The thickness from the surface of the ceramic substrate to the surface of the insulating layer is, for example, 40 to 70 μm. Therefore, the opening becomes relatively deep, which presents an inconvenience in that the subsequent printing operation for forming the noble metal layer and the insulating layer is difficult.
本発明は係る点に鑑みてなされ、開口部のレベリングを
行い、これにより厚膜導体パターンを形成するためのス
クリーン印刷工程の作業が容易になるセラミック回路基
板を提供することを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a ceramic circuit board in which openings are leveled, thereby facilitating a screen printing process for forming a thick film conductor pattern.
［課題を解決するための手段］
前記の課題を解決するために本発明は、セラミック基体
と、
当該セラミック基体上に形成される第１の導体層と、
当該第１導体層上の所定部分に開口部を設けて形成され
る絶縁層と、
前記開口部に形成される第２の導体層と、当該第２導体
層上に形成されるメッキ層と、当該メッキ層上に形成さ
れる貴金属層と、当該貴金属層上に形成される第３の導
体層と、を具備し、
前記第２導体層の上面は前記絶縁層と少なくとも同一表
面か、それ以下に形成されることをを特徴とする。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention includes: a ceramic substrate; a first conductor layer formed on the ceramic substrate; an insulating layer formed with an opening, a second conductor layer formed in the opening, a plating layer formed on the second conductor layer, and a noble metal layer formed on the plating layer. and a third conductive layer formed on the noble metal layer, wherein the upper surface of the second conductive layer is at least the same surface as the insulating layer or below. .
［作用コ
本発明に係るセラミック回路基板においては、セラミッ
ク基体上に第１の導体層を形成した後、所定部分に開口
部を設けて第１導体層上に絶縁層を形成する。次に、前
記開口部に第２の導体層を形戊し、さらに第３の導体層
上にメッキ層を形成し、次に、前記メッキ層上に金およ
び白金からなる貴金属層を形成する。[Function] In the ceramic circuit board according to the present invention, after the first conductor layer is formed on the ceramic substrate, an opening is provided in a predetermined portion and an insulating layer is formed on the first conductor layer. Next, a second conductor layer is formed in the opening, a plating layer is formed on the third conductor layer, and then a noble metal layer made of gold and platinum is formed on the plating layer.
このようにして、開口部のレベリングが比較的容易に行
われる。In this way, leveling of the openings is relatively easy.
［実施例］
次に、本発明に係るセラミック回路基板の実施例を添付
の図面を参照して以下詳細に説明する。[Example] Next, an example of the ceramic circuit board according to the present invention will be described in detail below with reference to the accompanying drawings.
第１図にセラミック回路基板の断面を示し、第２図にそ
の作製に係る工程を示す。FIG. 1 shows a cross section of the ceramic circuit board, and FIG. 2 shows the steps involved in its production.
第１図に示される例は、グリーンシ一トＧと、当該グリ
ーンシ一トＧ上に形成され、Ｗ，Ｍｏの高融点金属から
なる第１の導体層１２と、当該第１導体層１２の一部に
形成される開口部ｐを有して前記第１導体層ｌ２上に形
成された絶縁層１８ａ，１８ｂを含む。また前記開口部
ｐをレベリングするために施される第２の導体層１６で
あるＭＯを主或分とする下層部１６ａと、当該第２導体
層１６のＷを主或分とする上層部１６ｂと、さらに、前
記第２導体層ｌ６の上層部１６ｂ上に形成されるニッケ
ルメッキ層２２とを有している。さらにニッケルメッキ
層２２に形成され、Ａｕ１Ａｇ系の貴金属層２４と、当
該貴金属層２４および前記絶縁層１８ｂ上に形成される
Ａｇ−Ｐｄ，ＡｇＰｔ系の第３の導体層２６とで構或さ
れている。The example shown in FIG. 1 includes a green sheet G, a first conductor layer 12 formed on the green sheet G and made of a high melting point metal such as W or Mo, and a The first conductor layer 18 includes insulating layers 18a and 18b formed on the first conductor layer l2 and having an opening p formed in a portion of the first conductor layer l2. Further, a lower layer portion 16a mainly composed of MO, which is the second conductor layer 16 applied to level the opening p, and an upper layer portion 16b mainly composed of W of the second conductor layer 16. and a nickel plating layer 22 formed on the upper layer portion 16b of the second conductor layer l6. Further, it is formed on the nickel plating layer 22 and is composed of an Au1Ag based noble metal layer 24, and a third conductive layer 26 of Ag-Pd, AgPt based, which is formed on the noble metal layer 24 and the insulating layer 18b. There is.
次いで、上記のセラミック回路基板の製造方法の一例を
説明する。Next, an example of a method for manufacturing the above ceramic circuit board will be explained.
先ず、工程（ａ）において、未焼結の基体であるグリー
ンシ一トＧをドクタブレード法を用いて均一な厚さ、例
えば、５００μｍに形成し、この後、金型による打ち抜
きにおいて所定の寸法に切断する。First, in step (a), a green sheet G, which is an unsintered substrate, is formed into a uniform thickness, for example, 500 μm, using a doctor blade method, and then punched with a die to a predetermined size. Cut into.
次に、工程（ｂ）において、グリーンシー１− Ｇ上に
第１導体層１２を形成する。この場合、ＷまたはＭｏの
メタライズ或分に印刷助剤を加えたメタライズペースト
をスクリーン印刷を用いて行う。Next, in step (b), the first conductor layer 12 is formed on the green sea 1-G. In this case, a metallization paste prepared by adding a printing aid to a certain amount of W or Mo metallization is performed using screen printing.
次に、王程（Ｃ）において、前記第１導体層ｌ２の一部
分上に開口部ｐが形成された絶縁層１８ａをグリーンシ
一トＧと同一組戊をもってスグリーン印刷により形成す
る。Next, in step (C), an insulating layer 18a in which an opening p is formed on a portion of the first conductor layer l2 is formed by green printing with the same pattern as the green sheet G.
次に、工程（ｄ）において、第１導体層１２の開口部ｐ
にスクリーン印刷により第２導体層１６を形戊する。こ
の場合、予め、グリーンシ一トＧと熱収縮率が近似した
Ｍｏのメクライズ戊分に印刷助剤を加えたメタライズペ
ースとを用いて第２導体層１６の下層部１６ａを形戊す
る。Next, in step (d), the opening p of the first conductor layer 12 is
Then, the second conductor layer 16 is formed by screen printing. In this case, the lower layer portion 16a of the second conductor layer 16 is formed in advance using a green sheet G and a metallization paste prepared by adding a printing aid to a metallization paste of Mo having a heat shrinkage rate similar to that of the green sheet G.
工程（ｅ）において、前記絶縁層１８ａ上に開口部ｐと
同一の開口部を画或するように絶縁層１８ｂをグリーン
シ一トＧと同一戊分をもって、スクリーン印刷により形
成する。In step (e), an insulating layer 18b is formed on the insulating layer 18a by screen printing with the same length as the green sheet G so as to form an opening that is the same as the opening p.
工程（ｆ）において、ＷまたはＭＯのメタライズ或分に
印刷助剤を加えたメクライズペースとを用いて開口部ｐ
に形成された第２導体層１６の上層部１６ｂを形戊する
。In step (f), the opening p is formed using a metallization paste of W or MO and a printing aid added thereto.
The upper layer portion 16b of the second conductor layer 16 formed in the second conductive layer 16 is then shaped.
さらに工程（ｇ）において、第１導体層１２と第２導体
層１６と絶縁層１８ａ，１８ｂとを形成したグリーンシ
一トＧを還元雰囲気中で焼結する。Further, in step (g), the green sheet G on which the first conductor layer 12, the second conductor layer 16, and the insulating layers 18a and 18b are formed is sintered in a reducing atmosphere.
次いで工程（５）において、前記第２導体層１６上に硼
素系の無電解メッキ法によりニッケルメッキ２２を厚さ
３μｍで形成する。Next, in step (5), nickel plating 22 is formed to a thickness of 3 μm on the second conductor layer 16 by a boron-based electroless plating method.
次に、工程（ｉ）において還元雰囲気中で９００℃、約
３０分の熱処理を行う。Next, in step (i), heat treatment is performed at 900° C. for about 30 minutes in a reducing atmosphere.
さらに、工程（Ｊ）において、ＡｕおよびＡｇの貴金属
組威のペーストをニッケルメッキ２２上にスクリーン印
刷等により３０μｍの厚さをもって、貴金属層２４を形
成した後、非酸化雰囲気中９６０〜１１００℃で、Ａｕ
およびＡｇの組或に合わせて、例えば、約３０分間熱処
理を行い貴金属を溶解する。Furthermore, in step (J), after forming a noble metal layer 24 with a thickness of 30 μm on the nickel plating 22 by screen printing a paste of noble metal composition of Au and Ag, the paste is heated at 960 to 1100°C in a non-oxidizing atmosphere. , Au
Heat treatment is performed for about 30 minutes depending on the combination of silver and silver, for example, to melt the noble metal.
工程（ｋ）において、厚膜導体ペーストであるＡｇ−Ｐ
ｔ系ペーストあるいはＡｇ−Ｐｄ系ペーストをスクリー
ン印刷において前記絶縁層上に掛かり開口部ｐの直径よ
り大なる表面積である第３の導体層２６を形成する。In step (k), thick film conductor paste Ag-P
A third conductive layer 26 is formed by screen printing a t-based paste or an Ag--Pd based paste over the insulating layer and having a surface area larger than the diameter of the opening p.
工程（１）において、前記Ａｇ−Ｐｔ系ペーストが形成
されｔこ実施例にあっては、酸化雰囲気中８５０℃で１
０分間焼戊する。また、前記ＡｇＰｄ系ペーストが形成
された実施例にあっては酸化雰囲気中７５０℃で１０分
間焼或する。In the step (1), the Ag-Pt paste is formed.
Burn for 0 minutes. Further, in the embodiment in which the AgPd-based paste is formed, it is baked at 750° C. for 10 minutes in an oxidizing atmosphere.
以上のようなセラミック回路基板の製造方法においては
貴金属層および第３導体層の形成のための開口部のレベ
リングが比較的容易に行われる。In the method for manufacturing a ceramic circuit board as described above, leveling of the opening for forming the noble metal layer and the third conductor layer is relatively easily performed.
なお、当該実施例ではセラミック回路基板どしているが
、斯かるセラミック回路基板を積層して多層のセラミッ
ク回路基板を形戊することも可能である。Although a ceramic circuit board is used in this embodiment, it is also possible to form a multilayer ceramic circuit board by laminating such ceramic circuit boards.
［発明の効果］
以上のように、本発明のセラミック回路基板によれば、
セラミック基体と、当該セラミック基体上に形成される
第１の導体層と、当該第１導体層上の所定部分に開口部
を設けて形成される絶縁層と、前記開口部に形成される
第２の導体層と、当該第２導体層上に形成されるメッキ
層と、当該メッキ層上に形成される貴金属層と、当該貴
金属層上に形成される第３の導体層と、を具備し、前記
第２導体層の上面は前記絶縁層と少なくとも同一表面か
、それ以下に形戊され、これにより前記開口部のレベリ
ングが容易に行われて貴金属層および第３導体層を形成
するためのスクリーン印刷工程の作業が容易になる効果
を奏する。[Effects of the Invention] As described above, according to the ceramic circuit board of the present invention,
a ceramic base, a first conductor layer formed on the ceramic base, an insulating layer formed by providing an opening in a predetermined portion on the first conductor layer, and a second conductor layer formed in the opening. a conductor layer, a plating layer formed on the second conductor layer, a noble metal layer formed on the plating layer, and a third conductor layer formed on the noble metal layer, The upper surface of the second conductor layer is formed to be at least flush with or below the surface of the insulating layer, so that the opening can be easily leveled to form a screen for forming the noble metal layer and the third conductor layer. This has the effect of making the printing process easier.
第ｔ図は本発明に係るセラミック回路基板の９
１０
構或を示す断面図、
第２図は本発明に係るセラミック回路基板の製造方法を
説明するための概略工程のフローチャートである。
Ｇ・・・グリーンシ一ト
１６・・・第２導体層
２２・・・ニンケルメッキ層
２６・・・第３導体層
１２・・・第１導体層
１８ａ，１８ａ・・・絶縁層
２４・・・貫金属層
１
１FIG. t is a cross-sectional view showing a 910 structure of a ceramic circuit board according to the present invention, and FIG. 2 is a flowchart of a schematic process for explaining a method for manufacturing a ceramic circuit board according to the present invention. G...Green sheet 16...Second conductor layer 22...Ninkel plating layer 26...Third conductor layer 12...First conductor layer 18a, 18a...Insulating layer 24... Through metal layer 1 1
Claims (2)
る絶縁層と、 前記開口部に形成される第２の導体層と、 当該第２導体層上に形成されるメッキ層と、当該メッキ
層上に形成される貴金属層と、 当該貴金属層上に形成される第３の導体層と、を具備し
、 前記第２導体層の上面は前記絶縁層と少なくとも同一表
面か、それ以下に形成されることをを特徴とするセラミ
ック回路基板。(1) a ceramic base; a first conductor layer formed on the ceramic base; an insulating layer formed by providing an opening in a predetermined portion on the first conductor layer; and an insulating layer formed in the opening. a second conductor layer formed on the second conductor layer, a plating layer formed on the plating layer, and a third conductor layer formed on the noble metal layer. A ceramic circuit board, characterized in that the upper surface of the second conductive layer is formed at least on the same surface as the insulating layer or below the surface.
２導体層のメッキ層側の上層部はタングステン層であり
、一方、下層部はモリブデン層であることを特徴とする
セラミック回路基板。(2) The ceramic circuit board according to claim 1, wherein the upper layer on the plating layer side of the second conductor layer is a tungsten layer, while the lower layer is a molybdenum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16198589A JPH0327590A (en) | 1989-06-23 | 1989-06-23 | Ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16198589A JPH0327590A (en) | 1989-06-23 | 1989-06-23 | Ceramic circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0327590A true JPH0327590A (en) | 1991-02-05 |
Family
ID=15745844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16198589A Pending JPH0327590A (en) | 1989-06-23 | 1989-06-23 | Ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0327590A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328751A (en) * | 1991-07-12 | 1994-07-12 | Kabushiki Kaisha Toshiba | Ceramic circuit board with a curved lead terminal |
| KR100504048B1 (en) * | 1998-09-02 | 2005-09-26 | 삼성전자주식회사 | Refrigerator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54764A (en) * | 1977-06-02 | 1979-01-06 | Tokyo Shibaura Electric Co | Wiring board |
| JPS59171195A (en) * | 1983-03-18 | 1984-09-27 | 日本碍子株式会社 | Method of producing ceramic multilayer circuit board |
-
1989
- 1989-06-23 JP JP16198589A patent/JPH0327590A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54764A (en) * | 1977-06-02 | 1979-01-06 | Tokyo Shibaura Electric Co | Wiring board |
| JPS59171195A (en) * | 1983-03-18 | 1984-09-27 | 日本碍子株式会社 | Method of producing ceramic multilayer circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328751A (en) * | 1991-07-12 | 1994-07-12 | Kabushiki Kaisha Toshiba | Ceramic circuit board with a curved lead terminal |
| KR100504048B1 (en) * | 1998-09-02 | 2005-09-26 | 삼성전자주식회사 | Refrigerator |
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