JPH03271860A - Shared memory multiprocessor system - Google Patents

Abstract

PURPOSE:To perform various control by selectively outputting not only a shared memory but also contents of a second register by a selector to access the local memory of an arbitrary processor unit at the time of access from the IO device main body part of an input/output unit. CONSTITUTION:A bus interface 42a of an input/output unit 42 is provided with a first register 44 where the identifier of a shared memory 41 is stored, a second register 45 where identifiers of plural processor units 431, 432,... are stored, and a selector 46 which selects registers 44 and 45. At the time of access from the IO device main body part of an input/output unit 42, not only the shared memory 41 but also contents of the second register 45 are selectively outputted by the selector 46 in accordance with the IO access signal to access even the local memory of arbitrary one of plural processor units 431, 432,.... Thus, DMA transfer is possible and various control is performed.

Description

[Detailed Description of the Invention] [Summary] A bus interface, especially in a common memory multiprocessor system, used in a control unit of an electronic computer or an electronic exchange.
- With regard to the bus circuit of the input/output unit, the purpose of the bus circuit of the input/output unit is to enable direct memory access transfer not only to the common memory but also to the local memory area in other processor units and to perform a wide variety of controls. In addition to the first register that stores the common memory identifier, the interface is provided with a second register that stores the identifiers of multiple processor units, and a selector that selects these two registers. Output unit IO
When accessing from the main body of the device, in addition to the common memory, a selector selects and outputs the contents of the second register in response to an IO access signal, and accesses the local memory of any processor unit among multiple processor units. The configuration is such that it can be done.

[Industrial application field]

The present invention relates to a bus interface circuit used in a control unit of an electronic computer or an electronic exchange, particularly in a common memory multiprocessor system.

In recent years, the so-called multiprocessor system, in which multiple processors are used to collectively operate a system, has been increasingly used as a means of speeding up the control units of computers and switching equipment. Among these, the common memory multiprocessor method, in which a common memory is used for multiple processors, is known as a promising method in terms of feasibility. In this case, in order to cope with control formats that are expected to become more and more complex in the future, it is necessary to enable a wide variety of controls using an input/output unit that is common to each processor on the external bus. There is.

[Conventional technology]

FIG. 6 shows a block diagram of a conventional example. In the figure, a common memory (CM) 1 and each processor unit (P
LJ#1~n) 21~23 and input/output unit (IOU
) 3 is connected to an external system bus 4. Common memory 1. The processor units 21 to 23 each have an individual identifier (ID>) as a bus interface circuit (INF) ia,
2+a to 23a, and it is determined by looking at the identifier (ID) on the bus 4 whether or not the access is for the user. FIG. 7 shows a memory area image visible from the software. In this example, 172 of the memory spaces are common memory (CM) spaces, and the rest are each processor units 21 to 2.
3 local memory (LM) space. In order to realize such memory area access, the bus interface circuit (INF>la, 2+) between 8 and 238 contains a boundary address indicating where the local memory (LM) area starts and an identifier for common memory 1 ( ID)
is set, and as shown in Figure 8, internal bus 2+b
When the address on 2'-2'3b is accessed by the common memory area MC, the external bus 4 is accessed using the identifier of the common memory 1 set in the common memory TD register 5 of the bus interface circuits 21-22. By doing so, the local memory area ML can be used independently only within each processor unit 21-23. In other words, each processor unit 21-23 cannot access the local memory area ML of other processor units. In this case, in FIG. 8, the external bus interface unit 6 is enabled when the comparator 8 detects that the internal bus address B is smaller than the address A preset in the boundary register 7 (A>8). done, A〈B
In this case, it is regarded as an access to the local memory area ML, and the external bus interface section 6 is not enabled.

On the other hand, an input/output unit (IOLI) 3 common to each processor unit 21 to 23 provided on the external bus 4
The bus interface circuit 3a also has the configuration shown in FIG. 8, and can access the common memory area Mc, but cannot access the local memory areas M of each of the processor units 21-23.

[Problem to be solved by the invention]

In the above conventional example, although it is possible to perform direct memory access (DMA) transfer of the common memory area MC, the O-cal memory area ML of each processor unit 21 to 23 cannot be accessed. DMA to local memory area ML by 3b
There was a problem in that transfer was no longer possible and complex control could not be performed.

The present invention provides a common memory multiprocessor system that allows input/output units to perform DMA transfer not only to the common memory but also to local memory areas in other processor units to perform a wide variety of controls. purpose.

[Means to solve the problem]

FIG. 1 shows a diagram of the principle of the present invention. In the figure, 40 is an external bus, 41 is a common memory, 42 is an input/output unit, and 43+
, 432, . . . are multiple processor units,
The present invention provides a common memory 41. Input/output unit 42.11
This is applied to a common memory multi-processor system in which several processor units 431, 432, . .

Therefore, in the present invention, in addition to the first register 44 storing the identifier of the common memory 41, the bus interface 42a of the input/output unit 42 newly stores the identifiers of the plurality of processor units 43+, 432, . A second register 45. and the first register 44 and the second register 44
A selector 46 for selecting the register 45 is provided. As a result, when accessing from the IO device main body of the input/output unit 42, in response to the 0 access signal, in addition to the common memory 41, the selector 46 selectively outputs the contents of the second register 45 and outputs the contents of the second register 45. The local memory of any of the processor units 43+, 432, . . . can also be accessed.

[Effect]

When accessing the common memory 41, internal bus address B
is smaller than the register value A of the boundary register 47 (A
>B), this is detected by the comparator 48, and the bus access control unit 50 is enabled by the output of the OR gate 49. At this time, the IO access signal (IOA) is set to f'LJ, the selector 46 selects and outputs the contents of the first register 44, and an identifier for accessing the common memory 41 is output on the external bus 40. .

On the other hand, processor units 43+, 432,...
When accessing, internal bus address B is register value A.
(B>A>, and no signal is output from the comparator 48. At this time, the IO access signal (IO
Since A) is set to rHJ, the bus access control unit 50 is enabled via the OR gate 49, and the selector 46 selectively outputs the contents of the second register 45 by rHJ of the IO access signal (IOA) and outputs it to the external device. An identifier for accessing the local memory of any of the processor units 43+, 432, . . . is output on the bus 40, thereby making it possible to access the local memory.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the present invention, in which the same components as in FIG. 6 are given the same numbers. In FIG. 2, IO is an input/output unit (IO-U), which is composed of an IO device main body section IOa, an internal bus interface section IOb, and an external bus interface section IOC. FIG. 3 shows a detailed block diagram of the internal bus interface section IOb, and FIG. 4 shows a detailed block diagram of the external bus interface section IOc. In FIG. 2, reference numeral 11 denotes a bus arbiter, which performs arbitration, such as determining the priority order for the external bus 4, between each of the processor units 21 to 23 and the input/output unit IO. In the present invention, when there is an access from the IO device main body section IOa (IO access signal 10AC>rLJ access signal from the internal bus interface section IOb (IOA
), and the selector 21 (FIG. 4) provided in the external bus interface section IOc outputs the register 2 holding the identifier (ID) of each processor unit 21 to 23.
By selectively outputting the contents of 2,
When accessing from Oa, not only the common memory 1 but also the local memory ML in other processor units 21 to 23 is used.
It also allows access to.

Next, the operation of the present invention will be explained in conjunction with the timing chart shown in FIG.

Request signal (REQ) by IO device main unit IOa
When becomes rLJ, the address/data on the internal bus (however, the data is omitted in the figure) and the IO access signal (IOAC) are sampled via the gate 31° flip 70 knob 32, and are sent from the internal bus interface section IOb. An address (ADRi) and an access signal (IOA) are output and supplied to the external bus interface section IOc. In this case, when accessing the common memory area Mc, the IO access signal (IOAC) is set to rHJ, and the access signal (IOA) is set to I'LJ.

Here, the register value A of the boundary register 33 is set in advance, and the comparator 34 compares this register value with the address <ADRi) of the flip-flop 32, and determines whether the access to the common memory area MC is For example, the address (ADRi)B is smaller than the register value A of the boundary register 33, (A>B) the output of the comparator 34 t y r)-1", and the output of the OR gate 35 is r
HJ, and the request signal (RQ) to the external bus interface IOC becomes rHJ. When the request signal (RQ) becomes rHJ, the bus request signal (BRQ) is output via the gate circuit 23 of the external bus interface section IOc.
) becomes rLJ and is supplied to the bus arbiter 11. When the bus request permission signal (BACK) is returned from the bus arbiter 11, the bus start signal (BS) becomes "Yes" at the external bus interface IOC. In this case, since the access signal (IOA) is f'LJ, the selector 21 selects the common memory ID register 24, and thereby,
The contents of the register 24, that is, the identifier (ID) for accessing the common memory 1, are selected, and the bus start signal (
The signal is output via the gate 25 which is set to the bus state at 88). At this time, the internal bus interface section IOb
The address ADRi output from the bus start signal (
The signal is output (ADRo) via the gate 26 which is in the bus state at BS).

On the other hand, when accessing the local memory area Mi, the ■0 access signal (IOAC) is set to rLJ, and the access signal (IOA) is set to rHJ. In this case, since the access is to the local memory area Mi, the address (
ADRi)B is larger than the register value A of the boundary register 33 (B>A), and the output of the comparator 34 becomes rLJ, but since the access signal (IOA) is rHJ, the output of the OR gate 35 becomes rHJ, and the request signal ( R
Q) becomes rHJ. Request signal (RQ) is rHJ
Then, the bus request signal (BRQ) becomes rLJ, and when the bus request permission signal (BACK) is returned from the bus arbiter 11, the bus start signal (BS> becomes "L". In this case, the access signal (IOA) becomes rHJ. Therefore, the selector 21 selects the processor unit identifier register 22. As a result, the contents of the register 22, that is, the identifiers (ID) for accessing each processor unit 21 to 23 are selected, and the bus start signal (BS) is selected. At this time, the address ADR+ output from the internal bus interface section IOb is also output via the gate 25 which is set to the bus state by the bus start signal (BS). is output.

That is, in the case of access by the input/output unit IO, it is possible to access not only the common memory area MC but also the 0-cal memory area ML of each of the arbitrary processor units 21 to 23. A variety of i-controls can be performed.

The processor unit (21-23) selected by the identifier (IO) sets the ready signal (RDY) to rLJ to notify that it has received the signal normally, and thereby the external bus cycle for the external bus 4 of the input/output unit IO ends. Furthermore, the ready signal (RDY) in the external path interface section IOc is converted into RDYI by the gate circuit 27, and is sent to the internal bus interface section IOb, and is then sent to the gate circuit 3.
At step 6, a ready signal (RE
ADY), thereby completing the internal bus cycle for the internal bus of the input/output unit IO.

〔Effect of the invention〕

As explained above, according to the present invention, the bus interface of the input/output unit includes the processor unit identifier register (second register) and the IO access signal (IOA).
By providing a selector that selects and outputs the contents of the second register, when accessing from the main body of the IO device, it is possible to access not only the common memory area but also the local memory area within the processor unit. A greater variety of controls can be performed than in the example.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a specific configuration diagram of the internal bus interface section, and Fig. 4 is a specific configuration diagram of the external bus interface section. 5 is an operation timing chart of the present invention, FIG. 6 is a block diagram of a conventional example, FIG. 7 is a memory area image diagram seen from software, and FIG. 8 is a configuration diagram of a conventional bus interface circuit. In the figure, 1 is a common memory, 21 to 23.43+, 432,... are processor units, 2+a, 22a,...42a are bus interface circuits, 4.40 is an external bus, IO. 42 is an input/output unit, IOa is an IO device main body, IOb is an internal bus interface, IOG is an external bus interface, 11 is a bus arbiter, 21.46 is a selector, 22.45 is a processor unit identifier register (second
23.27.36 is a gate circuit, 24.44 is a common memory identifier register (first register), 25.26 is a gate, 32 is a flip-flop, 33.42 is a boundary register, 34.48 is a comparator , 35.49 indicates the or gate.

Claims (1)

[Claims] An external bus (40), a common memory (41), an input/output unit (42), and a plurality of processor units (43_1, 4
3_2,...) are connected, and the common memory (41),
Input/output unit (42), multiple processor units (
43_1, 43_2, . . . ) each have an individual identifier, and the input/output unit 43_1, 43_2, . . . The common memory (41) is connected to the bus interface (42a) of (42).
In addition to the first register (44) storing the identifier of
The above multiple processor units (43_1, 43
A second register (45) for storing an identifier of __2,...) and a selector (46) for selecting the first register (44) and the second register (45) are provided. When the input/output unit (42) is accessed from the IO device main body, in addition to the common memory (41), the selector (46) selects the second register (45) in response to the IO access signal. ) is selected and outputted to the plurality of processor units (43_1, 43_2, . . . ).
A common memory multiprocessor system characterized by being able to access the local memory of any processor unit in ).