JPH03270069A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To ensure an alignment margin without inhibiting improvement in the degree of integration as much as possible by forming the side edge, in the direction of a line connecting the centers of both contact sections in an active region, not in parallel with a line connecting the centers and equalizing alignment allowance to the active region in the lower section of a capacitor contact for any side of the active region. CONSTITUTION:Side edges L1, L2 in the direction along a line L tying each center of a bit-line contact section CH1 and a capacitor contact section CH2 in an active region AA are formed in a non-parallel shape to the line L. The active region AA is inclined in the bit-line direction (the horizontal direction), and the capacitor contact section CH2 has an extension section AA1 in the symmetric direction to the bit-line contact section CH1 while using a line in the orthogonal direction (the vertical direction) to a bit-line as an axis. CH3 represents a capacitor contact section to the shared active region AA of an adjacent cell, and the same extension section AA2 is also formed to the section. In the constitution, all of allowance to the active-region side edges L1-L4 of the capacitor contact section CH2 can be equalized.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding the pattern shape of a semiconductor memory device, particularly a DRAM cell, an active region shape that can secure an alignment margin without hindering high integration as much as possible is provided. It has a MOS transistor and a capacitor, and one of the source and drain regions of the MOS transistor is connected to a bit line.
The other side is in contact with the capacitor, and the bit line is a stacked capacitor type DPI cell wired on the MOS transistor via an insulating film. The contact area of the capacitor is an integral part that connects the contact parts of the capacitor and is inclined with respect to the bit line. In a semiconductor memory device having the cell to which an extended portion of the active region is added, side edges of the active region in the direction of a line connecting the centers of both contact portions are made non-parallel to the line connecting the centers, The positioning margin of the capacitor contact portion with respect to the active region is configured to be the same value with respect to both sides of the active region.

[Industrial application field]

The present invention relates to a pattern shape of a semiconductor memory device, particularly a DRAM cell.

In recent years, as DRAMs have become more highly integrated, memory cell structures are required to be compact, have a storage capacity of a required value, and have excellent electrical performance such as charge retention.

Various types of memory cells are known, such as a trench capacitor type and a stacked capacitor type. The present invention belongs to the stacked capacitor type, but since the shape of the active region is particularly related to the leakage current of the junction, a device is required to suppress the leakage of the accumulated charges. Therefore, it is necessary to carefully select manufacturing conditions for memory cells and to devise cell patterns.

[Conventional technology]

FIG. 6 shows a typical planar configuration and cross section of a conventional stacked capacitor cell. In this figure, BL (the subscript i is used to distinguish one from the other and will be omitted as appropriate).

) is the bit line, WL is the word line, CE is the capacitor electrode, CP is the cell plate, D is the train region, S
is the source area. Most DRAM memory cells are of the one-transistor, one-capacitor type, which is also the case in this example.
, WLi, and S constitute a QS FET, and CE CP constitutes a capacitor. CH, is a contact hole between BL and D, and CH, is a contact hole between CE and S. FO is a field oxide film, and a region of the semiconductor substrate SUB surrounded by this is an active region AA, and source/drain regions D/S are formed in this active region. (b) in this figure is line A in (a)
- It is a cross section of A' part.

Conventional stacked capacitor type DRAM cells have a structure in which a capacitor is stacked on a MOS transistor and a bit line is wired to this, so the shape of the active area AA of the MOS transistor is composed of lines parallel to the direction of the bit line. It is a rectangular shape (elongated in the bit line direction). In this case, the bit line is wired from a contact portion to the cell, then on the word line via the interlayer insulating film, and then on the capacitor.

Figure 7 is also of the same type (Japanese Patent Publication No. 6O-2784), and like parts are given the same reference numerals throughout the figures. In this memory cell, the electrodes CE and CP of the capacitor of the memory cell at the intersection of WLi and BLi are formed to also straddle the adjacent word line WLj, even if the capacitor capacitance is made as large as possible.

However, in this structure, since the bit line is wired above the capacitor, the wiring must be formed in a large stepped portion from the contact portion to the source/drain of the transistor to the top of the capacitor. For this reason, disconnections occur frequently and high manufacturing yields cannot be obtained.

Therefore, the positional relationship between the bit line and the capacitor is as follows.
As shown in the figure, a planar layout was considered in which no bit lines were placed directly above or below the capacitor. This eighth
In the figure, the position of the capacitor of a conventional stacked capacitor cell is shifted so that it is not directly under the bit line, but is placed between BLi and BLj in a partial view of the bit line. Conversely, valleys are likely to be formed in the gaps between capacitors due to the uneven shape of the surface, and the idea is to fill these valleys with bit lines. B-B in Figure 8
An example of the cross-sectional structure of the ' section is shown in FIG.

In (a), the bit line BL is inserted into the valley formed by each capacitor CE, etc., and the level difference at the bit line contact CH is alleviated. In (c), the bit line BL is formed before the capacitor is formed, and the capacitor CE, etc. is stacked on the bit line. This (b) is JP-A-1-137
666, together with drawings such as FIG. 1O.

Although the planar pattern in FIG. 9(b) is the same as in FIG. 8, the idea is different from that in FIG. 9(a), in which the bit line BL is formed via an interlayer insulating film after forming the MOS t-transistor.
The capacitor is arranged so as to be placed on the bit line, and the connection between the capacitor and the MO3I-transistor is made at the gap between the bit lines. This eliminates the need for bit lines to run over large steps created by capacitors, eliminating problems such as disconnections. The drawback is a slight increase in bit line capacitance, but this can be addressed by design.

In either case, the transistor (MOS) is its source,
One side of the drain is on the bit line, and the other side is on the gap in the bit line, so the center line connecting the center of the contact part of the source electrode and the center of the drain contact is not parallel to the bit line, and the other side is on the bit line. They are not parallel to each other, but intersect diagonally.

When the word line or bit line and the center line connecting the source and drain intersect obliquely, the shape of the active region of the transistor is simply a shape in which the source and drain are connected by a constant width W. It is.

(Problem to be Solved by the Invention) However, in reality, the contact portion CH2 inside the storage capacitor requires a redundant area in order to obtain a margin for alignment between the active region and the contact hole. The reason for this is that the tip portion of the active region is prone to collapse due to process reasons such as selective oxidation, and to prevent this, the tip portion is extended redundantly in advance. In a DRAM in which memory cells must be arranged at high density, such redundant areas must be devised so as not to impede high integration.

Further, the alignment margin needs to be the same in the positive direction and the negative direction from the reference (zero alignment error) in any direction. This is because the occurrence of alignment errors is a random phenomenon, and as a general rule, there is no deviation in either the positive or negative direction with respect to the reference.

The present invention has been made with these points in mind, and it is an object of the present invention to provide an active region shape that can secure alignment margins without hindering high integration as much as possible. be.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the active area AA is
A side edge L2 in a direction along a line connecting the centers of the contact portion CHI with the bit line and the contact portion CH with the capacitor is made non-parallel to the line.

The active area AA is inclined with respect to the bit line direction (horizontal direction), and the contact portion CH with the capacitor is
, has an extension part AA in a direction symmetrical to the bit line contact part Cl-1 with the axis in the direction perpendicular to the bit line (vertical direction).

CH3 is a capacitor contact portion to the shared active area AA of an adjacent cell, and this portion has an extension portion AA similar to CH3.

[Function] With this configuration, the margins of the capacitor contact portion CI (,) relative to the active region side edge Ll-LA can all be made equal.

The side edge of the active region AAO is the boundary with the thick field oxide film, and if a positional shift occurs during drilling for forming the capacitor contact part CH2 and a portion enters the side edge,
This will create a hole in the field oxide film. This generates a leakage current and impairs the charge storage properties of the capacitor. By making all the margins equal as described above, the occurrence of such a problem can be avoided as much as possible.

〔Example〕

In the present invention, as shown in FIG.
, -CH3, the side edges L+ and Lx of the active area AA are made non-parallel to the straight line connecting the centers of the active area AA. Figure 3 shows a case where these are made parallel.

When parallel, the capacitor contact hole CH7,
It becomes impossible to make all the margins for the side edges of the active area equal. That is, contact hole Cl-1
□ has a side edge like the same CH+.

Place it in the center of the active area AA with L2 (drill the holes so that it looks like this), but with this you can make the margins the same for CH1 and L, but not for CH. No. That is, the active area AA is bent as shown in the figure at the contact hole CHZ. Specifically, the active area AA is an extension part AA in a direction symmetrical to CH, with the vertical line passing through the center of CH as the axis of symmetry.
+, so the side edge of this extension, and CH
Even if the interval δ2 between L1 and CHt is equal to the interval δ1 between L1 and CH, the interval δ3 between CHt and the intersection p+z of the side edge L4 of the extended portion and the side L2 is not equal to the interval δ1δ2. δ3〉δ1. δ2, which is equal to the extension line of 2 shown by the dotted line and CH! The interval is .

Therefore, in the present invention, as shown in FIG. 2(b), L+.

Tilt L2 as shown by the dotted line so that δ1-δ2=δ. The shift amount d for this purpose can be calculated as follows.

As shown in Fig. 4, if the center of the contact hole CHZ is Po, a perpendicular line P extending from this point to the side edges, L,
oH+ and PoHz are the extreme distances, and δ and δ2 are the intervals of this portion. The distance between the side edge Lz, Li and CH is indicated by the line PoP+z drawn from Po to the intersection point ptz, and δ
, is the interval of this part. As mentioned above, L2 is parallel to L, L, L.

If it is line symmetrical to L+, Lz, then δ3>δ1, δ.

Therefore, we changed the very natural idea of making ,L, parallel to L and made it non-parallel as shown in Figure 2. That is, as shown by the dotted line, the side edge L1. L! Rotate the intersection point P1
Move ° to pH and the intersection point P to Plff. PII
+P In point can be determined under the condition that P, H5=PoP11. Note that H3 is the end point of a perpendicular line that is dotted and descends from Po.

Note that even if this deformation (the above rotation) is performed, the side edge L1°12
It is reasonable to maintain the width F of the active region of the part from the viewpoint of maintaining the gate width W of the transistor, but this may cause failure in pattern creation. The pattern must be deformed under the condition of P + zP + a = P + t P 13. Under this condition, W becomes slightly narrower, but in reality, this change can be completely ignored.

Move the intersection points P1□ and P14 upward by d and get P+t+P
+i, but in this case, the center of rotation of the side edge is the second
As shown in the figure, set CH to nearby point 01.

The center of CH, is set to 0, and the perpendicular line 00. =f.

If the slope 1j of the line is θ, the following equation is obtained.

2f cos θ-F -----...
(1). Distance 111P between point P0 and point P. P
, is f-d, and PoHs sets the X, Y coordinates of Hl as (x
+,y+) then PoHs= (f +d)cosβ...
・Since the purpose is to obtain 6PoHs=PoPz−f d, which is (3), solve equation (3) for d, and at this time,
Since d<<a, b, equations (2) and (4) are equal to 1. Therefore, if tanβ=tanθ, then = f−d, tanθ= b / a ...... (2) The optimal shift ild can be calculated using the second equation (5).

The purpose of adding the extension parts AA, . . . AAZ to the active area AA is to expand the active area around the capacitor contact part as much as possible, and to cope with the narrowing of the active area in this part during field oxidation. The purpose is to make it difficult for the field section to collide with the field section. The extension portions AA, . . . AAZ have the above-mentioned line-symmetric shape due to the highly integrated arrangement of memory cells and the orderly arrangement with symmetry/repeatability.

Side edge L1 of active area. If L2 is parallel to the center line, δ, 〉δ1. becomes δ2, contact hole CH
z is likely to come into contact with the field oxide film on the side edges, L,. Although the collision of the capacitor contact portion with the field oxide film itself is not a fatal problem, as the degree of overlap (collision) increases, the deterioration of the junction breakdown voltage becomes more severe. That is, under the field oxide film, impurities of the same conductivity type as the basic one are ion-implanted at a relatively high concentration for channel strength/contact, and the more the capacitor contact parts overlap in this region, the more the impurity increases. Since the P-type head region and the N-type region with high concentration come into contact with each other, the junction breakdown voltage decreases, and leakage current is likely to occur. Stacked capacitor type mouth 1? In AM, although the capacitor contact may be located at a position where it touches the field oxide film to some extent, it is preferable from the viewpoint of suppressing leakage current that it does not collide with the field oxide film as much as possible.

Above (5) 2, a and b are contact holes CH,,CH
1/2 of the distance in the X and Y directions between the two, therefore CHs ~ CHz
The distance in the X and Y directions between
times, b is the bit line pitch (in case of folded bit line structure)
There is also.

An example is shown in FIG. a = 1.8 μm, b = 1 μm
m, and the memory cell area is a x b = 1.8 μm2
It is. In this case, the position correction dimension d is calculated to be d = 0.0165 since the radius of the active region (transistor gate width) is 0.43 μm. However, in this example, d = 0.02 μm. Depending on manufacturing conditions, d may be further increased. This is because when the field oxide film is formed by selective oxidation, the convex portions of the field oxide film pattern are difficult to oxidize, while the concave portions are easily oxidized. Since the field oxide film under the contact hole CHZ in FIG. 5 does not protrude much, it is necessary to correct the position of the active region more than when assuming an ideal state.

This FIG. 5 is of the format shown in FIG. 9(b). The manufacturing order is word line WL, make a contact hole and make bit line BL, make contact hole and make capacitor electrode CE,
The order will be... The method of extending the active region diagonally to the bit line is effective in the method of passing the bit line through the valley as described above, as well as the method of passing the bit line under the capacitor electrode as in this example.

〔Effect of the invention〕

As explained above, according to the present invention, when the capacitor contact portion is randomly misaligned with respect to the active area, junction leakage, which is a problem caused by misalignment, does not occur in a specific direction, and the dynamic RAM This can contribute to improving charge retention characteristics.

[Brief explanation of drawings]

Figure 1 is an illustration of the principle of the present invention, Figure 2 is an explanatory diagram of the pattern in Figure 1, Figure 3 is an explanatory diagram showing a pattern with parallel side edges, and Figure 4 is an illustration of each part of the pattern in Figure 3. 5 is a schematic plan view showing an embodiment of the present invention, FIG. 6 is an explanatory view of a stacked capacitor type memory, FIG. 7 is a sectional view showing a specific example of FIG. 6, and FIG. 8 is a schematic plan view showing an embodiment of the present invention. 9 is a sectional view of FIG. 8, and FIG. 10 is a sectional view and a plan view of the memory of FIG. 9(b). In Figure 1, WL is a word line, AA is an active area, and L. x is its side, L and center line, AA. is the extension part, CH. is a pit line contact portion, and Hz is a capacitor contact portion. Applicant R Shitsu Stock % Formula % Figure 3 Explanatory diagram of each part of the pattern Figure 4 CM: Capacity contact part Figure 1 Figure 2 Explanatory diagram of star 1 capacitor type memory Figure 6

Claims (1)

[Claims] 1. It has a MOS transistor and a capacitor, and the MOS
A stacked capacitor type DRAM cell in which one of the source and drain regions of the transistor is in contact with a bit line (BL) and the other is in contact with the capacitor, and the bit line is wired on the MOS transistor via an insulating film, and the MOS The active area (AA) of the transistor is an integral part connecting the contact part with the bit line (CH_1) to the contact part with the capacitor (CH_2), and is inclined with respect to the bit line. , in a semiconductor memory device having the cell, in which an extended portion (AA_1) of the active region is added in a direction symmetrical to the bit line contact region with respect to a line perpendicular to the bit line as an axis; , the line connecting the centers of both contact parts (
By making the side edges (L_1, L_2) in the L) direction non-parallel to the line connecting the centers, the positioning margin of the capacitor contact portion with respect to the active area can be set to which side (L_1 to L_4) of the active area. A semiconductor memory device characterized in that the values are the same.