JPH03266294A - Dynamic memory - Google Patents

Abstract

PURPOSE:To save the trouble of the arbitration of data access and refreshment by dividing two pairs of low decoders, word lines, bit lines, bit lines precharging circuits and sense amplifying circuits into ones for refreshing and ones for data access respectively. CONSTITUTION:When a pair of bit lines 5-1a and 5-1b is precharged to a fixed electric potential by a bit line precharging circuit 1-1 in the case of data- accessing memory cell capacitance 4-1 and a word line 2-1 is selected by a first low decoder 7-1, the information of the memory cell capacitance 4-1 is presented on the bit line 5-1a by a transistor 3-1a. Besides, when a pair of bit lines 5-2a and 5-2b is precharged to the fixed electric potential by a bit line precharging circuit 1-2 and a word line 2-2 is selected by a second low decoder 7-2 in the case of refreshing memory cell capacitance 4-2, the information of the memory cell capacitance 4-2 is presented on the bit line 5-2a by a transistor 3-2. Thus, the arbitration in an external part of refreshment and the data access is eliminated.

Description

[Detailed description of the invention] Industrial applications The present invention relates to dynamic memory.

Conventional technology FIG. 2 shows the internal configuration of a conventional dynamic memory.

In the figure, 1 is a bit line precharge circuit, and 2 is a word line. The memory cell is composed of a transistor 3 driven by a word line 2 and a memory cell capacitor 4. 5 is a bit; 6 is a sense amplifier a. The basic operation of the dynamic memory will be explained below.

When accessing the memory cell capacitor 4 (first, the bit line 5 is precharged to a predetermined potential by the bit line precharge circuit 1 and the operation begins.

Thereafter, when the transistor 3 is driven by the word line 2 selected by a row decoder (not shown), information on the memory cell capacitance 4 appears on the bit line 5. Eventually, the potential of the bit line 5 is amplified by the sense amplifier 6, and data access to the dynamic memory (after the basic operation described above, the data on the bit line selected by a column decoder (not shown) is output to the outside via the internal data bus. This can also be done by writing data from the outside into the memory cell capacitor 4 through the internal data bus. It is necessary to refresh the information in row (X, memory cell capacity 4).Data access is an external request, and refresh is a request determined by the specifications of the dynamic memory.

In the conventional configuration (as shown in Figure 2, the memory cell capacity that can be accessed at a time in one memory cell column in the bit line direction is one), so if the above two requests occur at the same time, data access is limited to refresh. Problems to be Solved by the Invention Even if Data Access Requests and Refresh Requests Occur at the Same Time When Data Access Requests and Refresh Requests Occur at the Same Time, Data Access Needs to Be Temporarily Standby; The present invention, which previously required an external circuit to mediate between access and refresh, is related to dynamic memory. It is possible to perform refresh within the dynamic memory regardless of whether or not there is data access, thereby eliminating external mediation between refresh and data access. It is an object of the present invention to provide a dynamic memory capable of solving the above-mentioned problems.Means for solving the problems The present invention aims to solve the above-mentioned problems. The present invention has the above-described configuration, and the present invention has two sets of row decoders, a word line, a bit line, a bit line precharge circuit, and a sense amplifier circuit, respectively, for refreshing and for data. When accessing data, the rope coater for data access, the bit line precharge circuit, the word line, the bit line, and the sense amplifier operate according to the timing given from the outside, and are connected to the internal data bus through the column decoder to exchange data. Row 2 Naware 4 -X
Regarding the refresh operation, the refresh timer starts operating at a predetermined period determined by the refresh timer.As long as the refresh counter is counted up, even if the refresh address is incremented, the refresh row decoder, bit line precharge circuit, word style In this case, there is no data access, so there is no need to connect it to the column decoder. Embodiment A dynamic memory according to an embodiment of the present invention is shown in FIG. 1. In the same figure, 1 -1, 1-2 are bit line preacher 9th section 2-1, 2-2 are word salts 3-1a,
3-2 are transistors driven by the word lines 2-1 and 2-2. 4-114-2 is the memory cell capacity. Bit lines 5-1a, 5-1b, bit line 5-2a
, 5-2b constitute a bit line pair.
-2 is a sense amplifier.

When accessing data to the memory cell capacity 4-1, the bit line precharge circuit 1-1 first performs data access to the bit line pair 5.
-1a and 5-1b are precharged to a predetermined potential.

Thereafter, the word line 2-1 is
When is selected, information on the memory cell capacitance 4-1 appears on the bit line 5-1a by the transistor 3-1a. Eventually, the potential of the bit line 5-1a changes to the sense amplifier 6-1.
is amplified by

When refreshing the memory cell capacity 4-2 (first, the bit line precharge circuit 1-2 refreshes the bit line pair 5).
-2a and 5-2b may be precharged to a predetermined potential.
Thereafter, the word line 2-2 is decoded by the 20th decoder 7-2.
is selected, information on the memory cell capacity 4-2 appears on the bit line 5-2a by the transistor 3-2.
Eventually, the potential of the bit line 5-2a is amplified by the sense amplifier 6-2.

Data access is an external request, and refresh is a request determined by the specifications of the dynamic memory, so these requests may occur simultaneously. For example, transistors 3-1a, 3-1b1, memory cell capacity 4
The case where refreshing is performed at the same time as data access in a cell consisting of -1 will be explained below. (1) When a data cycle starts while refreshing is amplified onto the bit line 5-2b via the transistor 3-1b.On the other hand, since the driving capability of the sense amplifier 6-1 is designed to be slightly larger than that of the sense amplifier 6-2, especially during writing, the sense amplifier 6- Number 1 is given priority. Writing is performed normally. Write operation 1
The data on the data bus 9 is written to the memory cell capacitor 4-1 through the bit line 5-1a and the transistor 3-1a through the sense amplifier 6-1.

(2) If a refresh cycle starts during data access, the information in the memory cell capacity 4-1 may be amplified by the sense amplifier 6-1 on the bit line 5-1a via the transistor 3-1a. Even if the data on the internal data bus 9 is written to the memory capacity 4-1 through the bit line 5-1a during writing, the driving capacity of the sense amplifier 6-2 will be reduced even if the sense amplifier 6-2 starts operating during the data access cycle. Sense amplifier 6 is smaller than sense amplifier 6-1 and does not affect data access.Sense amplifier 6
-2, the information in the memory cell capacitor 4-1 is refreshed on the bit line 5-2b via the transistor 3-1b.

As described above, in this embodiment, the bit lines that become active are different when the sense amplifier is accessing data and when refreshing. Each memory cell has two sets of row decoders, a word line, a bit line, a bit line precharge circuit, and a sense amplifier circuit.
By dividing the bit line precharge circuit and sense amplifier circuit into one for refresh and one for data access, the bit line precharge circuit and sense amplifier circuit operate differently for data access and refresh. Refreshing can be performed inside the memory regardless of whether data is being accessed or not, so there is no need to arbitrate between data access to dynamic memory and refreshing on the outside.

[Brief explanation of drawings]

FIG. 1 is a peripheral circuit diagram of a memory cell according to an embodiment of the present invention. FIG. 2 is a peripheral circuit diagram of a conventional memory cell.

Claims (1)

[Claims] a memory cell composed of a charge storage capacitor and two transistors connected to the charge storage capacitor; two sets of word lines for independently driving the two transistors; and a memory cell for each of the two transistors. two sets of connected bit lines for reading and writing data; two sets of bit line precharge circuits and two sets of sense amplifier circuits respectively connected to the two sets of bit lines;
A dynamic memory comprising two row decoders for selecting the two sets of word lines and a column decoder for connecting one of the two sets of bit lines to an internal data bus.