JPS6045502B2 - Semiconductor content addressable memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic MIS content addressable memory circuit having a self-refresh function.

Conventionally, 4-element and 6-element type dynamic MIS content addressable memory circuits are known, but these dynamic type MIS content addressable memory circuits have a refresh control circuit and a rewrite circuit outside the content addressable memory cell array. was needed.

Furthermore, in rewriting, there are significant restrictions on the control timing, and the number of locks that are generally required increases, and the operating speed is also slowed to ensure a margin between clocks. As described above, conventional dynamic MIS content addressable memory circuits have disadvantages such as increased amount of metal in peripheral circuits and slow operation speed.
It was hot. In order to eliminate these drawbacks, the present invention uses two dynamic random access memory circuits and one MIS transistor to enable associative operation while preserving the self-refresh function, thereby creating a Thai-Namik type MIS associative memory. DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit is provided and will now be described in detail with reference to the drawings.

The figure shows one embodiment of the invention.

In the figure, 1 is a first unit with a self-refresh function.
A dynamic random access memory circuit with Q1
-1, Q2-1, Q3-1 are the MIS transistors,
C-1 is the capacity. Similarly, 2 is a second random access memory circuit, Q1-2, Q2-2, Q3-2 are its MIS transistors, and C-2 is a capacitor. B-1 is the number of bits of the first random access memory circuit 1, K1
-1 is a common line of the same memory circuit, B-2 is the bit number of the second random access memory circuit 2, and K1-2 is a common line of the same memory circuit. K2, K3, K4 and K5 are common lines common to both random access memory circuits 1 and 2. In the first random access memory circuit 1,
The sources of MIS transistors Q1-1, Q2-1, and Q3-1 are connected in common, and the sources of MIS transistors Q1-1
The drain of MIS transistor Q is connected to the common line K1-1.
The drain of 3-1 is connected to bit line B-1.
The gate of MIS transistor Q1-1 is connected to the drain of MIS transistor Q2-1, the connection point thereof is connected to common line K2 via capacitor C-1, and the gate of MIS transistor Q2-1 is connected to common line K3. , the gates of the MIS transistors Q3-1 are connected to the common line. Configuring the second random access memory circuit 2■
S transistor Q1-2, Q2-2, Q3-2, capacitance C
The connection relationship of -2 is exactly the same. MIS transistor Q1 in this first random access memory circuit 1
-1, Q2-1, Q3-1, the source of ■S transistor Q4 is connected to the common source of MIS transistors Q1-2, Q in the second random access memory circuit 2.
MIS transistor Q is connected to the common source of 2-2 and Q3-2.
The drain of 4 is connected. The gate of MIS transistor O is connected to a common line 3. Now, conflicting storage data is stored in the first and second random access memory circuits 1 and 2.

That is, if binary data M to be stored is stored in the first random access memory circuit 1, inverted data M of M4 is stored in the second random access memory circuit 2.
The same applies to the opposite case, but in the following description, it is assumed that the stored data M is stored in the first random access memory circuit 1 and the inverted data M is stored in the second random access memory circuit 2. The associative operation that is a feature of the present invention will be explained below. The associative operation is an operation that outputs the exclusive OR M4S of stored data M and search data S.

In the figure, when a low potential is applied to the common lines K3 and K4 and a high potential is applied to the common line, MIS transistors Q2-1,
Q3-1, Q2-2, and Q3-2 are in the off state, and the S transistor Q4 is in the on state. In this - state, the common line K
1-2 is given a potential corresponding to the search data S, and the common line K
A potential corresponding to the inverted data S of S is applied to 1-1. Applying contradictory potentials corresponding to the search data S to the common lines K1-1 and K1-2 is a very important operation in performing associative operation, and is different from the operation of a normal random access memory circuit. be. Common line K1-1, K1-
After applying a potential corresponding to the search data S to the common line K
When a high potential is applied to MIS transistor Q4, the following potentials appear at both terminals 3 and 4 of MIS transistor Q4, corresponding to the binary states of storage data M and search data S. When 1M=low potential and S=low potential, the stored data M is at a low potential, so the MIS transistor Q1-1 is in the off state, and the inverted data M is at a high potential, so the MIS transistor Q1-2 is in the on state. ,
The potential S of the common line K1-2 appears at the terminals 3 and 4, and becomes a low potential.

That is, MlS=0. When 2M=low potential and S=high potential, as in case 1, ■S transistor Q1-1 is off, Q1-2 is on, and terminals 3 and 4 are connected to the common line K.
A potential S of 1-2 appears and becomes a high potential.

That is, MlS=1. When 3M=high potential and S=low potential, the stored data M is at a high potential, so the MIS transistor Q1-1 is in the on state, and the inverted data M is at a low potential, so the S transistor Q1-2 is in the off state. The potential of the common line K1-1 appears at terminals 3 and 4, and becomes a high potential.

That is, MlS=1. 4 When M=high potential and S=high potential, MIS transistor Q1-1 is on, Q1-2 is off, and terminals 3 and 4 have the potential of the common line K1-1, as in case 3. appears and becomes a low potential.

That is, M(f)S=0. In this way, MIS
By outputting the source/drain terminals 3 and 4 of the transistor Q4, the exclusive OR MlS of the storage data M and the search data S is outputted, thereby achieving an associative operation. Note that during write operation, read operation, and self-refresh operation, the common lines K1-1 and K
1-2 should be given a high potential, and the common line K5 should be given a low potential. Other than that, the operation is the same as that of a normal random access memory circuit having a self-refresh function consisting of three transistors and a capacitor, so a description thereof will be omitted. As explained above, in the present invention, a dynamic content addressable memory circuit having a self-refresh function can be constructed, so that the following advantages arise.

(1) The amount of hardware in peripheral circuits has been reduced), so the capacity of the associative memory itself can be increased.

(2) Restrictions on control timing in rewriting are not as great as in the past, and high-speed operation is possible by the margin provided between clocks in the past.

[Brief explanation of drawings]

The figure shows an embodiment of a semiconductor content addressable memory circuit according to the present invention. 1, 2...Random access memory circuit, 3,
4...Output terminal, Q1-1, Q2-1, Q3-
1, Q1-2, Q2-2, Q3-2, Q4...
MIS transistor, B-1, B-2...Bit line, K1-1, K1-2, K2, K3, K4, K5
・・・・・・Common line.

Claims (1)

[Claims] 1. The sources of the first, second, and third MIS transistors are connected in common, the drain of the first MIS transistor is connected to the first common line, and the drain of the second MIS transistor is connected to the first MIS transistor. connect to the gate of
The drain of the third MIS transistor is connected to the bit line, and the gate of the first MIS transistor and the second MIS transistor are connected to each other.
A connection point of the drain of the transistor is connected to a second common line via a capacitor, a third common line is connected to the gate of the second MIS transistor, and a fourth common line is connected to the gate of the third MIS transistor. connecting the second, third, and fourth common lines of the first and second random access memory circuits, respectively, using two dynamic random access memory circuits having a self-refresh function connected to each other; 3 of the first and second random access memory circuits;
A fourth MIS transistor is connected between the common sources of two MIS transistors.
connected to the source and drain of the transistor, and the fourth M
Connecting a fifth common line to the gate of the IS transistor,
storing conflicting storage data in the first and second random access memory circuits, applying conflicting search data to first common lines of the first and second random access memory circuits, respectively; 2. A semiconductor content addressable memory circuit, characterized in that an associative output of storage data and search data is obtained at the source/drain terminals of the fourth MIS transistor by controlling the potentials of the third, fourth, and fifth common lines.