JPH03263681A - First-in first-out circuit - Google Patents

Abstract

PURPOSE:To attain miniaturization of the circuit, to improve the degree of integration of a semiconductor device and to reduce the cost by providing an address comparison section comparing bit addresses counted up by a write word address counter and a readout word address counter and a signal output section. CONSTITUTION:An address coincidence comparator circuit 34 compares count-up of each address of a write word address counter 30 and a readout word address counter 32 and outputs a signal representing the processing indicating a state (FULL state) of end of write to all addresses of a memory 10 or a signal representing the processing indicating a state (EMPTY state) of no write to all addresses of the memory 10 based on the information representing the state of write or read. Since it is not required to provided a flip-flop to each word address, a FULL signal and an EMPTY signal are surely outputted with simple circuit constitution. Thus, the miniaturization of the circuit and the degree of integration of the semiconductor device are improved and the cost is reduced.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a first-in-first-out circuit used when writing and reading data into and from a memory of a semiconductor integrated circuit, for example, in a predetermined order.

[Conventional technology]

Conventional typical first-in, first-out processing (
Some Fast In Fast Out (hereinafter abbreviated as FIFO) circuits have a configuration as shown in FIG. 5, for example. The FIFO circuit in FIG. When a write request signal is applied to this FIFO circuit along with input data, the data is written to the storage unit 10 according to the bit counter 13 indicating the write word address by the operation of the write control unit 12; Each time the count is increased by one, the flip-flops 14 prepared for each address are sequentially set to r1j.Also, when reading the written data, the read request signal is given as in the case of writing. When the read control unit 16
As a result of the operation, data is read from the storage section 10 according to the counter 17 of the ■ bit indicating the calling word address, and at the same time, the flip-flops 14 are sequentially reset to "0" every time the counter 17 counts up by one. In addition, in the figure, the code 22A is a write decoder;
22B is a read decoder. 24A and 24B are operational amplifiers for writing and reading data into and from the storage unit 10 using write and read permission signals. Here, when the flip-flops 14 are all set to "1", the AND circuit #118 on the output side of the flip-flops 14 is activated, indicating that writing to all addresses in the storage section 10 has been completed. The signal (FULL signal) is A
The signal is output from the ND circuit 18 to the write control unit 12 to prohibit further writing. Conversely, when all the flip-flops 14 become "0", the output of the flip-flops 14 becomes N. The R circuit 20 is activated, and a signal (EMPTY signal) indicating that nothing has been written to any address is sent to the NOR
The signal is output from the circuit 20 to the read control unit 16, and further reading is prohibited.

[Problem N that the invention attempts to solve]

However, in the conventional FIFO circuit, the FULL
In order to form the signal and the EMPTY signal, the storage unit 1
Since the same number of flip-flops 14 as the number of addresses of 0 is required, when using a large capacity FIFO circuit with a large number of addresses, the number of required flip-flops becomes too large and the size becomes large. . Further, multi-stage logic is required to obtain the logical OR (NOR) and logic wI (AND) of the outputs of the flip-flops, making the configuration of the logic circuit complicated. Therefore, conventional FIFO circuits inevitably become larger and more complex, which poses a problem in improving the degree of integration of semiconductor devices and reducing costs. The present invention was made to solve the above-mentioned conventional problems, and it is possible to reliably handle the FULL signal and E M with a simple circuit configuration.
An object of the present invention is to provide a first-in first-out circuit that can output a PTY signal.

[Means to solve the problem]

In a first-in-first-out circuit, the present invention includes an address comparison section for comparing the count-up of each address of a write word address counter and a read word address counter, and a comparison result and a memory in a write or read state. To output a signal indicating that writing has been completed to all addresses in memory, or a signal indicating that nothing has been written to all addresses in memory, based on information indicating that writing has been completed to all addresses in memory. The above-mentioned problem has been solved by providing a signal output section.

[Effect]

First-in first-out circuit (FIFO times B)
In this case, writing and reading of data is performed according to the address indicated by each of the write word address counter and the read word address counter counting up by one. Therefore, the inventor conducted various investigations and considerations regarding the operation of read and write word address counters. The results will be explained, for example, with reference to the schematic diagram of FIG. 1 which shows the count-up addresses (write count-up address Aw, read count-up address Ar) of each write and read address counter (number of words n=21'n). That is, as shown in FIG. 5A, in the initial state where nothing is written in the memory (EMPTY state),
The count-up address of each counter is equal (AV
=Ar). Next, when data writing begins, the same figure (
As shown in B), the write food address counter sequentially counts up, and the count-up addresses become different (AV≠Ar). In this case, when reading is performed and the read counter's count-up address A' becomes equal to the write count-up address AW (AV = Ar), E
It becomes MPTY state. Also, as the writing progresses, the write address exceeds the highest address (AV=2m-1 in the figure) and returns to the first address (address Av=O in the figure), as shown in (D) in the same figure. progresses, and the write address becomes equal to the read address, as shown in FIG.
=Ar) +No more data can be written to the memory (FULL state). Therefore, it is understood that both the EMPTY state and the FULL state occur when the write address Aw and the read address Ar are equal. Therefore, by determining the condition of AV=Ar, it can be determined that either the EMPTY state or the FULL state has occurred. Furthermore, when each address satisfies the condition of AW = Ar, determining whether the memory is in the EMPTY state or the FULL state is based on information indicating that the memory is in the write or read state. It can be done based on For example, the number of bits of each address counter for writing and reading is increased by one from the number of bits of the memory, and the most significant bit (AjL Ajr) is used as a bit for determining whether the write address Aw precedes or not. Apply to. The output of this bit allows Ajw=
A jr is in t′Lζi writing state, and AJv4=
For example, if a write request signal is currently being input, it is in the write state, and if a read request signal is currently being input, it is in the read state. The signals can be write and read information. Based on the above, compare how far each counter has counted up, and based on the information indicating the write or read status, determine the state Q (FULL 8: state) in which writing has been completed to all addresses. ), nothing is written to all addresses! g<EMPTY condition!
The present invention was conceived based on the idea that it is possible to know 9). According to the present invention, there is no need to provide a flip-flop for each word address as in the conventional case, so a simple circuit i.
Alternatively, the FULL signal and EMPTY signal can be reliably output. Therefore, it is possible to reduce the size of the FIFO circuit, thereby increasing the degree of integration and reducing the cost of semiconductor devices such as semiconductor integrated M circuits.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. First, a first example will be described. This first embodiment has an 11+ configuration as shown in FIG.
A write address counter 30 with 1 bit and l+
It is a FIFO circuit having a 1-bit read address counter 32 and an address-number comparison circuit 34 for outputting a FULL signal or an EMPTY signal from a comparison of each count-up address of each address counter 30.32. The rest of the configuration is the same as the conventional FIFO circuit shown in FIG. 5 above, so similar parts are given the same numbers and their explanation will be omitted. The FIFO circuit according to the embodiment is characterized in that the number of bits of the address counters 30 and 32 is increased by one than the number of bits required for the word address of the storage section 10. That is, if the memory has n==2m words (memory>10), the number of bits of each address counter 30-32 is m+1 bits.
．． In 32, the lower m bits (Awo ~ AWI1
1-1, Aro-Ar1-1) to each decoder 22A.
, 22B, and the most significant 1
The bits (Ajw, Arj) are used as a FULL state determination signal and an EMPTY state determination signal. Further, as shown in detail in FIG. 3, the address-number comparison circuit 34 outputs exclusive logic 81f! of the same bit number of each counter 30.32. - Exclusive or times to take #l36(0)~36〈7-1)-3
6 monks, NOR times N38, NA, ND circuits 40,
It consists of a combination of inverters 42. The sequence of the address counter of the FIFO circuit according to the embodiment will be explained based on FIG. 1 mentioned above. In the FULL state, each determination signal of the most significant bit is Ajw≠
Ajr and the count-up address of each counter 30.32 is determined from AvL=Ar, and EM
The PTY state is determined from the fact that Ajw=Ajr and Aw=Ar. That is, in FIG. 3, if nothing is written in the storage section 10 at the time of start, both the write address Al and the read address Ar are the first address O10. Furthermore, the most significant bits AjJ and Ajr are all 0, with no count up. Therefore, from the address-number comparison circuit 34, AW=A'',
Moreover, since Ajw=Ajr, the storage section 10 is
It is determined that the state is MPTY. Next, the state in which the write address has advanced to J2 is shown in the same figure (B
) and AV +Ar, the state of the storage unit 10 is Ft
Neither JLL nor EMPTY. After that, reading starts, and the state in which the read address A' catches up with the write address AW and becomes AW = Ar is shown in Fig. 3 (C). In this case, Aw = Ar, and the most significant bit is AJW because the count is not up
=Ajr, it is determined that the storage unit 10 is in the EMPTY state. Furthermore, the writing address advances, and writing to the highest address 2rn-1 is completed, as shown in (D) of the same figure.
Assume that the count is increased from the initial address 0. In this case, the most significant bit AJw for writing is counting up, but the most significant bit AJ for reading is counting up, resulting in AJW#AJr.However, AV
≠8, so it is not in the FULL state.Furthermore, as the write address AM advances and becomes Aw = Ar as shown in (E) in the same figure, each of the most significant bits becomes A.
jw, i-Ajr, the storage unit 10
It is determined that the memory of is in the FULLfl: state. In this embodiment, zero flip-flop outputs had to be detected ζ2, as shown in FIG. 5 above.
Compared to a conventional FIFO circuit, if the outputs of the (11) bit address counters are compared, the memory section 10 is EMPT.
Since it is possible to accurately determine whether the Y state or the FULL state is present, a comparator circuit can be used instead of a flip-flop, and the FIFO circuit can be significantly simplified. Next, a second example will be described. In the first embodiment, as shown in FIG. 3, in the address-number comparison circuit 34, the write address counter 3
0 and the read address counter 32 are (rI+1) bits, and the FULL state of the memory, E
The MPTY status was determined. On the other hand, this second
In the embodiment, as shown in FIG.
An 11-bit address counter is used instead of 0+1 bits, and a latch circuit 44 consisting of a flip-flop is used to send a write request signal and a read request signal to the NAND circuit 40.
It is designed to be input via W and 44R. In this second embodiment, it is determined whether the count-up address outputs of the respective write address counters (outputs AWO to Awn-1) and read address counters (outputs ArO to Arl'1l-1) of width bits match. The exclusive OR circuits 36(0) to 36(n-1) make a judgment, and the outputs of these exclusive OR circuits 36 are NORed. Further, the read request signal or the write request signal is latched by the latch circuits 44W and 44R, and ANDed with the output of the NOR circuit 38 to determine the EMPTY state or the FULL state. That is, when the write address AV and the read address Ar are equal (AW = Ar), the storage unit 1o is in the EMPTY state when the read request signal is input, and the storage unit 1o is in the EMPTY state when the write request signal is input.
It can be determined that 0 is a FULL state.

【Effect of the invention】

As explained above, according to the present invention, the memory is FULL.
However, it is possible to reliably determine the EMPTY state using a circuit configuration that is much simpler than the conventional one. Therefore, excellent effects can be obtained in that the degree of integration of semiconductor integrated circuits can be improved and costs can be significantly reduced.

[Brief explanation of drawings]

1 is a schematic diagram showing the counting status of each address counter for detailed explanation of the present invention; FIG. 2 is a block diagram showing the configuration of a FIFO circuit according to a first embodiment of the present invention; 3 is a logic circuit diagram showing a configuration example of an address-number comparison circuit in the circuit, and FIG. 4 is a logic circuit diagram showing a configuration example of an address-number comparison circuit according to a second embodiment of the present invention. , Figure 5 shows the conventional F
FIG. 2 is a block diagram showing an example of an IFO circuit. 40...NAND circuit. 44...Latch circuit.

Claims (1)

[Claims] (1) An address comparison unit for comparing the addresses of bits that are counting up in the write word address counter and read word address counter, and the result of the comparison and whether the memory is in the write or read state. a signal output unit for outputting a signal indicating that writing has been completed to all addresses of the memory or a signal indicating that nothing has been written to all addresses of the memory, based on the information indicated; A first-in-first-out circuit characterized by comprising: