JPH03263337A - Method of connection of integrated circuit device - Google Patents

Method of connection of integrated circuit device

Info

Publication number
JPH03263337A
JPH03263337A JP2062931A JP6293190A JPH03263337A JP H03263337 A JPH03263337 A JP H03263337A JP 2062931 A JP2062931 A JP 2062931A JP 6293190 A JP6293190 A JP 6293190A JP H03263337 A JPH03263337 A JP H03263337A
Authority
JP
Japan
Prior art keywords
integrated circuit
dielectric substrate
package
gnd
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2062931A
Other languages
Japanese (ja)
Other versions
JP2541336B2 (en
Inventor
Kazufumi Takahashi
和史 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2062931A priority Critical patent/JP2541336B2/en
Publication of JPH03263337A publication Critical patent/JPH03263337A/en
Application granted granted Critical
Publication of JP2541336B2 publication Critical patent/JP2541336B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid reflection of a signal caused by impedance mis-matching and improve the performance of a radio frequency circuit by a method wherein one surface of a dielectric substrate is entirely grounded and microstrip lines are formed on the other surface and the terminal electrodes of a package and the terminal electrodes of an integrated circuit are connected to each other with the microstrip lines. CONSTITUTION:An integrated circuit 1 is a semiconductor chip having no covering and is mounted on a package 2. One surface of a dielectric substrate 5 is entirely used as ground (GND) 7 and conductor patterns 6 are formed on the other surface. The conductor patterns 6 are composed of microstrip lines which have characteristic impedances determined by the pattern widths, the dielectric constant of the dielectric substrate 5, the thickness of the dielectric substrate 5, etc., and are connected to both the electrodes 3 of the package 2 and the electrodes 4 of the integrated circuit 1. Further, the ground (GND) 8 of the package 2 is connected to the GND 7 of the dielectric substrate 5 with bonding wires 9.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路の接続方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for connecting integrated circuits.

〔従来の技術〕[Conventional technology]

従来この種の技術として、第４図に示すように、集積回
路１の端子電極４と他の端子電極、例えばパッケージ２
の電極３とボンディングワイヤ９で接続するワイヤボン
ディング法がある。Conventionally, as shown in FIG.
There is a wire bonding method in which the electrode 3 and the bonding wire 9 are connected.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の集積回路装置の接続方法の一例であるワ
イヤボンディング法は、ワイヤ自体のインピーダンスが
高インピーダンスになっており、高周波域では接続した
回路の伝送線路とインピーダンスの不整合を生じ、反射
損を大きくさせるなど、性能劣化の原因となる欠点を有
していた。In the wire bonding method, which is an example of the above-mentioned conventional method for connecting integrated circuit devices, the impedance of the wire itself is high, and in the high frequency range, impedance mismatch with the transmission line of the connected circuit occurs, resulting in reflection loss. It had drawbacks that caused performance deterioration, such as increasing the

〔課題を解決するための手段〕[Means to solve the problem]

本発明は集積回路の端子電極と他の任意の端子電極とを
接続する集積回路装置の接続方法において、片面全面を
グラウンドとし且つこのグラウンドと反対の面にマイク
ロストリップ線を形成した誘電体基板を用い、前記マイ
クロストリップ線によって前記二つの端子電極間を接続
するようになっている。The present invention provides a method for connecting an integrated circuit device to connect a terminal electrode of an integrated circuit to any other terminal electrode, using a dielectric substrate having one surface grounded and a microstrip line formed on the surface opposite to the ground. The microstrip line is used to connect the two terminal electrodes.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の分解斜視図、第２図は本実
施例の接続状態を示す斜視図、第３図は第２図の要部の
断面図である。FIG. 1 is an exploded perspective view of one embodiment of the present invention, FIG. 2 is a perspective view showing a connected state of this embodiment, and FIG. 3 is a sectional view of the main part of FIG. 2.

本実施例は片面全面をグラウンド（以下、ＧＮＤ）７と
し且つこのＧＮＤ７と反対の面にマイクロストリップ線
となる導体パターン５を形成した誘電体基板５を用い、
導体パターン５によって集積回路１の端子電＠４とパッ
ケージ２の電極３とを接続するものである。In this embodiment, a dielectric substrate 5 is used, which has a ground (hereinafter referred to as GND) 7 on one side and a conductor pattern 5 forming a microstrip line on the opposite side from the GND 7.
The terminal electrode 4 of the integrated circuit 1 and the electrode 3 of the package 2 are connected by the conductor pattern 5.

即ち、集積回路１は無被覆の半導体チップであり、パッ
ケージ２に搭載される。誘電体基板５は片面全面がＧＮ
Ｄ７であり、他の一面には導体パターン６を有する。導
体パターン６は、パッケージの電極３と集積回路の端子
電［ｉ４とを接続するが、そのパターン幅と誘電体基板
５の誘電率及び基板の厚さ等により定まる特性インピー
ダンスを有するマイクロストリップ線をなし、パッケー
ジの電極３と集積回路の電極４に接続される。That is, the integrated circuit 1 is an uncoated semiconductor chip, and is mounted on the package 2. The entire surface of one side of the dielectric substrate 5 is GN.
D7, and has a conductor pattern 6 on the other side. The conductive pattern 6 connects the electrode 3 of the package and the terminal voltage [i4] of the integrated circuit, and is a microstrip line having a characteristic impedance determined by the width of the pattern, the dielectric constant of the dielectric substrate 5, the thickness of the substrate, etc. None, connected to electrode 3 of the package and electrode 4 of the integrated circuit.

また、パッケージのＧＮＤ８と誘電体基板５のＧＮＤ７
とはボンディングワイヤ９によって接続される。In addition, GND8 of the package and GND7 of the dielectric substrate 5
and are connected by bonding wires 9.

〔発明の効果〕 以上説明したように本発明は、集積回路の端子電極と他
の端子電極とを、誘電体をＧＮＤと信号線ではさんだマ
イクロストリップ線によって接続することにより、端子
電極間の伝送線路の特性インピーダンスの値を自在に調
整することが可能になり、インピーダンス不整合による
信号の反射を防ぐことができ、高周波回路の性能を向上
させることができる効果がある。[Effects of the Invention] As explained above, the present invention connects a terminal electrode of an integrated circuit and another terminal electrode with a microstrip line in which a dielectric material is sandwiched between GND and a signal line, thereby improving transmission between the terminal electrodes. It becomes possible to freely adjust the characteristic impedance value of the line, prevent signal reflection due to impedance mismatch, and improve the performance of high-frequency circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の分解斜視図、第２図は本実
施例の接続状態を示す斜視図、第３図は第２図の要部の
断面図、第４図は従来のワイヤボンディングによる接続
例の斜視図である。 １・・・集積回路、２・・・パッケージ、３・・・パッ
ケージの電極、４・・・集積回路の端子電極、５・・・
誘電体基板、６・・・導体パターン、７・・・ＧＮＤ、
８・・・パッケージのＧＮＤ、９・・・ボンディングワ
イヤ、１０・・・半田。Fig. 1 is an exploded perspective view of one embodiment of the present invention, Fig. 2 is a perspective view showing the connection state of this embodiment, Fig. 3 is a sectional view of the main part of Fig. 2, and Fig. 4 is a conventional FIG. 3 is a perspective view of an example of connection by wire bonding. DESCRIPTION OF SYMBOLS 1... Integrated circuit, 2... Package, 3... Electrode of package, 4... Terminal electrode of integrated circuit, 5...
Dielectric substrate, 6... Conductor pattern, 7... GND,
8... Package GND, 9... Bonding wire, 10... Solder.

Claims (1)

【特許請求の範囲】[Claims] 　集積回路の端子電極と他の任意の端子電極とを接続す
る集積回路装置の接続方法において、片面全面をグラウ
ンドとし且つこのグラウンドと反対の面にマイクロスト
リップ線を形成した誘電体基板を用い、前記マイクロス
トリップ線によって前記二つの端子電極間を接続するこ
とを特徴とする集積回路装置の接続方法。In a method for connecting an integrated circuit device to connect a terminal electrode of an integrated circuit to any other terminal electrode, a dielectric substrate having one surface entirely grounded and a microstrip line formed on the surface opposite to the ground is used. A method for connecting an integrated circuit device, comprising connecting the two terminal electrodes using a microstrip line.
JP2062931A 1990-03-13 1990-03-13 Method of connecting integrated circuit device Expired - Fee Related JP2541336B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2062931A JP2541336B2 (en) 1990-03-13 1990-03-13 Method of connecting integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2062931A JP2541336B2 (en) 1990-03-13 1990-03-13 Method of connecting integrated circuit device

Publications (2)

Publication Number Publication Date
JPH03263337A true JPH03263337A (en) 1991-11-22
JP2541336B2 JP2541336B2 (en) 1996-10-09

Family

ID=13214524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2062931A Expired - Fee Related JP2541336B2 (en) 1990-03-13 1990-03-13 Method of connecting integrated circuit device

Country Status (1)

Country Link
JP (1) JP2541336B2 (en)

Also Published As

Publication number Publication date
JP2541336B2 (en) 1996-10-09

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