JPH03263246A - Address controller in patrolling storage device - Google Patents

Abstract

PURPOSE:To suppress danger for destroying data in a memory part by holding a readout address received from a control part until when patrol write processing is performed, and using it as a write address for patrol processing. CONSTITUTION:The control part 52 sends out a patrol designation signal PAT to designate that processing is patrol processing with the readout address to a memory part 51 in a readout operation in the patrol processing. The memory part 51 stores the readout address in a register 53, and reads out fetch data, and returns it to the control part 52. Also, the address stored in the register 53 is held until a write operation is performed in the patrol processing. In such a case, the memory part 51, in the case of receiving processed store data, writes the address held in the register 53. Thereby, it is enough to send a processing destination from the control part 52 to the memory part 51 only for one time when the patrol processing is performed. In such a manner, it is possible to suppress the danger to destroy the data in the memory part 51 in the patrol processing, which improves reliability.

Description

[Detailed Description of the Invention] [Summary] Regarding a patrol address control device for a storage device having a function of performing patrol processing, the present invention improves the reliability of the storage device by suppressing the risk of data destruction in the memory section during patrol processing. The aim is to reduce the hardware size as well as to reduce the hardware scale. In a storage device configured such that access to the memory section is performed via a control section, the control section includes means for sending a patrol designation signal specifying that patrol processing is being performed to the memory section during patrol processing, When the memory unit receives the patrol designation code, the memory unit is configured to hold the read address for patrol processing received from the control unit in a register until the time of patrol write processing, and use it as the write address for patrol processing.

[Industrial Application Field] The present invention relates to address control during patrolling, which performs address control during patrol processing in a storage device that includes a memory section and a control section, and the control section has a function of performing patrol processing of data stored in the memory section. Regarding equipment.

[Prior Art] As shown in FIG. 4, conventional storage devices include a memory section l having a storage area such as a RAM 12 for storing information, and a control interface for accessing this memory section 1 from an external device. It consists of two parts: Part 2.

Here, the control section 2 has a function of performing interface control with an external device 4 such as a CPU and an interface control with a memory section 1, and has an address register 21 therein for storing a processing destination address received from the external device 4. We are prepared.

On the other hand, the memory section 1 receives the R in response to a control instruction from the control section 2.
AM! The control unit 2 has an address register 11 therein for storing a processing destination address instructed by the control unit 2.

In this storage device, from CP Ll etc. to RA of memory part l
When there is an instruction for read or write processing to M12, the processing destination address specified by this CPU is first stored in the register 21 of the control unit 2, and then the address is stored in the register 21 of the control unit 2. , this register 21
The processing destination address is transferred to the register 11 of the memory section 1, and the memory section 1 controls access to the RAM 12 based on the processing destination address of the register 11.

In such storage devices, patrol processing has conventionally been performed between accesses by the CPU or the like. In this patrol processing, the control unit 2 reads the data stored in the RAM 12 of the memory unit 1, checks whether or not there is an error in the stored data, and if there is an error, detects it using an error check code (ECC) or the like. The corrected data is then written to the same address location again.
Generally, even if there is no error in the stored data, the read data is written to the same address location.

The processing sequence during this patrol processing is shown in FIG.

In FIG. 5, the access request signal REQ is a signal that conveys an access request from the control section 2 to the memory section 1, and the command signal CMD is a 1-bit signal that conveys a read/write instruction from the control section 2 to the memory section 1. and “0′
'', it becomes a fetch command, and when it is "1", it becomes a store command. Also, the address signal ADD is the processing destination address sent from the control section 2 to the memory section 1, and the store data SD is the data to be written to the memory section 1. .

To explain the operation during patrol processing with reference to FIG. 5, first, the control unit 2 sends an access request signal REQ of “l” to the memory unit l to notify that there is an access request.
A command signal CMD of '0' instructing fetch processing and a processing destination address ADD are sent.

When the memory section 1 receives these signals, it stores the processing destination address in the register 11, reads the fetch data FD from the processing destination address, and sends it to the control section 2. As a result, the control unit 2 checks the fetch data for errors, and if there is an error, it corrects it.

After this, the control unit 2 again controls the memory unit l.

Access request signal REQ of “1” conveying an access request
Then, it sends a command signal CMD of "1" that conveys a store command, an address signal ADD that specifies a processing destination address, and store data SD that has been corrected.

The memory unit 1 again stores the sent processing destination address in the register 11 and stores the sent store data SD in the address specified by the register 11.

[Problems to be Solved by the Invention] In conventional patrol processing, the control unit 2 transmits the processing destination address to the memory unit 1 by sending address signals ADD separately during fetch processing and store processing. Therefore, even though the address at the time of reading and writing the patrol process is the same, for one patrol process, the processing destination address of the register 21 of the control unit 2 is stored in the register of the memory unit l. Wasteful interface processing is performed, such as performing the same processing twice.

If such an address is sent twice for reading and writing, the probability that the sent address will be changed due to noise from the outside world increases twice, resulting in the sending address changing. In this case, the contents of the RAN 12 may be destroyed, resulting in a decrease in the reliability of the storage device.

Furthermore, in order to send the address twice, a circuit for performing the processing is required, which also causes an increase in the hardware scale of the control unit 2.

The present invention has been made in view of these problems, and its purpose is to improve the reliability of a storage device by suppressing the risk of data destruction in the memory section during patrol processing, and to improve the reliability of the storage device. The aim is also to reduce the size of software.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The patrol address control device for a storage device according to the present invention includes a memory section 51 having a register 53 that holds address information, and a control section 52 that controls access between the memory section 51 and an external device 55 via an interface. In a storage device configured such that the device 55 accesses the memory unit 51 via the control unit 52,
The control unit 52 stores a patrol designation signal PAT specifying patrol processing at the time of patrol processing in the memory unit 5.
When the memory unit 51 receives the patrol designation signal FAT, the memory unit 51 retains the read address for patrol processing received from the control unit 52 in the register 53 until the time of patrol write processing, and writes the read address for patrol processing. Configured for use as an address.

[Action 1 The control unit 52 stores the memory unit 51 at the time of reading patrol processing.
, along with the read address ADD, the patrol designation signal FA designates that the command is for patrol processing.
Send T.

Thereby, the memory section 51 stores the received read address in the register 53, reads the fetch data from the read address, and returns it to the control section 52, and holds the address stored in the register 53 until writing in patrol processing.

After performing patrol processing on the fetch data read out by the memory section 51, the control section 52 sends out the patrol-processed store data to be written into the memory section 51, but at this time does not send out the write destination address.

When the memory unit 51 receives the processed store data, it writes it to the address held in the register 53.

As a result, during patrol processing, the control section 52 only needs to send the processing destination address once to the memory section 51.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

The schematic structure of the storage device to which the patrol address control device of the present invention is applied is the same as that shown in FIG. 4 described above.

However, in the apparatus of the embodiment, the control section 2 is newly equipped with a function of sending a 1-bit patrol designation signal FAT to the memory section 1 instructing that the patrol processing is to be performed during the patrol processing.

Further, FIG. 2 shows a circuit configuration on the memory side including an address set circuit 30 that receives the patrol designation signal PAT and the like. In FIG. 2, 30 is an address set circuit which includes a NAND circuit 31 to which a patrol designation signal FAT and a command signal CMD are input, and a NAND circuit 31 to which a patrol designation signal FAT and a command signal CMD are input.
It consists of an AND circuit 32 to which the output signal of the circuit 31 and the access request signal REQ are input, and the output signal of the AND circuit 32 is input to the control input terminal of the address register 11 as the address set signal AST.

These access request signal REQ, command signal CMD,
Each of the patrol designation signals PAT is a 1-bit signal, and the address set circuit 30 determines the access mode from the control unit 2 to the memory unit as follows based on a combination of these signals. That is, ■PAT=0. When CMD=0, it is a normal fetch processing request ■PAT=O, when CMD=1, it is a normal store request ■PAT=1. When CMD=0, fetch request during patrol processing ■PAT=1
．． When CMD=1, it is determined that the request is a store request during patrol processing.

Address set signal A is output to register 11.
When ST is ■, ■, ■, °'l", when it is ■, '0"
Make it.

The address signal ADD sent from the control unit 2 side is input to the data input terminal of the register 11, and this register 11 becomes the data input terminal when the address set signal AST from the address set circuit 30 is 1". The input address signal ADD is taken in and held, and
”, the data capture process is not performed.The address signal held in this register 11 is R.
It is output to the AM12 interface.

The operation of this embodiment will be explained below with reference to FIG. Here, FIG. 3 is a diagram showing a processing sequence during patrol processing by the embodiment device.

During patrol processing, the control unit 2 sends an access request signal REQ of "1-" to the memory unit 1, indicating an access request.
, a command signal CMD of "O" indicating a fetch command, a patrol designation signal PAT of '1'' designating patrol processing, and an address signal ADD designating a processing destination address are sent.

When the memory section 1 receives these signals, the address set circuit 30 determines whether or not to take in the address signal ADD received from the control section 2 into the register 11 in accordance with the aforementioned determination conditions (1) to (4).

At the time of fetching the patrol processing in (2), the NAND circuit 31
The output signal of the AND circuit 32 is “1” The output signal of the AND circuit 32 is “1”
``'', the address set signal AST of ``l'' is output from the address set circuit 30 to the register 11, and therefore the address signal A from the control section 2 is output to the register 11.
DD will be imported.

The memory unit 1 reads the fetch data from the RAM 12 according to the processing destination address taken into the register 11, and sends it to the control unit 2. The control unit 2 performs an error check on this fetch data, and if there is an error, it is corrected.

After that, the control unit 2 controls the memory unit 1 to
along with the access request signal REQ, command signal CMD, and patrol designation signal PAT.

Send the store data that has undergone corrections, etc. However, unlike the conventional method, an address signal ADD specifying the write destination address is not sent at this time.

When the memory unit l receives these signals, the address set circuit 30 determines the access request signal REQ, the command signal CMD, and the patrol designation signal PAT, and thereby determines that it is in the above-mentioned patrol processing store mode, Address set signal AST output to register 11
is set to “0”.

As a result, the address information previously held in register 11 (i.e., the read address during patrol processing)
is held as it is, and using this as a write address, the patrol-processed store data sent from the control unit 2 is written to the RAMI 2.

As a result of the above, it is only necessary to send the processing destination address once from the control section 2 to the memory section 1 during patrol processing.

Various modifications are possible in implementing the invention. For example, in the above-mentioned embodiment, a 1-bit patrol designation signal PAT was newly provided in addition to the command signal CMD, but this patrol designation signal FA
T can also be included in the command signal CMD. For example, the command signal CMD may be made into 2 bits to specify four modes: normal read/write and patrol read/write.

[Effects of the Invention] As explained above, according to the present invention, the process destination address was sent twice from the control unit to the memory unit during patrol processing in the past, but with the present invention, it can be sent only once. Therefore, the probability that the sent processing destination address information changes due to noise from the outside world is reduced to 1/2, and the RAM
12, the risk of data corruption occurring can be reduced, which greatly contributes to improving the reliability of the storage device.

Furthermore, by configuring the control unit so that it only needs to send address information once during patrol processing, it is possible to reduce the hardware scale.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a block diagram showing a circuit configuration on the memory side in an embodiment of the present invention; FIG. 3 is a diagram showing a processing sequence during patrol processing in the embodiment; FIG. 4 is a diagram illustrating a schematic configuration of a storage device, and FIG. 5 is a diagram illustrating a processing sequence during conventional patrol processing. In the figure, 1...Memory unit 2...Control unit 4...Central processing unit (CPU) 11.21...Address register 12...Random access memory (RAM) 30...
・Address set circuit 31...NAND circuit 32...AND recall REQ...Access request signal CMD...Command signal FAT...Patrol designation signal ADD...Address signal SD...Store data FD ... Fetch data conventional patrol processing Figure 5

Claims (1)

[Scope of Claims] 1. A memory section (51) having a register (53) that holds address information, and a control section (52) that interfaces and controls access between the memory section (51) and an external device (55). ) and configured such that access from the external device (55) to the memory unit (51) is performed via the control unit (52), the control unit (52) A means (54) is provided for sending a patrol designation signal (PAT) specifying patrol processing at the time of processing to the memory unit (51), and the memory unit (51) receives the patrol designation signal (PAT).
a storage device configured to hold the read address for patrol processing received from the control unit (52) in the register (53) until the time of patrol write processing and use it as a write address for patrol processing. address control device during patrol.