JPH03263109A - Mounting structure of computer - Google Patents
Mounting structure of computerInfo
- Publication number
- JPH03263109A JPH03263109A JP2060955A JP6095590A JPH03263109A JP H03263109 A JPH03263109 A JP H03263109A JP 2060955 A JP2060955 A JP 2060955A JP 6095590 A JP6095590 A JP 6095590A JP H03263109 A JPH03263109 A JP H03263109A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- power source
- layer
- power supply
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000000956 alloy Substances 0.000 claims abstract description 6
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 229920001721 polyimide Polymers 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 4
- 239000011810 insulating material Substances 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 23
- 239000000463 material Substances 0.000 abstract description 9
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は計算機の実装構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a computer implementation structure.
従来、複数の半導体素子を高密度に同一基板へ搭載する
計算機の実装構造としては１日経エレクトロニクス６−
１７、Ｎｏ、３７１．Ｐ２５１〜２５２．１７８５に示
されている構造が知られている。この従来構造では、給
電用の多層アルミナセラミック基板上に半導体素子間の
信号伝達用として、ポリイミド系樹脂を絶縁膜とする薄
膜微細多層配線が形成されている。Conventionally, the Nikkei Electronics 6-
17, No. 371. The structures shown in P251-252.1785 are known. In this conventional structure, a thin film fine multilayer interconnection using polyimide resin as an insulating film is formed on a multilayer alumina ceramic substrate for power supply for signal transmission between semiconductor elements.
ところで、計算機用として、実装される半導体素子は年
々高集積化、高速化の傾向にある。これに伴って最近で
は素子当り３０Ｗを越える消費電力の論理素子が開発さ
れてきた。この大消費電力傾向は増々加速し、数年後に
は素子当り１００Ｗを越える半導体素子が開発されるで
あろう。Incidentally, semiconductor devices mounted in computers are becoming more highly integrated and faster each year. Along with this, logic elements with power consumption exceeding 30 W per element have recently been developed. This trend of high power consumption will continue to accelerate, and in a few years, semiconductor devices that can exceed 100 W per device will be developed.
一方、上記従来実装構造では、アルミナセラミックスが
半導体素子への給電用基板として採用しているため、比
抵抗の大きなＷなどの高融点材料を電源層に用いざるを
得ない。また、基板形成プロセス上の制約から、電源層
−層当りの厚さを大きくできず、結局電源層の抵抗を小
さくするには限界がある。給電用基板としての低抵抗化
手段は、電源層の多層化が考えられるが、基板の厚さ方
向へのスルホール抵抗が大きくなり、やはり低抵抗化に
は限界が存在する
このような低抵抗化に限界があるアルミナセラミックス
給電用基板で大電力消費半導体素子に給電する場合、電
圧降下が大きな問題となる。On the other hand, in the conventional mounting structure described above, since alumina ceramics is used as the substrate for power supply to the semiconductor element, a high melting point material such as W having a high specific resistance must be used for the power supply layer. Further, due to constraints on the substrate forming process, it is not possible to increase the thickness per layer of the power supply layer, and there is a limit to reducing the resistance of the power supply layer. A possible means of reducing resistance as a power supply board is to make the power supply layer multilayered, but the through-hole resistance increases in the thickness direction of the board, and there is still a limit to how low resistance can be achieved. When power is supplied to a large power consuming semiconductor element using an alumina ceramic power supply substrate that has a limit, voltage drop becomes a major problem.
本発明の目的は、大電力消費半導体素子への給電に対し
、電圧降下がほとんど無視できる給電用基板を具備した
実装構造を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a mounting structure equipped with a power supply substrate in which a voltage drop can be almost ignored when power is supplied to a large power consuming semiconductor element.
上記目的を達成するため本発明では、給電用として低抵
抗化が容易なＣｕ、Ａｌ、Ａｕあるいはこれらの合金か
らなる厚板材を電源層とする多層電源基板上に、半導体
素子相互の信号配線を行う多層薄膜微細配線基板を形成
した基板を用いる。In order to achieve the above object, the present invention provides signal wiring between semiconductor elements on a multilayer power supply substrate whose power supply layer is a thick plate material made of Cu, Al, Au, or an alloy thereof, which can easily reduce the resistance for power supply. A substrate on which a multilayer thin film fine wiring board is formed is used.
半導体素子と該基板との接続には、柔構造リードを用い
る。Flexible leads are used to connect the semiconductor element and the substrate.
多層電源基板は、上記したようにＣｕ、ＡＩ。 The multilayer power supply board is made of Cu and AI as described above.
Ａｕあるいはこれらの合金材料からなる厚板の電源層か
ら構成されているため、材料自身の比抵抗が小さく、板
厚を厚くすれば、電源層の低抵抗化は容易である。さら
にこれを基板の構造材として用いることが可能である。Since the power supply layer is made of a thick plate made of Au or an alloy thereof, the resistivity of the material itself is low, and the resistance of the power supply layer can be easily reduced by increasing the thickness of the plate. Furthermore, it is possible to use this as a structural material for a substrate.
多層電源基板上に形成されたＣｕポリイミド系からなる
多層薄膜微細配線基板は、基板上に搭載される半導体素
子相互の信号配線を行うことができる。A multilayer thin film fine wiring board made of Cu polyimide formed on a multilayer power supply board can perform signal wiring between semiconductor elements mounted on the board.
半導体素子を基板に接続する柔構造リードは、主にＳｉ
材料からなる熱膨張率の小さな半導体素子と熱膨張率の
大きな基板と熱膨張差を吸収し。Flexible structure leads that connect semiconductor elements to substrates are mainly made of Si.
It absorbs the difference in thermal expansion between a semiconductor element made of materials with a small coefficient of thermal expansion and a substrate with a large coefficient of thermal expansion.
接続寿命を確保する作用がある。It has the effect of ensuring the connection life.
以下、本発明の実施例を第１図及び第２図により説明す
る。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第１図及び第２図は本発明の実装構造の概念図である。1 and 2 are conceptual diagrams of the mounting structure of the present invention.
第１図において、半導体素子ＩＣは多層電源基板Ｌｖ及
び多層薄膜微細配線基板Ｌｓからなる基板に柔構造リー
ドＣｆを介してはんだＣｓで接続されている。多層電源
基板Ｌｖは、接地を含む複数の異なる電位を供給する電
源層ｖ１〜Ｖ。In FIG. 1, a semiconductor element IC is connected to a substrate consisting of a multilayer power supply board Lv and a multilayer thin film fine wiring board Ls via a flexible structure lead Cf with solder Cs. The multilayer power supply board Lv has power supply layers v1 to V that supply a plurality of different potentials including ground.
（４とは限らない）で構成され電源層Ｖ□〜ｖ４間はポ
リイミド系の有機絶縁材料で互いに絶縁されている。ま
た各電源層はＣｕ、ＡＩ、Ａｕあるいはこれらの合金材
料の厚板で作られ電気抵抗を十分小さくかつ構造的に十
分な強度が得られるようにしである。半導体素子ＩＣ相
互の信号配線は電源基板Ｌｖ上に形成された多層薄膜微
細配線基板Ｌｓで行うが、これは接地層Ｇ１．Ｇ２間に
縦横方向に接続する信号層Ｓｘ、Ｓｙから構成されてお
り、多層電源基板Ｌｖと同様の材料系から成る。(not limited to 4), and the power layers V□ to v4 are insulated from each other with a polyimide-based organic insulating material. Further, each power supply layer is made of a thick plate of Cu, AI, Au, or an alloy of these materials, so as to have sufficiently low electrical resistance and sufficient structural strength. Signal wiring between the semiconductor devices IC is performed on a multilayer thin film fine wiring board Ls formed on the power supply board Lv, which is connected to the ground layer G1. It is composed of signal layers Sx and Sy connected vertically and horizontally between G2, and is made of the same material system as the multilayer power supply board Lv.
基板に対してこのような材料系を採用したとき。When such a material system is adopted for the substrate.
基板と半導体素子ＩＣとの間には無視出来ないほどの熱
膨張差が生じるため、これを吸収し半導体素子ＩＣの接
続寿命を確保するため微細かつ水平垂直のどの方向に対
しても変位可能な柔構造り−ドＣｆを介してはんだＣｓ
により接続する。Since there is a non-negligible difference in thermal expansion between the substrate and the semiconductor device IC, in order to absorb this difference and ensure the connection life of the semiconductor device IC, it is possible to displace minutely and in any horizontal or vertical direction. Solder Cs via flexible structure wire Cf
Connect by.
その詳細構成を第３図により説明する。第３図は柔構造
リードＣｆ部及びその周辺の拡大図である。第３図（、
）は柔構造リードＣｆであり、らせん形状をしている。Its detailed configuration will be explained with reference to FIG. FIG. 3 is an enlarged view of the flexible structure lead Cf portion and its surroundings. Figure 3 (,
) is a flexible structure lead Cf, which has a spiral shape.
第３図（ｂ）にはその接続状況を示した。柔構造リード
Ｃｆは多層薄膜微細配線基板Ｌｓに形成されたスルホー
ルＴＨに基板接続部Ｃｆ、が固定されている。柔構造リ
ードＣｆは基板接続部Ｃｆ１を除き水平及び垂直方向に
自由に変形可能な構造をしている。柔構造リードの自由
端Ｃｆ、ははんだＣｓにより半導体素子ＩＣに接続され
ている。なお、この基板への外部からの電源供給及び信
号入出力は基板裏面に設けられた電源端子Ｐｖ及び信号
端子Ｐｓで行う。FIG. 3(b) shows the connection status. The flexible structure lead Cf has a substrate connecting portion Cf fixed to a through hole TH formed in the multilayer thin film fine wiring substrate Ls. The flexible structure lead Cf has a structure that can be freely deformed in the horizontal and vertical directions except for the board connection part Cf1. The free end Cf of the flexible structure lead is connected to the semiconductor element IC by solder Cs. Note that external power supply and signal input/output to this board are performed through a power terminal Pv and a signal terminal Ps provided on the back surface of the board.
第２図は本発明に図る他の実施例を示す概念図である。FIG. 2 is a conceptual diagram showing another embodiment of the present invention.
その基本的構成は第１図に示したものと同じであるが、
電源供給を裏面からではなく多層電源基板Ｌｖの側面か
ら電源ケーブルｖ４′（電源層に対応して設ける）をボ
ルト・ナツトでＢで接続する。こうすることにより基板
裏面の端子密度を減らすことができる。Its basic configuration is the same as shown in Figure 1, but
Power is supplied not from the back side but from the side surface of the multilayer power supply board Lv by connecting a power cable v4' (provided corresponding to the power supply layer) with a bolt and nut at B. By doing this, the terminal density on the back surface of the board can be reduced.
本発明によれば、従来のセラミックス給電用基板では、
内臓されている導体のシート抵抗が約６ｍＱ”であるの
に対し、本発明の多層電源基板では約０．０２ｍＱ’
（厚さ１ｍｍの銅板を使用）を得ることができ１／３０
０に抵抗を小さくできる。これにより電圧降下がほとん
ど無視できる多層電源基板を具備した実装構造を得るこ
とができるので、１００Ｗを超える大電力消費半導体素
子の搭載が可能となり、将来の大形高速計算機が実現で
きる。According to the present invention, in the conventional ceramic power supply substrate,
While the sheet resistance of the built-in conductor is approximately 6 mQ'', the multilayer power supply board of the present invention has a sheet resistance of approximately 0.02 mQ'.
(using a copper plate with a thickness of 1 mm) can obtain 1/30
The resistance can be reduced to 0. This makes it possible to obtain a mounting structure equipped with a multilayer power supply board in which the voltage drop is almost negligible, making it possible to mount semiconductor elements with large power consumption exceeding 100 W, and realizing future large-scale high-speed computers.
第１図及び第２図は本発明の実施例を示す実装構造の概
念図、第３図は柔構造リードの接続概念図である。
ＩＣ−ｍ−半導体素子、Ｌｓ−−一多層薄膜微細配線基
板、Ｌｖ−−一多層電源基板、Ｃｆ−−一柔構造リード
第１図
ＩＣ・・・半導体素子
ＣＢ・・・はんだ
Ｃｆ・・・柔構造リード
Ｌｓ・・・多層薄膜微細配線基板
Ｌｖ・・・多層電源基板
Ｇ、、Ｇ、・・・接地層
Ｓｘ、Ｓｙ・・・信号層
ｖ、 、 ｖ、 、 ｖ２． ｖ、・・・電ＰＪＮＰｓ
・・・信号端子
Ｐｒ・・・電源端子
第２図
第３図
（ａ）
（ｂ）
Ｐｓ
Ｃｆ・・・柔構造リード
Ｃｆよ・・・基板接続部
Ｃｆ、・・・自由端
ＴＨ・・・スルホール
Ｐｓ・・・信号端子1 and 2 are conceptual diagrams of a mounting structure showing an embodiment of the present invention, and FIG. 3 is a conceptual diagram of connection of flexible structure leads. IC-m--semiconductor element, Ls--1 multilayer thin film fine wiring board, Lv--1 multilayer power supply board, Cf--1 flexible structure lead Figure 1 IC...Semiconductor element CB...Solder Cf. ...Flexible structure lead Ls...Multilayer thin film fine wiring board Lv...Multilayer power supply board G, , G,...Ground layer Sx, Sy...Signal layer v, , v, , v2. v,...den PJNPs
...Signal terminal Pr...Power terminal Fig. 2, Fig. 3 (a) (b) Ps Cf...Flexible structure lead Cf...Board connection part Cf,...Free end TH... Through hole Ps...signal terminal
Claims (2)
よりなる多層電源基板上に多層薄膜配線基板を形成し、
これに柔構造リードを介して複数の半導体素子を接続し
たことを特徴とする計算機の実装構造。1. A multilayer thin film wiring board is formed on a multilayer power supply board made of a low resistance thick plate conductive material with an organic insulating material interposed therebetween.
A computer mounting structure characterized in that a plurality of semiconductor elements are connected to this via flexible structure leads.
ポリイミド系樹脂を、低抵抗厚板導電材料としてＣｕ、
Ａｌ、Ａｕあるいはこれらの合金を用いたことを特徴と
する特許請求の範囲第１項記載の計算機の実装構造。2. Polyimide resin is used as the organic insulating material constituting the multilayer power supply board, Cu is used as the low resistance thick plate conductive material,
The computer mounting structure according to claim 1, characterized in that Al, Au, or an alloy thereof is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2060955A JPH03263109A (en) | 1990-03-14 | 1990-03-14 | Mounting structure of computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2060955A JPH03263109A (en) | 1990-03-14 | 1990-03-14 | Mounting structure of computer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03263109A true JPH03263109A (en) | 1991-11-22 |
Family
ID=13157326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2060955A Pending JPH03263109A (en) | 1990-03-14 | 1990-03-14 | Mounting structure of computer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03263109A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208024B1 (en) * | 1996-12-12 | 2001-03-27 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation using restraining straps |
| US8552606B1 (en) | 2012-03-29 | 2013-10-08 | Samsung Electro-Mechanics Co., Ltd. | Spindle motor |
-
1990
- 1990-03-14 JP JP2060955A patent/JPH03263109A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208024B1 (en) * | 1996-12-12 | 2001-03-27 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation using restraining straps |
| US6362520B2 (en) | 1996-12-12 | 2002-03-26 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation using restraining straps |
| US8552606B1 (en) | 2012-03-29 | 2013-10-08 | Samsung Electro-Mechanics Co., Ltd. | Spindle motor |
| US8729757B2 (en) | 2012-03-29 | 2014-05-20 | Samsung Electro-Mechanics Co., Ltd. | Spindle motor |
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