JPH03262158A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To enable pixels to be scanned at a high speed by a method wherein a selection transistor is constituted in such as state that a prescribed voltage is given to its gate electrode to enable it to be turned ON or OFF depending on whether an interband tunneling phenomenon occurs on the surface of a drain region just under a gate or not. CONSTITUTION:A reset pulse is given to the overflow gate 56 of a transistor T1 through the intermediary of an overflow gate line l1 from an overflow gate terminal POG, the potential of an N<+> source region 22 which forms the photodiodes PD of all pixels 46 is set to a preset potential, and then a preset charge is determined in quantity. In this state, when light is made to impinge on a PD for a certain integral time, an optical signal charge is stored in the N<+> source region 22. The charge stored in the pixels 46 are read out through such a way that a horizontal scanning circuit 41 and a vertical scanning circuit 42 are made to output scanning pulses respectively, a vertical signal line l<3> is selected, and the erased selection transistors T2 whose threshold voltages are set to Vth2 are selectively turned ON or OFF in the pixels 46 through a horizontal selection line L2 so as not to enable a write to take place. By this setup, the high speed scanning of pixels can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device capable of high-speed scanning of pixels.

[Conventional technology]

3 and 4 are a circuit configuration diagram showing the basic configuration of a conventional MO8 type solid-state imaging device, and a cross-sectional view showing the cross-sectional structure of one pixel.

In FIG. 3, 41 is a horizontal scanning circuit, 42 is a vertical scanning circuit, 44 is a horizontal switch MO3) transistor, 45 is an integrating circuit for detecting a read signal, VS is a video signal output line,
■ is the video output, POD is the UT overflow train terminal, PoG is the overflow gate terminal, Jl! 1 is the overflow K-1 line, p
2 is an Ap horizontal selection line, p3 is an Ap vertical signal line, and ρ4 is an overflow drain line. Further, 46 indicates a component for one pixel, and is composed of a photodiode PD and transistors T], , and T2 each having an overflow gate and an MO8 transfer gate.

As shown in FIG. 4, each pixel 46 has three N+ diffusion regions 51 to 53 formed in the upper layer of a P-type Si substrate 50. As shown in FIG.

5 on the P-type St substrate 50 between the N+ diffusion regions 5], , 52.
An overflow gate 56 made of polysilicon is formed through the 102 film 54. Further, a transfer gate 57 made of polysilicon is formed on the P-type St substrate 50 between the N+ diffusion regions 52 and 53 with an S102 film 55 interposed therebetween. The transistor T1 is formed by the N+ diffusion region 51.52 and the overflow gate 56, and the transistor T1 is formed by the N+ diffusion region 52.53 and the transfer gate 57.
2, a photodiode PD is formed by a pn junction between an N+ diffusion region 52 and a P-type Si substrate 50. Also,
N+ diffusion region 51 overflow gate 56. The transfer gate 57 and the N+ diffusion region 53 are connected to the overflow drain line 114, the overflow gate 111, the Aρ horizontal selection line p2, and the AN vertical signal line g3, respectively.

Further, the transistor T2 having the transfer gate 57 functions to prevent the charge photoelectrically converted by the photodiode PD from flowing to the AI1 vertical signal line ρ3 by being turned off. Transistor T] overflow gate 5
6. The N+ diffusion regions 51 are respectively connected to an overflow gate terminal POG' and an overflow drain terminal PoD, thereby performing a presetting operation of the photodiode PD as described later. Furthermore, when the photodiode PD is irradiated with strong light during imaging, it also serves as an overflow drain that sweeps out the charge overflowing from the photodiode PD and suppresses blooming.

In such a configuration, the overflow gate terminal P
. 0 to the overflow gate 56 of the transistor T1 via the overflow gate line p1, the potential of the N+ diffusion region 52 forming the photodiode PD of all pixels 46 is set to a preset potential, and the amount of charge in the preset state is set. decide.

In this state, when light is incident on the photodiode PD for a certain integration period Ti, the photo-excited optical signal charges are accumulated in the N+ diffusion region 52, and the potential of the N+ diffusion region 52 decreases. This operation is based on "IEEE J.

5o11d-3tate C1rcuits, Vol.
5C-2, no, 12 p, 65-73Sept 19
G. P. Weckler's paper “0p
eration of p-n juncHon ph
otodetectors in a photon
P
I (Photo.

n-Flux Integration) mode.

In this way, the readout of the charge of each pixel 46 accumulated in the N+ diffusion region 52, that is, the imaging is carried out by the horizontal scanning circuit 4.
1 and the vertical scanning circuit 42 respectively to select the All vertical signal line ρ3 and to select the selection transistor T of each pixel 46 via the AN horizontal selection line ρ2.
2 by selectively turning on/off each pixel 46.
and finally the video signal V. This is done by reading out the information as Uo.

[Problem to be solved by the invention]

The conventional solid-state imaging device is configured as described above, and the selection transistor T2 has a MO8FET structure, so when miniaturizing it, there is a problem that short channel effects such as generation of hot electrons and induction of bunch-through phenomenon occur. There was a point.

Further, since the switching operation of the selection transistor T2 is not very fast, there is a limit to the scanning speed of the pixel 46. Therefore, when capturing an image of a subject with a high spatial frequency, such as a fast-moving object, there is a problem in that the number of pixels cannot be increased, and therefore the image cannot be captured with sufficient resolution.

On the other hand, as a MOSFET with high-speed switching operation and no short channel effect, "IEEE International
ational Electron Devices
Meeting, Digest.

f Technical Papers, pp402
E of -405°゛, Mr. TAKEDA et al.'s paper "^ban
d to band tunneling MOS d
Interband tunneling MO described in evice J
There is a 3FET (hereinafter referred to as rB''1-M03FETj).

FIG. 5 is a cross-sectional view of the B11-MOSFET.

As shown in the figure, a P+ drain region 11 and an N+ source region 12 are formed on the surface of a P substrate 10, respectively. An oxide film 13 with a thickness of 10 to 15 nm that allows tunneling is formed from the center of the P+ drain region 11 to the end of the N+ source region 12.
A gate electrode 14 is formed on 3. Also, a P+ drain region 11, a gate electrode 14 and an N+ source region 1
2 are drain terminals 15. It is connected to the gate terminal 16 and the source terminal 17.

In addition, in FIG. 5, Lo■ is between the gate electrode 14 and P+
A region overlapping with the drain region 11 (hereinafter referred to as "gate")
This is called the "drain overlap region." ) length (less than or equal to).

It is called "gate and drain overlap length." ), and L8. is P+ drain region 11 and N+ source region 1
2 (hereinafter referred to as "drain-source length").

In such a configuration, when voltages are applied to the drain terminal 15 and the source terminal 17 so that the source side becomes a high voltage, and a positive voltage is applied to the gate electrode 14 via the gate terminal 16, the P+ drain region 11 and A deep depletion region 10 on the surface of the P− substrate 10 between the N+ source region] 2
As shown in the band diagram of FIG. 6, interband tunneling occurs in the surface region 11a of the P+ drain region 11 in the gate and drain overlap region, and electrons and holes ( h
ole) pairs are generated in the conduction band and single valence band, respectively.

Then, due to space charge conduction, electrons flow into the N+ source region 12 via the depletion region 10a, and holes flow into the P+ drain region 11, so that a current 1 shown in the following equation (1) flows.

I −q−N, ·μ. ff −E (1) In equation (1), Nt is the number of hole-electron pairs, q is the charge element, and μ. 4. is the drain-source length L8. of the depletion region 10a. The effective mobility determined by E is the oxide film 13 in the gate-drain opal-tube region.
is the electric field strength applied to

As described above, current flows through the B11-MOSFET due to the movement of two carriers, so high-speed switching operation is possible. In addition, since the conductivity types of the drain and source are different, and a P+N+ potential barrier is generated between the drain and the first lath, the length LsP between the drain and source is set to 0.
Even if the thickness is reduced to 1 μm or less, the short channel effect does not occur. However, the B2T-MO8FET has never been used as a switching transistor in a solid-state imaging device.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a solid-state imaging device that is composed of selection transistors that do not cause short channel effects even when miniaturized, and that is capable of high-speed pixel scanning. shall be.

[Means to solve the problem]

A solid-state imaging device according to the present invention includes a first conductivity type semiconductor substrate, a photoelectric conversion section formed in the semiconductor substrate, and a part of the photoelectric conversion section formed on the semiconductor substrate, a selection transistor that performs switching of the electrical signal photoelectrically converted by the photoelectric conversion section, and the selection transistor includes a drain region of a first conductivity type selectively formed on the surface of the semiconductor substrate; a second conductivity type source region selectively formed on a surface of a semiconductor substrate; an insulating film formed from above the drain region to an end of the source region and having a thickness that allows tunneling; and the insulating film. It is configured to include a nonvolatile information storage layer that is formed above and performs nonvolatile information storage by trapping carriers, and a gate electrode that is formed on the nonvolatile information storage layer.

[Effect]

In this invention, the selection transistor that performs switching of the electrical signal photoelectrically converted by the photoelectric conversion section is
A predetermined scanning pulse is applied to the gate electrode, and the device is turned on/off depending on whether interband tunneling occurs on the surface of the train region directly under the gate.

〔Example〕

0 Figure 1 shows an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the cross-sectional structure of one pixel of the J solid-state imaging device. The basic configuration of the solid-state imaging device is the same as the conventional example shown in FIG.

As shown in FIG. 1, in each pixel, an N+ diffusion region 51. P+ drain region 21. N+
Source regions 22 are respectively formed. N+ diffusion region 51. An overflow gate 56 made of polysilicon is formed on the P St substrate 20 between the N+ source regions 22 with a 5102 film 54 interposed therebetween.

Further, an SiO2 film 23 having a thickness of 70 to 100 mm is formed from the center of the P+ drain region 21 to the end of the N+ source region 22 to allow tunneling. A SiN film 24 is formed on this SiO2 film 23, and a transfer gate 25 is formed on the 513N4 film 24.

In FIG. 1, Lov is the gate and drain overlap length between the transfer gate electrode 25 and the P+ drain region 21, and LsP is the gate and drain overlap length between the transfer gate electrode 25 and the P+ drain region 21 and the N+ drain region 21.
This is the drain-source length between the source region 22 and the source region 22 .

Then, the transistor T of FIG.
1 to the N+ source region 22. The P+ drain region 21 and the transfer gate 25 form the selection transistor T2 shown in FIG. That is, the transistor T2 having the transfer gate 25 becomes a B2T, -MNO3FET, and its operation is such that a predetermined voltage is applied to the transfer gate 25, and the P+ drain region 2 in the drain gate overlap region is
Band-to-band tunneling (hereinafter, this phenomenon is referred to as "horizontal tunneling") occurs in the surface region 21H of 1.

). In addition, as will be described in detail later, the threshold voltage of the selection transistor T2 can be changed between Vth1 and Vth2 by write and erase operations. Note that 20a is a deep depletion region. Further, a photodiode PD shown in FIG. 3 is formed by a PN junction between the N+ source region 22 and the PSi substrate 20. and N+] 1 2 diffusion region 51 . Overflow gate 56. Transfer gate 25 and P+ drain region 21 are connected to overflow drain line 114 . Overflow gate line Fi, AN
It is connected to the horizontal selection line p2 and the AN vertical signal line, Q3.

Further, when the transistor T2 having the transfer gate 25 is turned off, the charge photoelectrically converted by the photodiode PD is transferred to the AN vertical signal line l! 3. It works to prevent leakage. The overflow gate 56 and N+ diffusion region 51 of the transistor T1 are connected to an overflow gate terminal PoG and an overflow drain terminal PoD, respectively, thereby performing a presetting operation of the first diode PD as described later. Furthermore, when the photodiode PD is irradiated with strong light during imaging, it also serves as an overflow drain that sweeps out the charge overflowing from the photodiode PD and suppresses blooming.

The imaging operation of the solid-state imaging device having such a configuration will be described.

First, a reset pulse is applied from the overflow gate terminal PoG to the overflow gate 56 of the transistor T1 via the overflow gate line ρ1, and all pixels 46
N+ source region 22 forming the photodiode PD of
The potential of is set as a preset potential, and the amount of charge in the preset state is determined.

When light is incident on the photodiode PD for a certain integration period Ti in this state (hereinafter referred to as the "imaging preparation state"), the photoexcited optical signal charge is accumulated in the N+ source region 22, and the N+ source region 22 is Potential decreases. As described in the conventional example, this operation is equivalent to the PFl mode in a normal MO3 type solid-state image sensor.

To read out the charges of each pixel 46 accumulated in the N+ source region 22 in this way, the horizontal scanning circuit 41 and the vertical scanning circuit 42 output scanning pulses, select the Aρ vertical signal line p3, and select the Aρ vertical signal line p3. horizontal selection line,
This is done by selectively turning on/off the selection transistor T2, which has been erased and whose threshold voltage is set to Vth2, in each pixel 46 via Q2 so that writing does not occur. At this time, since the selection transistor T2 is turned on/off by the movement of two carriers by horizontal tunneling, high-speed switching operation is possible. Therefore, in the solid-state imaging device of this embodiment, which scans pixels by turning on/off the selection transistor T2, it is possible to scan pixels at high speed, and even objects with a high spatial frequency such as fast-moving objects can be imaged with sufficient resolution. I can do it.

In addition to the above-described imaging operation, image information of each pixel 46 is written into the selection transistor T2 as described below.

First, in the imaging preparation state, when light is incident on the photodiode PD for a certain integration period Ti, as in the imaging operation, the optically excited optical signal charge is accumulated in the N+ source region 22,
The potential of N+ source region 22 decreases.

After that, when the drain side of the selection transistor T2 is set to a sufficiently lower potential than the source side and a predetermined positive high voltage is applied to the transfer gate 25, the surface of the PSt substrate 20 between the P+ drain region 2 and the N+ source region 22 is deep depletion region 2
0a is formed. Then, P+ directly below the transfer gate 25
Horizontal tunneling occurs in the surface region 21a of the drain region 21. At this time, the amount of horizontal tunneling generated also changes depending on the potential of the N+ source region 22, which determines the amount of photoelectric conversion of the photodiode PD. Thereafter, electrons flow into the N+ source region 22 via the depletion region 20a due to space charge conduction, and holes flow out toward the P+ drain region 21.

Furthermore, since the write voltage is high and the electric field strength applied to the SiO2 film 23 is sufficiently high, tunneling occurs in the SiO2 film 2B, and some of the electrons generated by horizontal tunneling tunnel through the 5IO2 film 23, and the SiO2
4 in the membrane 24 (hereinafter, this phenomenon will be referred to as "vertical tunneling"). The trapped charges in the Si3N4 film 24 raise the threshold voltage of the selection transistor T2 from the erased state V□h2.

The amount of increase in the threshold voltage is proportional to the electric field strength and the amount of horizontal tunneling, and the charge strength is
The lower the potential of the N+ source region 22, which determines the surface potential of the pixel 46, the higher the potential. Therefore, the threshold voltage of the selection transistor T2 increases in proportion to the amount of photoelectric conversion by the photodiode PD, which is image information of the pixel 46. In this way, pixel 4
6 image information is written into the selection transistor T2. The highest threshold level of the selection transistor T1 due to this writing is Vth■.

FIG. 2 is a band diagram showing the above-described horizontal tunneling and vertical tunneling. FIG. 4(a) shows a case where the vertical tunneling is modified FN) tunneling, and FIG. 6(b) shows a case where the vertical tunneling is direct tunneling. In Figure 2, TNl represents horizontal tunneling, and TN
2 indicates vertical tunneling. Also, φ, φ
are unique values determined by the 112 P+ drain region 21 and the 5t3N4 film 24, respectively, and Vox' is the potential applied from the front surface to the back surface of the S I O2 film 23.

Also, φ ′ is φB′ mi φ −φ −V ′ ...(4)1
It is an index defined as 1 12 0X.

When the index φ'>0, as shown in FIG. 2, modified FN) tunneling occurs as horizontal tunneling, and when φ'B≦0, direct tunneling occurs as horizontal tunneling.

The image information written to the selection transistor T2 is read out as follows.

First, the transistor T1 is turned on by applying a predetermined voltage from the overflow gate PoG at a time corresponding to each retrace period of horizontal scanning, and a predetermined voltage is applied from the overflow drain terminal PoD to the N+ diffusion region which is the drain of the transistor T1. 51. Then, the source of the transistor T1 and the selection transistor T
The N+ source region 22, which is also the source of the photodiode PD, is supplied with a level of charge that is negligible, which is the charge conversion amount of the photodiode PD.

Thereafter, a scanning pulse of a voltage level (vtl, 1 or more) that does not cause writing, that is, vertical tunneling, is sequentially applied to the transfer gate 25 of the selection transistor T2 of each pixel 46 to cause horizontal tunneling. By doing so, the selection transistor T2 is turned on, and an amount of charge corresponding to the threshold voltage of the selection transistor T2 is transferred to the P+ drain region 21. That is, the selection transistor T
If the threshold voltage of transistor T2 is high, the amount of charge transferred to P+ drain region 21 will be small, and if the threshold voltage of transistor T2 is low, the amount of charge transferred to P+ drain region 21 will be large. Therefore, the video output V has a negative correlation with the photoelectric conversion amount of the photodiode PD during writing. Ul
is read out via the AN vertical signal line β3. Moreover, since the switching of the selection transistor T2 is performed by horizontal tunneling, the readout operation can be performed at high speed during imaging.

On the other hand, to erase the image information stored in the selection transistor T2, a negative high voltage is applied to the transfer gate 25, and the Si3N4
The electrons trapped in the film 24 are transferred to the PSt substrate 20.
This is done by daytrapping in the direction and lowering the threshold voltage to Vlhl. After performing this erasing operation, the above-described imaging operation can be performed thereafter.

As described above, since the selection transistor T2 is turned on and off during imaging and readout by horizontal tunneling, high-speed switching operation is possible.

In addition, the conductivity types of the drain and source of the selection transistor T2 are different, and a P''N+ potential barrier is generated between the drain and source, so the length sP between the drain and source of the selection transistor T2 should be set to 0.1 μm or less. Even if miniaturization is performed, the short channel effect does not occur. Therefore, the number of pixels can be increased by miniaturization.

In this embodiment, in order to provide the selection transistor T2 with a non-volatile memory function, the MNO8 structure is used, but the structure is not limited to this, and floating gate MO3FET structure, M
ON OS (Metal Oxide NlLr1
It may be realized by other structures such as a de Oxide Sem1conductor structure.

〔Effect of the invention〕

90 As explained above, according to the present invention, the selection transistor that performs switching of the electrical signal photoelectrically converted by the photoelectric conversion section applies a predetermined voltage to its gate electrode, and It turns on/off depending on whether interband tunneling occurs or not.

Therefore, the switching operation of the selection transistor becomes faster, and a solid-state imaging device having this selection transistor can perform high-speed scanning of pixels. In addition, since the conductivity types of the drain region and source region of the selection transistor are different, the short channel effect does not occur in this selection transistor due to the PN barrier that occurs between the two regions, making it possible to increase the number of pixels through miniaturization. It becomes possible.

Furthermore, a predetermined high voltage is applied to the gate electrode to generate band-to-band tunneling on the surface of the drain region directly under the gate electrode, and electrons generated by the band-to-band tunneling are tunneled into the insulating film to form a non-volatile information storage layer. Since image information can be written by trapping it inside, non-volatile information storage can be achieved.

In addition, readout is performed by applying a predetermined readout voltage to the gate electrode and causing band-to-band tunneling on the surface of the drain region directly under the gate electrode.
The switching operation becomes faster, and the readout operation of stored image information can be performed at higher speed.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the cross section of one pixel of a solid-state imaging device which is an embodiment of the present invention, FIG. 2 is a band diagram showing the write operation of the selection transistor T2 shown in FIG. 1, and FIG. A circuit diagram showing the basic configuration of a conventional solid-state imaging device, FIG. 4 is a sectional view showing a cross section of one pixel of a conventional solid-state imaging device, FIG. 5 is a sectional view showing a B2T-MOSFET, and FIG. 5 is a band diagram showing the operation of the B2T-MOSFET shown in FIG. 5. FIG. In the figure, 20 is a PSt substrate, 21 is a P+ drain region, 22 is an N+ source region, 23 is a Sto film,
24 is a 513N4 film, and 25 is a transfer gate 1 2 . Note that the same symbols in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A semiconductor substrate of a first conductivity type, a photoelectric conversion section formed in the semiconductor substrate, and a photoelectric conversion section formed on the semiconductor substrate, including a part of the photoelectric conversion section, A solid-state imaging device including a selection transistor that performs switching of a converted electrical signal, the selection transistor comprising: a drain region of a first conductivity type selectively formed on the surface of the semiconductor substrate; and a drain region of a first conductivity type selectively formed on the surface of the semiconductor substrate. a second conductivity type source region selectively formed in the drain region; an insulating film formed from above the drain region to an end of the source region and having a thickness that allows tunneling; and on the insulating film. What is claimed is: 1. A solid-state imaging device comprising: a nonvolatile information storage layer that stores nonvolatile information by trapping carriers; and a gate electrode formed on the nonvolatile information storage layer.