JPH0325967B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a PLL (phase-locked closed loop) synthesizer device with a frequency setting function, and particularly relates to a PLL (phase-locked closed loop) synthesizer device with a frequency setting function.
This invention relates to a frequency setting method for a PLL synthesizer device used in a wireless device for which only 2 channels are approved.

[Conventional technology]

FIG. 5 shows the configuration of the main parts of a PLL synthesizer device with a frequency setting function as an example of a conventional type. In the figure, 51 is a microprocessor consisting of an IC (integrated circuit), and this microprocessor 51 has a ROM (read-on memory).
52 is externally connected, and this ROM 52 stores in advance a program for operating the microprocessor 51 and frequency data corresponding to all channels. Reference numeral 53 is a keypad including a numeric keypad, etc., and is used to specify a channel, that is, frequency data to the microprocessor 51. Reference numeral 54 denotes a controller consisting of an IC, which operates an internal frequency divider (not shown) based on frequency data Df from the microprocessor 51.
The frequency division number of the oscillator is changed, thereby controlling the DC voltage applied to the next-stage voltage-controlled oscillator 55 to control the oscillation frequency to a set value. Note that the output signal of the voltage controlled oscillator 55 is fed back to the controller 54, forming a PLL circuit. Further, an R/S switching signal for switching between reception (R) mode and transmission (S) mode is input to the microprocessor 51.

To set the frequency in the conventional type shown in FIG.
52. With this, ROM5
2 outputs frequency data corresponding to that channel in the form of a parallel signal, and is supplied to the controller 54 via the microprocessor 51 as frequency data Df. The controller 54 is
The frequency division number is changed based on this frequency data Df,
The DC voltage to the voltage controlled oscillator 55 is controlled to control the oscillation frequency to a set value.

[Problem that the invention seeks to solve]

In the conventional frequency setting method described above, as the number of channels increases, the external ROM 5
It is necessary to increase the memory capacity of the microprocessor 51 and the ROM 52, and the number of connection bit lines, that is, the number of terminals, between the microprocessor 51 and the ROM 52 also increases, so the overall space occupied by the microprocessor 51, ROM 52, etc. increases. This causes the problem of an increase in the size of the frequency data transmitting unit and, eventually, an increase in the scale of the entire device, resulting in an increase in cost. Furthermore, since the microprocessor 51 is involved in the operation when frequency data is read from the ROM 52, there arises the problem that a burden is placed on the functions of the microprocessor 51 itself.

On the other hand, the current system is applied to devices that can use a very large number of channels, so for example, it can be applied to devices that are licensed for only a small number of channels (1 to 2 channels) within a wide usable frequency band. On the other hand, if the current method is applied, the waste of space occupied by the external ROM 52 becomes more noticeable.

The present invention was created in view of the problems with the conventional type described above, and provides a PLL synthesizer device with a frequency setting function that reduces the functions of a microprocessor, and enables cost reduction and device size reduction. It is intended to.

[Means for solving problems]

As shown in the principle block diagram of FIG. 1, according to the present invention, a first predetermined number of clocks or a second predetermined number of clocks are activated in response to a signal PTT selectively instructing a receiving mode and a transmitting mode. outputs the clock CK of the first predetermined number or the second clock CK.
strobe signal after outputting a predetermined number of clocks.
A microprocessor 1 that outputs the STB and respective frequency data at the time of reception and transmission are arranged and stored in advance in order, and the frequency data is transmitted from the microprocessor to a first predetermined number or a second predetermined number. Programmable bits are read out serially one bit at a time in response to the clock of
ROM2 and the data Df read from the programmable ROM are temporarily held for a predetermined number of bits,
A PLL synthesizer device with a frequency setting function is provided, characterized in that it includes data output control means 3 for setting internally held data as frequency data in response to the strobe signal.

[Effect]

The microprocessor 1 sends a first predetermined number of clocks or a second predetermined number of clocks to the PROM 2.
When CK is supplied, PROM2 outputs clock CK.
Frequency data Df is read out serially one bit at a time according to the number of data output control means 3.
be taken in. Since the data output control means 3 can temporarily hold only a predetermined number of bits, when data exceeding the predetermined number of bits is fetched, the data becomes invalid sequentially starting from the first data bit fetched. That is, the data output control means 3
Only the most recently fetched data of a predetermined number of bits is temporarily held, and this held data is set as frequency data when the strobe signal STB is output from the microprocessor 1.

As described above, the device of the present invention makes it possible to read frequency data from the PROM 2 by changing the number of clocks CK supplied from the microprocessor 1 to the PROM 2 between the reception mode and the transmission mode, and also makes it possible to read the frequency data from the PROM 2. By making it possible to distinguish between data for use and data for transmission, the functions of the microprocessor 1 itself can be suppressed to a minimum, and
By making it possible to take out frequency data serially from the PROM 2, it is possible to reduce the size of the frequency data sending unit, and even the scale of the device, and at the same time to reduce costs.

〔Example〕

FIG. 2 shows the configuration of the main parts of a PLL synthesizer device with a frequency setting function as an embodiment of the present invention. The example shown in FIG. 2 shows the case of a PLL synthesizer device used in a wireless device in which only a small number of channels (two channels in this embodiment) are authorized within a wide usable frequency band.

In the figure, 10 is a microprocessor consisting of an IC, and this microprocessor 10 has a PTT signal (hereinafter referred to as a mode switching signal) for switching between reception mode and transmission mode.
, a power switch on/off (ON/OFF) signal, and a channel switching signal CH are input. Microprocessor 10 to 4
types of signals, namely selection signal SEL, clock signal CK, reset signal RST and strobe signal
STB is output. The selection signal SEL is output in response to the channel switching signal CH.
It is input to PROM21 and 22, and the signal
PROM21 when CH specifies channel 1
is selected, and when signal CH specifies channel 2, PROM 22 is selected. clock signal
CK is output in response to the power ON signal based on the state of the mode switching signal PTT.
21, 22 and the PLL synthesizer controller 30. When the signal PTT specifies the receive mode, the clock signal CK is output and 32 pulses are output, and when the signal PTT specifies the transmit mode, 32 pulses are output. will output 64 pulses. The reset signal RST is output in response to the power ON signal and is input to the PROMs 21 and 22. The strobe signal STB is output when a predetermined number (32 or 64) of clock signals CK are output from the microprocessor 10, and is input to the PLL synthesizer controller 30.

Each PROM 21 and 22 has a capacity of 64 bits, and each PROM has frequency data at the time of reception (assumed D1 to D32) and frequency data at the time of transmission (assumed D33 to D64) arranged in order. These frequency data are serially read out one bit at a time each time the clock CK is input. Note that as the frequency data at the time of transmission, data of a frequency shifted by the reception intermediate frequency from the frequency at the time of reception is used.

The PLL synthesizer controller 30 has a built-in 19-bit shift register (not shown), and the aforementioned PROM 21 is stored in this shift register.
Or data read from 22 is stored sequentially. Therefore, in the process in which data D1, D2, D3, .
...becomes invalid. This controller 30
is a function that responds to the strobe signal STB issued when 32 or 64 clock signals CK are output from the microprocessor 10 and sets the data held in the shift register at that time as frequency data. have.

In addition, the controller 0 changes the frequency division number of an internal frequency divider (not shown) based on the set frequency data, thereby adjusting the DC voltage applied to the next stage voltage controlled oscillator 40. The oscillation frequency is controlled to the set value. Note that the output signal of the voltage controlled oscillator 40 is fed back to the controller 30, forming a PLL circuit. The oscillation frequency signal stabilized in this feedback system is sent to either the receiving section or the transmitting section. Although not shown, selection of either the receiving section or the transmitting section is made in accordance with the state of the mode switching signal PTT.

FIGS. 3 and 4 show the operation timings of the signals of each part in FIG. 2. Hereinafter, the frequency setting operation by the apparatus shown in FIG. 2 will be explained with reference to FIGS. 3 and 4. For the sake of simplicity, it is assumed that channel 1 is specified in advance for the channel switching signal CH.

(1) When setting reception mode (see Figure 3) First, when the power is turned on, the reset signal RST becomes “0”, which makes the PROM21 readable and the clock signal CK changes.
Supplied to PROM21. Data Df is serially read out one bit at a time from the PROM 21 in response to the clock signal CK, but since the number of pulses of the clock signal CK is 32 as described above, the data Df consists of 32 bits D1 to D32. is read out. Of this 32-bit data, D14 to D
32 19-bit data are stored in a shift register within the controller 30. controller 30
Now, in response to the strobe signal STB that is generated when 32 clocks CK are output from the microprocessor 10, this 19-bit data D is output.
14 to D32 are set as frequency data at the time of reception. After the strobe signal STB is output, the reset signal RST becomes "1" and returns to the initial state.

(2) When setting the transmission mode (see Figure 4) First, when the power is turned on, the reset signal RST becomes “0”, which makes the PROM21 readable and the clock signal CK changes.
Supplied to PROM21. In this case, since the number of pulses of the clock signal CK is 64 as described above, the data Df read from the PROM 21 is 64 bits D1 to D64. this
The 64-bit data is sequentially stored in the shift register in the controller 30, and from the time when the data D20 is stored, the data D1, D2,...
becomes invalid. In the controller 30, a strobe signal is generated when 64 clocks CK are output from the microprocessor 10.
In response to STB, the 19-bit data held in the shift register at this time, ie, data D46 to D64, is set as frequency data for transmission. And this strobe signal STB
After the output of , the reset signal RST becomes “1”,
Return to initial state.

As described above, according to the device of this embodiment, the microprocessor 10 outputs the PROM 21 or 22.
Frequency data can be read simply by supplying clock CK to microprocessor 1.
The function of 0 itself can be reduced. Also,
Since the frequency data is taken out serially from the PROM 21 or 22, the frequency data sending section can be downsized, which can even contribute to downsizing the device scale and reducing costs.

In addition, in the device shown in Fig. 2,
Although the case where the data capacity stored in PROM 21 or 22 is 64 bits has been described, the present invention is not limited to this, and the same applies even if the number of bits is different. In addition, two PROMs 21 and 22 were used depending on the number of channels, but for example,
It is also possible to configure it with one piece by using PROM.

〔Effect of the invention〕

As described above, according to the present invention, while reducing the functions of the microprocessor, it is possible to reduce the size of the frequency data sending section, and ultimately to reduce the scale of the device and the cost.

[Brief explanation of the drawing]

Figure 1 shows a PLL with frequency setting function according to the present invention.
2 is a block diagram showing an embodiment of the present invention; FIG. 3 is a timing diagram of the operation of signals in each part of FIG. 2 when setting the reception mode; and FIG. 4 is a diagram showing the setting of the transmission mode. Operation timing diagram of the signals of each part in Fig. 2 at the time, Fig. 5
The figure shows an example of a conventional type with frequency setting function.
FIG. 2 is a block diagram showing the main parts of a PLL synthesizer device. (Explanation of symbols), 1, 10... Microprocessor, 2, 21, 22... PROM, 3... Data output control means, 30... PLL synthesizer controller, PTT... Mode switching signal, CK...
Clock signal, STB...Strobe signal, Df...
...Frequency data.

Claims (1)

[Claims] 1. Outputting a first predetermined number of clocks or a second predetermined number of clocks (CK) in response to a signal (PTT) selectively instructing a reception mode and a transmission mode, respectively; A microprocessor 1 that outputs a strobe signal (STB) after outputting a first predetermined number or a second predetermined number of clocks, and a microprocessor 1 in which frequency data at the time of reception and at the time of transmission are arranged and stored in sequence in advance, and A programmable ROM 2 from which frequency data is serially read out bit by bit in response to a first predetermined number of clocks or a second predetermined number of clocks from the microprocessor, and data (Df) read from the programmable ROM. A PLL synthesizer device with a frequency setting function, comprising data output control means 3 for temporarily holding a predetermined number of bits and setting internally held data as frequency data in response to the strobe signal.