JPH03259638A - Start-stop data speed automatic recognition circuit - Google Patents

Abstract

PURPOSE:To recognize a start-stop data speed automatically by adopting the constitution such that a bit serial character SD sent from an opposite equipment is converted into a parallel data and the converted data is compared with a predetermined reference value. CONSTITUTION:A counter 12 starts counting of a 9.6kHz clock. A shift register 13A converts the input character SD into a parallel data sequentially by using the clock as a shift clock. when four bits in the middle are inverted and the resulting data is inputted to an identification circuit 14A, an output of a flip-flop 15A goes to 8 to inform the detection of a code 21H. When a Q output of the flip-flop 15A goes to 'H', the signal is fed back to in OR gate G2 to close the gate. In this case, since an output of an identification circuit 14B detecting a frequency of 600ps is not the code 21H, the output remains at 'L' as shown in (k) and a Q output of a flip-flop 15B similarly remains at 'L'.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an automatic start-stop data speed recognition circuit that can automatically recognize the start-stop data speed of a partner terminal connected to a commodem, terminal, etc. The purpose is to have the connected terminal transmit a specific character SD related to the data rate in bit serial, and to receive the character SD and control the start of counting operation of the counter. A counter that receives a clock (n clocks) of n times the highest baud rate of serial data and performs a counting operation of n clocks under the control of the counter control circuit, and a character SD is paralleled by using the counter output as a shift clock. A shift register that converts into data, an identification circuit that detects that the output of the shift register matches a predetermined value, and an identification circuit that latches the output of the identification circuit with the output clock of a counter and determines the latched output. It consists of a flip-flop for output.

[Industrial Field of Application] The present invention relates to an automatic start-stop data rate recognition circuit that can automatically recognize the data start-stop speed of a partner terminal connected to a modem, terminal, etc.

The data start-stop speed of the other terminal connected to the modem, terminal, etc. varies. Therefore, it is required to be able to quickly recognize the data start/stop speed of these partner terminals.

[Prior Art] Conventionally, terminal modems and the like have been configured to set their own data speed using a switch, keyboard, etc., depending on the data speed of a connected device.

FIG. 5 is a conceptual diagram of the configuration of a conventional system. A modem 1 and a partner device 2 are connected via a cable 3. modem 1
is provided with a date switch 1a for setting a data transfer rate according to the data rate of the partner device 2. Then, data is transferred from the modem to the partner device 2 at the data rate set by the day switch 1a.

[Problem to be solved by the invention] In conventional systems, whenever the data rate changes or the partner device changes, the data rate must be changed manually each time, resulting in poor operability. In some cases, there was a risk that the data rate could be set incorrectly.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an automatic start-stop data rate recognition circuit that can automatically recognize the start-stop data rate.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
11 has a specific character SD related to data speed transmitted from the connected terminal terminal via bi-soto serial,
A counter control circuit 12 receives the character SD and controls the start of the counting operation of the counter, and a counter control circuit 12 receives a clock (n clock) that is n times the maximum baud rate of the serial data to be transferred, and controls the counter control circuit 11. Below is a counter that performs a counting operation of n clocks; 13 is a shift register that converts the character SD into parallel data using the output of the counter 12 as a shift clock; 1
4 is an identification circuit for detecting that the output of the shift register 13 matches a predetermined value; 15 is the identification circuit 1;
This is a flip-flow tube that latches the output of 4 with the output clock of the counter 12 and uses the latched output as a discrimination output.

[Operation] The connected terminal sends the data speed of that terminal as a specific character SD, and this character SD is converted to parallel data in the shift register 13, and the standard set in advance in the identification circuit 14 is converted. Compare with data. If they match, it is known that the baud rate is the one recognized by itself, so the flip-flop 15 and the identification circuit 14
The output is latched and the discrimination output is given to an internal CPU (not shown). The CPU receives this determination output and transfers data to the other party's terminal at the recognized baud rate.

In this manner, according to the present invention, it is possible to automatically recognize the start-stop data rate.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.
A specific example is shown in which two speeds (1200, 6 (10 bps)) can be recognized in series.The example shown in the figure is n times (n -16
) is used as the n clock of 9°6 KHz. Components that are the same as those in FIG. 1 are designated by the same reference numerals.

In the figure, a counter control circuit 11 includes an inverter G1 that inverts a character SD and a flip-flop FFI that receives the output of the inverter G1 as a clock CLK. "H" is input to the 0 manual input of the flip-flop FF, and a reset signal R is input to the reset manual input R.
Contains ESET. The Q output of flip-flop FFI is input to the load input LOAD of counter 12.

A clock of 9.6 is input to the clock CLK of the counter 12, and a reset signal RESE is input to the reset input R.
It has a T in it. In this example, 1200 bps and 6
00 bps, a shift register 13A for 1200 bps manual power and a shift register 13B for 600 bps manual power are provided. character sd
is common to the data output of these shift registers 13A and 13B, and the Q2 output of the counter 12 is input to the clock input CLK of the shift register 13A.
The three outputs (MSB) are respectively input to the clock CLK of the shift register 13B.

The counter 12 is a 4-bit counter, and the clock is 2/16 times (1
, 2KHz) and the 16x clock to 1/
It is equipped with a Q3 output that increases the frequency by 16 times (600Hz).

Both shift registers 13A and 13B constitute a 6-bit serial-to-parallel converter, and convert manually input serial characters SD into parallel data.

The identification circuit 14 corresponds to the shift register 13A.
and 14B corresponding to the shift register 13B are provided. These identification circuits 14A.

The input gates of each of the shift registers 14AB are configured to output an "H" level when the outputs of the shift registers 13A and 13B form a predetermined pattern.

The output of the identification circuit 14A enters the flip-flop 15A via the OR gate G2, and the output of the identification circuit 14B enters the flip-flop 15B via the OR gate G3.
It is within the power of 0 people. These flip-flops 15A
, 15B clock CLK has respective counter outputs Q2. Q3 is input, and the reset signal RESET is input to the reset manual input. Then, the Q outputs of each flip-flop 1.5A to 15B are taken out as discrimination outputs, and the respective OR gates G2. It is in the other input of G3. The operation of the circuit configured as described above will be explained as follows.

First, the detection operation of 1.200 bps will be explained using FIG. The human-powered character SD is (
As shown in a), the data is manually input in a bit-serial manner by sandwiching the data with a start bit ST and a stop bit SP.

The bit before the stop bit SP is the parity bit P. Now, the human-powered character SD is set to 21. o (H indicates hexadecimal). When the start bit ST of the character SD falls as shown in (a), the output of the inverter G1 rises to "H" in synchronization with this.

This rising edge becomes the latch clock for the flip-flop FFI, and latches the "H" level of the D input.

Therefore, the signal input to the LOAD of the counter 12 rises to "H" as shown in (b), enabling the counter 12.

As a result, the counter 12 starts counting the 9.6 KHz clock. The Q2 output of the counter 12 is (c
). Using this clock as a shift clock, the shift register 13A is a human-powered character SD.
are sequentially converted into parallel data and output as shown in (d) to (i). When the input code 21u described above is converted into binary data, it becomes "HLLLLH". Therefore, when the four middle bits are inverted and input to the identification circuit 14A, the output becomes "H" as shown in (j). this"
When latching "H" with a clock, flip-flop 1.
The output of 5A becomes “H” as shown in (U), and 21□
is detected.

When the Q output of the flip-flop 1.5A becomes “H”,
The signal is fed back to the OR gate G2 to close the gate. As a result, it is possible to prevent the output of the flip-flop 15A from inverting from "H" to "L".

At this time, the output of the identification circuit 14B that detects 600 bps does not become 21H, so its output remains "L" as shown in (k), and the Q output of the flip-flop 15B similarly remains "L". It is.

Above, we have explained the case of detecting 1200bps, but in exactly the same way, 600bps is detected in shift register 1.
3B, identification circuit 14B, and flip-flop 15B. The time chart at this time is as shown in FIG. The operation is exactly the same as in FIG. 3, only the clock is slower. In this way, if the output of the flip-flop 15A becomes "H", 1
If the output of the flip-flop 15B becomes "H", it can be determined that the speed is 600 bps.

In the above-described embodiment, the case where two types of data speeds are determined is taken as an example, but the present invention is not limited to this, and three types of data speeds are determined.
It can also detect more than one type of data rate. In this case, a shift register.

It may be necessary to provide as many identification circuits and flip-flops as there are data rates.

[Effects of the Invention] As described above in detail, according to the present invention, the bit-serial character SD sent from the partner device is converted into parallel data, and the converted data is converted to a predetermined reference value. By configuring the comparison, it is possible to automatically recognize the start-stop data speed.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a configuration block diagram showing an embodiment of the present invention, Fig. 3 is a time chart showing a 1200 bps detection operation, and Fig. 4 shows a 600 bps detection operation. The time chart, Figure 5, is a conceptual diagram of the configuration of the conventional system. In FIG. 1, 11 is a counter control circuit, 12 is a counter, 13 is a shift register, 14 is an identification circuit, and 15 is a flip-flop.

Claims (1)

[Scope of Claims] A counter control circuit (11) that receives bit-serial transfer of a specific character SD related to data speed from a connected terminal and controls the start of counting operation of a counter upon receiving the character SD; a counter (12) that receives a clock (n clocks) of n times the highest baud rate of the serial data to be transmitted and performs a counting operation of n clocks under the control of the counter control circuit (11); ) a shift register (13) that converts the character SD into parallel data using the output as a shift clock; and an identification circuit (14) that detects that the output of the shift register (13) matches a predetermined value; An automatic start-stop data speed recognition circuit is constructed of a flip-flop (15) which latches the output of the identification circuit (14) with the output clock of a counter (12) and uses the latched output as a discrimination output.