JPH03259123A - Display device, manufacture of display device, and substrate for display - Google Patents

Abstract

PURPOSE:To manufacture the display device efficiently by setting the minimum working size of semiconductor elements formed in a display area smaller than the minimum working size of semiconductor elements outside the display area. CONSTITUTION:The minimum working size of the semiconductor elements formed in the display area 11 is made smaller than the minimum working size of the semiconductor elements in areas 12 and 13 other than the display area. Namely, a picture element part 11 is formed by repeating the same pattern in two dimensions and worked finely by performing alignment and exposure divisionally plural times. A lead-out wiring part, on the other hand, is not the repetition of the same pattern frequently and a peripheral circuit part which is large in working rule is worked finely by batch exposure. Consequently, the peripheral circuit part and picture element part are formed having proper constitution without increasing the number of manufacture processes.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a display device 9 display device manufacturing method and display substrate, and particularly to a display device suitable for liquid crystal display, a display device manufacturing method, and a display device. related to the board for use.

[Conventional technology]

In TPT panels for liquid crystal display devices, T for each pixel is
Active matrix panels with built-in peripheral circuits are known in which PT elements and peripheral circuits for driving them are formed on the same substrate. Regarding these, for example, JP-A No. 64-2088 and JP-A No. 60-26932 can be mentioned.

Furthermore, a configuration is known in which a plurality of TPT elements are arranged in each pixel in order to provide redundancy to the TPT panel and improve the yield of large-screen panels. Regarding these, JP-A-63-186216, JP-A-61-121034, etc. can be mentioned.

Further, as a method of manufacturing a large-screen TPT panel, there is a divisional exposure method such as JP-A-61-180275.

[Problem to be solved by the invention]

In the above conventional technology, no special consideration is given to the structure of the TPT for each pixel and the TPT for the peripheral circuit, and therefore it is difficult to optimize the characteristics of both TFTs. There is.

An object of the present invention is to provide a display device and a display substrate having excellent characteristics. Furthermore, it is an object of the present invention to provide a method for manufacturing a display device that allows relatively easily obtaining a display device and a display substrate having excellent characteristics.

Another object of the present invention is to provide a TPT for each pixel and a TPT for peripheral circuits.
The object of the present invention is to form an optimal structure of each PT using a simple method, and to provide a panel exhibiting excellent properties.

Another object of the present invention is to provide a method for efficiently manufacturing a large-screen FT panel with excellent pattern accuracy.

[Means to solve the problem]

The features of the present invention for achieving the object E are as follows: 1) A display device includes at least one substrate, a plurality of semiconductor elements formed on the substrate, and a display body controlled by the semiconductor element. , the substrate is divided into a display area and an area other than the display area, the semiconductor element is formed in the display area and the area other than the display area, and the semiconductor element formed in the display area has a minimum processing dimension. is characterized in that it is smaller than the minimum processing dimension of the semiconductor element formed in the area other than the display area.

2) In the method for manufacturing a display device, a step of providing at least four substrates, and a step of dividing the substrate into a display area and a region other than the display area and forming a semiconductor element in each region. and forming a display body controlled by the semiconductor element, the semiconductor element being formed in the display area.

The method is characterized in that a divided exposure method is used, and the formation of the semiconductor element in areas other than the display area is performed by a batch exposure method.

3) In the display substrate, at least one substrate and 1.
1. A plurality of semiconductor elements formed on a substrate; the substrate is divided into a display area and an area other than the display area, and the semiconductor element has a display area and an area other than the display area. The minimum processing size of the semiconductor element formed in the first display area is smaller than the minimum processing size of the semiconductor element formed in an area other than the display area.

The objects/characteristics of the present invention described above and objects/characteristics of the present invention other than the above will be further clarified from the following description.

[Effect]

In order to achieve the above object, it was decided that the microfabrication rule for the rFT in the two-pixel portion is smaller than the microfabrication rule for the FT in the peripheral circuit portion. Here, the microfabrication rule refers to the minimum processing dimension (size of Si islands) for forming TPT.

(width and length of gate, width of contact hole, wiring layer) and allowance dimensions for mask alignment of these.

Furthermore, for this reason, in the photolithography step during the manufacturing process, it was decided that the peripheral circuit portions with large processing rules would be exposed all at once, and the pixel portions with small processing rules would be microfabricated by divided exposure.

In an active matrix panel with a built-in peripheral circuit for a liquid crystal display device, the pixel portion and the peripheral circuit portion have the following features.

(1) By reducing the size of the TPT in the pixel portion, the aperture ratio can be increased and a clear image can be obtained. This tendency is increasingly desired in high-definition display devices. On the other hand, there are fewer restrictions on the TPT processing method for the peripheral circuit portion, and relatively large elements can be used.

(2) As shown in FIGS. 1(b) and (c), which will be described later, the pixel portion is a two-dimensional repetition of the same pattern, and the photolithography process is divided into multiple steps per substrate for alignment. Microfabrication is possible by repeating exposure. On the other hand, in the peripheral circuit portion, the same pattern is not repeated in many cases, such as in the lead-out wiring portion, and the photomask must be changed every time the divided exposure is performed, resulting in poor workability. For this reason,
For the peripheral circuit area of one panel of the substrate j-, it is preferable to use a one-time exposure method of alignment and exposure.

(3) Regarding the characteristics of TPT, leakage current (off-state current) can be reduced in the pixel portion by reducing the TPT's width, and a clear image can be obtained. In the peripheral circuit portion, the size of the TPT can be increased to increase the withstand voltage between the source and drain, thereby increasing the driving capability.

(4) Substrates for TPT panels generally have a strain point of approximately 550 to 6.
A glass substrate at 50° C. is used. This glass substrate is deformed by heat treatment during the manufacturing process.

In particular, the problems of curvature and shrinkage are serious, and the dimensional shift becomes large around the glass substrate. Since the pixel part is placed in the center of the glass substrate, it is easy to perform microfabrication <The size of the TFT can also be made small, but the peripheral circuit part is placed in the periphery of the glass substrate, so it is necessary to process the TPT for pattern alignment etc. The larger the dimensions, the easier it is to create.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Embodiment 1 FIGS. 1(a), (b), (b), and (d) are a schematic plan view, a partially exploded perspective view, and a plane view of a TPT substrate for a liquid crystal display incorporating a peripheral circuit according to an embodiment of the present invention. A perspective cross-sectional view of a pattern and a color liquid crystal display device is shown.

Reference numeral 10 denotes a glass substrate, the quality of which is a strain point of 645° C. and the size of 60′×1.1t. Reference numeral 11 denotes a pixel area which is a display area in which TPTs for switches of each pixel are arranged in a matrix, and is 48 cm horizontally and 36 cm vertically, and is 50 pm.
The individual pixels of the mouth are arranged in 960 dots horizontally and 720 dots vertically, a total of 690,000 pixels. A polycrystalline silicon TPT with a minimum dimension of 3 μm is installed in this pixel. T.P.
T has an MO5 structure with a gate length of 10 μm.

The gate width is 3 μm. 12 and 13 are peripheral circuit areas which are areas other than the display area for driving pixel TPTs, and the minimum size of approximately 20,000 polycrystalline silicon TPs is 6 μm.
T is placed. 12 is a scanning line drive circuit consisting of a vertical shift register.

A signal line driving circuit 13 is composed of a sampling transistor, a dividing matrix, and a horizontal shift register. Typical processing dimensions of the TPT are the gate length of the load MO3 of 30 μm and the gate width of 10 μm, and the gate length of the driver MO5 of 6 μm and the gate width of 50 μm.

Note that the active matrix substrate formed in this example is used as a color liquid crystal display device as shown in FIG. 1(d). A thin film transistor 502 is formed on a glass substrate 501 near the intersection of signal electrodes 504 and scanning electrodes 503 formed in a matrix, and drives a pixel electrode 501 made of a transparent electrode. Glass substrates 5 facing each other with a liquid crystal layer 506, which is an electro-optic material, sandwiched therebetween.
A counter electrode 506 made of a transparent electrode and a color filter 507 are formed on 08, and a pair of glass substrates 501
, 508 are sandwiched therebetween. A pixel serving as a display body is thereby formed. A thin film transistor (TPT) driven color liquid crystal display device is constructed by adjusting the transmission of light from the light source at the pixel electrode 501 portion.

FIG. 2 shows a schematic cross-sectional view of the TPT. TPT for pixels
Since the planar dimensions (patterns) and the TPT for peripheral circuits are also different, they are created by the same process.

A polycrystalline silicon film 21 with a film thickness of 60 nm is formed on the surface of a glass substrate 20 by a low pressure CVD method at a substrate temperature of 550°C,
After further annealing in a nitrogen atmosphere at 600° C. for 20 hours, patterning was performed by photolithography. As described above, this patterning size is different between the pixel TPT and the peripheral circuit TPT. Next, a 120 nm thick silicon oxide film 22 as a gate insulating film and a 200 nm thick polycrystalline silicon film 23 as a gate electrode were deposited and patterned by photolithography. This pattern size is as described above, and the TFT section for one pixel is a TF for the peripheral circuit.
The minimum processing dimension is smaller than that of the T section. Thereafter, the source region 24. A drain region 25 was formed. Thereafter, an ITO transparent electrode and an aluminum wiring layer were formed.

Table 1 shows the characteristics of TPT formed by the above method. 1
The average value of measurements from 5 points on the board and 3 boards is shown. T of pixel part
The characteristic of PT is that its off-state current is small, which means that T
This is due to fine processing of PT. On the other hand, the characteristics of TPT・ in the peripheral circuit section are high breakdown voltage between source and drain.
Also, the carrier mobility is large, which is due to TPT
This is because the large dimensions of the polycrystalline silicon film prevent local breakdown and bunch-through of the polycrystalline silicon film, and reduce carrier mobility loss on the surface of the polycrystalline silicon layer. In terms of withstand voltage, the T-togo for the pixel part is approximately 】O~20
It is desirable that V and peripheral drive circuit TPT be approximately 30μ or more.

Example 2 Next, the screen size is 14" (commonly known as size, exact number is 26")
An example of application to a large screen liquid crystal display device of 8.8 m x 187.2 mm (12.9' diagonal) will be described with reference to FIG.

A TFT with a built-in peripheral circuit was formed in the same manner as in Example 1 using a glass substrate 3Q having a size of 300 x 235 mm2. However, the size of one pixel is 240 ITFT characteristics xF30p, m2, the number of pixels is: LL20x7BO, and the TPT dimension of the pixel section 31 is gate length 50 μm.

The dimensions of the TPT of the gate l118 μm9 peripheral circuit section 32 are gate length 50 pm and gate @50 μm.

The minimum wiring width is 10 μm in both cases, and the aperture ratio of one pixel is 60.5%.

The manufacturing process is the same as in Example 1 above.

In photolithography, as shown in Figure 3.

The peripheral circuit section 32 (scanning line drive circuit and signal line drive circuit) was exposed at once, and the 5 pixel section 31 was exposed 12 times in divisions. That is, first, the scanning line drive circuit and the signal line drive circuit were exposed at once, and then, using a 51 photomask, the pixel portion 3 was divided into 12 sections shown by dotted lines and exposed in sections. At this time, in order to prevent the scanning lines and signal lines from being disconnected at the boundaries of one divided exposure area, the following method is used as shown in FIG. First, a negative type photoresist was used, and 5 divided exposure areas were exposed overlapping each other by at least 10 μm ((a) in FIG. 4), which is the same as the wiring width W. As a result, it is possible to leave the photoresist in the portions irradiated with ultraviolet light at least once in the ultraviolet ray irradiated portion (hatched portion b) in the first divided exposure number and the ultraviolet ray irradiated portion (hatched portion C) in the second divided exposure number. This can prevent wiring breakage. Note that the area that has been double exposed to UV rays is almost surrounded by the area that has been exposed to normal UV rays once, so there is no negative effect on pattern accuracy. Good wiring connections are now possible without special consideration to the shape of the pattern.

This method makes it possible to form highly accurate patterns even on large-screen substrates.

In Example 2, pixel division was attempted as a method for improving the yield of TPT panels. Furthermore, gate split structure (multi-gate structure) is used to improve TPT characteristics, especially to reduce off-state current.
TPT was adopted.

FIG. 5 shows a plane pattern of pixel division. The manufacturing method is the same as in Example 2, but one pixel 50 is divided into two scan lines (5) and 2 (upper and lower).
Divided into two areas, one in each area, total of two T.
FT52a and 52b were installed. This results in one T
Even if the PT is damaged, the area of 1/2 of one pixel is 0N10FF
It works, defects are noticeable, and M is reduced. Also, T
F T 52 a.

In the structure of 52h, the gate electrodes 53a and 53b are divided into three parts with a pitch of 8μ. In addition, 54 is both 'r F T52a, 5
Signal line common to 2b, 55a and 55b are '1'F pa1''
A transparent electrode (ITO) is shown connected to the source region of.

With this structure, an aperture ratio of 49.7% is obtained for one pixel 50, and sufficient brightness can be obtained for practical use. Further, the gate division structure (multi-data electrode structure) can reduce the off-state current by half, and as a liquid crystal display device, a high-quality image can be obtained with small changes in brightness within the screen.

The present invention provides T
Not only PT, but also various sensors with built-in drive circuits, such as
It can also be applied to image sensors, pressure sensors that utilize the piezoresistance effect of silicon single crystals, thermal recording heads, etc.

Further, FIGS. 6 and 7 are photomask plane pattern diagrams showing differences in pattern size of a pixel portion and a peripheral circuit portion of a TPT-LCD.

It can be seen that the size of the Si island and the width of the AQ wiring are clearly different between the pixel portion and the peripheral circuit portion.

That is, FIG. 6 shows the pattern of area A shown in FIG. 1(c), and FIG. 7 shows the pattern of area B shown in FIG. 1(c).

To enumerate some of the features of the present invention, 1. In an active matrix panel in which peripheral drive circuits for a liquid crystal display device are built on the same substrate, the processing dimensions of the transistors in the pixel part are smaller than those in the peripheral drive circuit part. thing.

2. In an active matrix panel in which a peripheral driving circuit for a liquid crystal display device is built on the same substrate, the withstand voltage of the transistor in the peripheral driving circuit portion is made higher than that in the pixel portion.

3. In an active matrix panel in which a peripheral drive circuit for a liquid crystal display device is built on the same substrate, the leakage current of the transistor in the pixel part is made smaller than that in the peripheral drive circuit part.

4. Thin film transistors must be mainly made of polycrystalline silicon.

5. In the method of manufacturing a thin film transistor panel, the peripheral drive circuit portion should be exposed at once, and the two-pixel portion should be exposed using divided exposure.

6. To connect wiring near the boundary of divided exposure, use negative photoresist and expose the wiring in an overlapping manner with a dimension equal to or larger than the wiring width.

7. Forming a liquid crystal display using a thin film transistor panel.

According to the present invention, the peripheral circuit section and the pixel section of a TPT active matrix panel for liquid crystal display can each be formed into appropriate configurations without increasing the number of steps in the manufacturing process.

Therefore, it is possible to improve yield by forming high-definition panels, forming large-screen panels with high precision, and applying redundant systems.

That is, in TPT for LCD, if there is one defect in one substrate, the product will be rejected in principle.

In LSI, Si wafers are pelletized into small pellets, so even if one wafer has a defect, only that pellet becomes defective, and the other pellets can be considered good.

For this reason, 1) methods to prevent defects and 2) methods and redundancy systems that operate even in the presence of defects are being studied.

Examples of redundant systems include a) creating a plurality of TPTs for one pixel, and even if one is defective, the others operate and present a normal image;

b) Even if a wiring break occurs, normal operation can be achieved by double wiring.

C) A short circuit between the gate electrode and the drain electrode will cause a cross-shaped defect (all pixels in one vertical and horizontal row are destroyed), but this can be fixed by inserting an appropriate resistance value between the gate line and the gate electrode. It can be a defect (only one pixel).

and so on.

In the present invention, there is no particularly new redundant idea, but by distinguishing pattern accuracy, the above-mentioned redundant idea can be easily incorporated.

To provide a supplementary explanation of the terminology used in the specification, processing dimensions refer to the size of the Si island for TFT (gate width, gate length), the size of microfabrication such as the width of the wiring layer, and the width shown in Figure 2 24. , Fig. 4, width of c.

The breakdown voltage is the breakdown voltage between the source and drain of the MO5 structure TPT (factors that determine the breakdown voltage are the size (gate length), thickness, impurity concentration, etc. of the Si island).

The same substrate corresponds to the Si wafer of the glass substrate LSI process, which is the first starting material of the TPT process.

When adjoining or bonding different substrates, it is possible to create TPT on each substrate using separate processes.

Leakage current refers to the TPT's off-state current (source-to-train current when gate voltage (negative bias for n-channel) is applied).

Batch exposure 1-segment exposure is originally a batch exposure method in which the entire surface of one substrate is aligned and exposed once using a single photomask. Divide exposure is a method in which the exposure is performed separately.

Here, it refers to a method in which alignment and exposure is performed once for the peripheral circuit area, and alignment and exposure is performed multiple times for the pixel area.

The wiring width refers to the scanning path line and the signal path line.

〔Effect of the invention〕

According to the present invention, it is an object of the present invention to provide a display device and a display substrate having excellent characteristics. Furthermore, it is possible to provide a method for manufacturing a display device that allows relatively easily obtaining a display device and a display substrate having excellent characteristics.

[Brief explanation of drawings]

FIGS. 1(a) and 1(e) are schematic plan views of a T F'T panel for explaining embodiments of the present invention, and FIG. 1(b)
d) is a cross-sectional perspective view of a liquid crystal display device, FIG. 2 is a cross-sectional schematic diagram showing the FT structure of an embodiment of the present invention, and FIGS. 3 and 4 are views of a TPT panel of another embodiment of the present invention. A schematic plan view and a local enlarged view thereof, FIG. 5 is a schematic plan view of a pixel portion of a liquid crystal display device showing another embodiment of the present invention, and FIGS. 6 and 7 are
The figure is a plan view for explaining a pattern formed on a substrate. 10.30...Substrate, 1. ．． 1. ．． 31... Pixel area, 32 Fig. 1(a)? Figure ii (C) Glass curtain plate pixel area scanning II drive circuit Signal line 1 drive circuit Figure 1 (d) Figure 81 (b) Figure 2 Figure 81 (b) Figure 2

Claims (11)

[Claims] 1. at least one substrate; a plurality of semiconductor elements formed on the substrate; a display body controlled by the semiconductor element; the substrate is divided into a display area and an area other than the display area; The elements are formed in the display area and an area other than the display area, and the minimum processing dimensions of the semiconductor element formed in the display area are greater than the minimum processing dimensions of the semiconductor element formed in the area other than the display area. A display device characterized by its small size. 2. at least one substrate; a plurality of semiconductor elements formed on the substrate; a display body controlled by the semiconductor element; the substrate is divided into a display area and an area other than the display area; The element is formed in the display area and a region other than the display area, and the breakdown voltage of the semiconductor element formed in the area other than the display area is higher than the breakdown voltage of the semiconductor element formed in the display area. display device. 3. at least one substrate; a plurality of semiconductor elements formed on the substrate; a display body controlled by the semiconductor element; the substrate is divided into a display area and an area other than the display area; The elements are formed in the display area and a region other than the display area, and the leakage current of the semiconductor element formed in the display area is smaller than the leakage current of the semiconductor element formed in the area other than the display area. A display device characterized by: 4. a step of preparing at least one substrate; a step of dividing the substrate into a display area and a region other than the display area and forming a semiconductor element in each area; forming a display body controlled by the semiconductor element; The semiconductor element is formed in the display area by a divided exposure method, and the semiconductor element is formed in an area other than the display area by a batch exposure method. A method for manufacturing a display device. 5. In the method for manufacturing a display device according to claim 4, when carrying out the divided exposure method, in order to connect the wiring portions spanning between adjacent divided regions, a dimension larger than the wiring width is overlapped and exposed. A method for manufacturing a display device, characterized in that: 6. In the method for manufacturing a display device according to claim 5, when carrying out the divided exposure method, a dimension larger than the width of the wiring is overlapped in order to connect the wiring portions spanning between adjacent divided regions, and a negative 1. A method for manufacturing a display device, comprising exposing a molded photoresist to light. 7. A display device according to any one of claims 1 to 3, wherein the semiconductor element is a thin film transistor. 8. at least one substrate; a plurality of semiconductor elements formed on the substrate; the substrate is divided into a display area and an area other than the display area; and the semiconductor element is divided into the display area and an area other than the display area; A display substrate, characterized in that a minimum processing dimension of the semiconductor element formed in the display area is smaller than a minimum processing dimension of the semiconductor element formed in an area other than the display area. 9. 4. A display device according to claim 1, wherein the semiconductor element is a thin film transistor having an active layer made of polycrystalline silicon. 10. 4. A display device according to claim 1, wherein the semiconductor element in the display area is a thin film transistor having an active layer made of amorphous silicon. 11. 4. A display device according to claim 1, wherein the semiconductor element in a region other than the display region is a thin film transistor having an active layer made of polycrystalline silicon.