JP2934588B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a display device suitable for a liquid crystal display.

[0002]

2. Description of the Related Art In a TFT panel for a liquid crystal display device, there is known an active matrix panel with a built-in peripheral circuit in which TFT elements for each pixel and peripheral circuits for driving them are formed on the same substrate. For example, JP-A-64-2088, JP-A-60-26932 and the like are mentioned.

Further, in order to add redundancy to a TFT panel and to improve the yield of a large screen panel, a plurality of TFTs are provided in one pixel.
A configuration in which elements are arranged is known. Japanese Patent Application Laid-Open Nos. 63-186216 and 61-121034 relate to these.

Japanese Patent Application Laid-Open No. 61-180275 discloses a division exposure method as a method for manufacturing a large-screen TFT panel.

[0005]

In the prior art described above, no special consideration is given to the structure of the TFT for each pixel and the TFT for the peripheral circuit.
There is a problem that it is difficult to optimize the characteristics of both FT and FT.

An object of the present invention is to provide a display having excellent characteristics.
The object is to obtain the device relatively easily .

[0007]

[0008]

A feature of the present invention for achieving the above object is that a matrix is provided on the same substrate of a display device.
Area having a plurality of first semiconductor elements arranged in a matrix
Area and a plurality of second semiconductors for driving the display area.
Forming a peripheral circuit region having a body element and a second semiconductor element;
The point is that the breakdown voltage of the element is made higher than the breakdown voltage of the first semiconductor element .

The above objects and features of the present invention and other objects and features of the present invention will become more apparent from the following description.

[0010]

In order to achieve the above object, a TFT in a pixel portion is provided.
Is formed smaller than the fine processing rule of the TFT in the peripheral circuit portion. Here, the fine processing rule means the minimum processing dimensions (size of Si island, width and length of gate, width of contact hole and wiring layer) for forming a TFT, and allowance for mask alignment of these. Means dimensions.

Furthermore, in the photolithography step in the manufacturing process, the peripheral circuit portion having a large processing rule is finely processed by batch exposure, and the pixel portion having a small processing rule is finely processed by divided exposure.

In an active matrix panel with a built-in peripheral circuit for a liquid crystal display device, the features of the pixel portion and the peripheral circuit portion are as follows.

(1) When the size of the TFT in the pixel portion is reduced, the aperture ratio can be increased and a clear image can be obtained. This tendency is increasingly desired in high definition display devices. on the other hand,
In the peripheral circuit portion, there is little restriction on the processing size of the TFT, and a relatively large element can be used.

(2) As shown in FIGS. 2A and 2B described later, the pixel portion is a two-dimensional repetition of the same pattern.
Fine processing can be performed by repeating the photolithography process a plurality of times for one substrate and repeating alignment and exposure. On the other hand, in the peripheral circuit portion, in many cases, the same pattern such as a lead-out wiring portion is not repeated, and the photomask needs to be changed each time divided exposure is performed, resulting in poor workability. Therefore, the peripheral circuit area for one panel on the substrate is desirably a batch exposure method using one alignment and exposure.

(3) In the characteristics of the TFT, the pixel portion is TF
By reducing the dimension of T, a leak current (off current) can be reduced and a clear image can be obtained. In the peripheral circuit portion, the size of the TFT is increased, the breakdown voltage between the source and the drain is increased, and the driving capability can be increased.

(4) As a substrate for a TFT panel, a glass substrate having a strain point of about 550 to 650 ° C. is generally used. This glass substrate is deformed by heat treatment during the manufacturing process. In particular, the problems of curvature and shrinkage are great, and the dimensional shift is large in the periphery of the glass substrate. Since the pixel portion is arranged in the center of the glass substrate, it can be finely processed and the size of the TFT can be reduced. However, the peripheral circuit portion is arranged in the periphery of the glass substrate. It is easier to create a larger one.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIGS. 1 (a) and 1 (b) and FIGS. 2 (a) and 2 (b) are schematic plan views, partially exploded perspective views, of a liquid crystal display TFT substrate having a built-in peripheral circuit according to an embodiment of the present invention. FIG. 1 shows a plan view, a plane pattern thereof, and a perspective sectional view of a color liquid crystal display device. Reference numeral 10 denotes a glass substrate having a strain point of 645 ° C. and a size of 600 on one side.
mm square and 1.1 mm thick. Reference numeral 11 denotes a pixel area, which is a display area in which switching TFTs of each pixel are arranged in a matrix and has a width of 48 mm and a length of 36 mm. Each pixel having a square of 50 μm on each side is 960 dots wide and 72 pixels long.
0 dots, a total of 690,000 are arranged. In this pixel, a polycrystalline silicon TFT having a minimum size of 3 μm is provided. The TFT has a MOS structure, and its processing dimensions are a gate length of 10 μm and a gate width of 3 μm. Reference numerals 12 and 13 denote peripheral circuit regions which are regions other than the display region for driving the pixel TFTs. About 20,000 polycrystalline silicon TFTs each having a minimum dimension of 6 μm are arranged. Reference numeral 12 denotes a scanning line driving circuit including a vertical shift register, and reference numeral 13 denotes a signal line driving circuit including a sampling transistor, a division matrix, and a horizontal shift register. Representative TFT
The processing dimensions are as follows: load MOS gate length 30 μm, gate width 10 μm, driver MOS gate length 6 μm, gate width 50 μm.

The active matrix substrate formed in this embodiment is used as a color liquid crystal display as shown in FIG. On a glass substrate 501, a signal electrode 504 and a scanning electrode 503 are formed in a matrix.
Are formed, and the pixel electrode 501 made of a transparent electrode is driven. A counter electrode 506 made of a transparent electrode is provided on a glass substrate 508 facing the liquid crystal layer 506 which is an electro-optical material.
And a color filter 507, and a polarizing plate 505 is provided so as to sandwich the pair of glass substrates 501 and 508. Thus, a pixel serving as a display is formed.
A color liquid crystal display device driven by a thin film transistor (TFT) is configured by adjusting the transmission of light from a light source at the pixel electrode 501 portion.

FIG. 4 is a schematic sectional view of the TFT. The pixel TFTs and the peripheral circuit TFTs are also formed by exactly the same process except for the plane dimensions (pattern).

A polycrystalline silicon film 21 having a thickness of 60 nm is formed on a surface of a glass substrate 20 by low pressure CVD at a substrate temperature of 550 ° C.
Then, after annealing in a nitrogen atmosphere at 600 ° C. for 20 hours, patterning was performed by photolithography. This patterning size is the pixel TFT as described above.
And the peripheral circuit TFT are different. Next, a silicon oxide film 22 as a gate insulating film having a thickness of 120 nm and a thickness of 20
A polycrystalline silicon film 23 as a 0 nm gate electrode was deposited and patterned by photolithography. This pattern size is the above-mentioned size, and the minimum processing size of the pixel TFT portion is smaller than that of the peripheral circuit TFT portion. After that, the source region 24 and the source region 24 are implanted by ion implantation / annealing of phosphorus by a self-alignment method widely used today.
A drain region 25 was formed. Thereafter, a transparent electrode of ITO and an aluminum wiring layer were formed.

FIG. 3 shows the characteristics of the TFT formed by the above method. The average value of the measurements of 5 points and 3 substrates in one substrate is shown. A feature of the TFT in the pixel portion is that the off-state current is small, which is due to fine processing of the TFT. On the other hand, the characteristics of the TFT in the peripheral circuit portion are that the withstand voltage between the source and the drain is high and the carrier mobility is large. This is because through-flow can be prevented and loss of carrier mobility on the surface of the polycrystalline silicon layer is reduced. Withstand voltage is TF for pixel part
It is desirable that T is about 10 to 20 V and the peripheral drive circuit TFT is about 30 V or more.

Embodiment 2 Next, a screen size of 14 ″ (commonly known size, more precisely, 268.
An example in which the present invention is applied to a large-screen liquid crystal display device having a size of 8 mm × 187.2 mm and a diagonal of 12.9 ″) will be described with reference to FIG.

Glass substrate 3 of size 300 × 235 mm ²
0, a TFT panel with a built-in peripheral circuit was formed in the same manner as in Example 1. However, the size of one pixel is 240 × 80
μm ² and the number of pixels is 1120 × 780.
Indicates that the dimensions of the TFT are gate length 50 μm, gate width 8 μm,
The dimensions of the TFT of the peripheral circuit section 32 are a gate length of 50 μm and a gate width of 50 μm, and the minimum wiring width of both is 10 μm.
And the aperture ratio of the pixel is 60.5%.

The manufacturing process is the same as that of the first embodiment, but in photolithography, as shown in FIG. 5, the peripheral circuit portion 32 (scanning line drive circuit and signal line drive circuit) is exposed at a time, and the pixel portion 31 is exposed at one time. The exposure was divided into 12 times. That is, first, the scanning line driving circuit and the signal line driving circuit are exposed by batch exposure, and then the pixel portion 31 is divided and exposed in 12 sections shown by a dotted line using a 5 ″ photomask. In order to prevent the disconnection of the scanning line and the signal line at the boundary of, the following method is used as shown in Fig. 6. First, a negative type photoresist is used, and the area of the divided exposure is set to 10 µm which is the same as the wiring width W (( a)) The above exposure was repeated as a result, and as a result, at least one ultraviolet irradiation was performed on the ultraviolet irradiation portion (hatched portion b) in the first divided exposure and the ultraviolet irradiation portion (hatched portion c) in the second divided exposure. The photoresist can be left in the area to prevent disconnection of the wiring, and the part that has been subjected to double UV irradiation is almost surrounded by the part that has been subjected to normal single UV irradiation. It does not adversely affect the pattern accuracy. This allowed a good wiring connections without any special consideration to the shape of the connection pattern at the boundary of the divided exposure areas.

According to this method, a high-precision pattern can be formed even on a large-screen substrate.

In Example 2, pixel division was attempted as a method for improving the yield of a TFT panel. Further, a TFT having a gate division structure (multi-gate structure) was employed to further improve the TFT characteristics, particularly to reduce the off-state current.

FIG. 7 shows a plane pattern of pixel division. The manufacturing method is the same as that of the second embodiment, except that one pixel 50 is connected to the scanning line 51.
, And two TFTs 52a and 52b were provided, one for each area. This allows
Even if one TFT is damaged, half the area of one pixel is ON
/ OFF operation to make defects less noticeable. The structure of the TFTs 52a and 52b is also different from that of the gate electrodes 53a and 52b.
53b was divided into three at an 8 μ pitch. 54 is both TFs
T52a and 52b are common signal lines, and 55a and 55b are T
4 shows a transparent electrode (ITO) connected to the source region of the FT. In this structure, the aperture ratio of one pixel 50 is 49.7%, and practically sufficient luminance is obtained. Further, the off-state current can be reduced to half by the gate division structure (multi-data electrode structure), and a change in luminance in a screen as a liquid crystal display device is small and a high-quality image can be obtained.

The present invention is not limited to TFTs in a pixel portion and peripheral circuits in a liquid crystal display device, but also includes various sensors having a built-in drive circuit, for example, an image sensor, a pressure sensor utilizing the piezoresistance effect of silicon single crystal, and a thermosensitive recording device. Also applicable to heads and the like.

FIGS. 8 and 9 are photomask plane pattern diagrams showing the difference in pattern size between the pixel portion and the peripheral circuit portion of the TFT-LCD.

It is clear that the size of the Si island and the width of the Al wiring are different between the pixel portion and the peripheral circuit portion.

That is, the region A shown in FIG. 8 and FIG.
FIG. 9 shows the pattern of the region B shown in FIG.

Some of the features of the present invention are listed below: In an active matrix panel in which a peripheral drive circuit for a liquid crystal display device is incorporated on the same substrate, the processing dimensions of the transistors in the pixel portion are smaller than those in the peripheral drive circuit portion.

2. In an active matrix panel in which a peripheral drive circuit for a liquid crystal display device is incorporated on the same substrate, the withstand voltage of the transistor in the peripheral drive circuit portion is made larger than that in the pixel portion.

3. In an active matrix panel in which a peripheral driving circuit for a liquid crystal display device is incorporated on the same substrate, the leakage current of the transistor in the pixel portion is made smaller than that in the peripheral driving circuit portion.

4. Thin film transistors are mainly composed of polycrystalline silicon.

5. In the method of manufacturing a thin film transistor panel, the peripheral drive circuit portion is of a collective exposure type, and the pixel portion is of a divisional exposure type.

6. The connection of the wiring near the boundary of the divided exposure is
Exposure by using a negative photoresist to overlap a dimension larger than the wiring width.

7. A liquid crystal display device is formed using a thin film transistor panel.

According to the present invention, a peripheral circuit and a pixel portion of a TFT active matrix panel for liquid crystal display can be formed into appropriate configurations without increasing the number of steps in a manufacturing process. Therefore, it is possible to improve the yield by forming a high-definition panel, forming a large-screen panel with high accuracy, and applying a redundant system.

That is, in the case of an LCD TFT, if one substrate has one defect, it is rejected in principle.

In the LSI, since the Si wafer is pelletized in a small size, even if there is a defect in one wafer, only the pellet becomes defective and the other pellets can be regarded as good products.

For this reason, 1) a method of preventing a defect 2) a method of operating even if there is a defect, and a redundant system are being studied.

Examples of the redundant system (system) are as follows: a) A plurality of TFTs are formed for one pixel, and even if one is defective, the other operates to show a normal image.

B) Even if the wiring breaks, normal operation is performed by double wiring.

C) When the gate electrode and the drain electrode are short-circuited, a cross-shaped defect (all the pixels in one row and one row are lost) occurs, but an appropriate resistance value is inserted between the gate line and the gate electrode. Point defect (only one pixel)
Can be.

And the like.

In the present invention, there is no particular new redundant idea, but by distinguishing the pattern accuracy, the above-mentioned redundant idea can be easily adopted.

The terms in the specification will be supplementarily explained. The processing size is the size of the fine processing such as the size of the Si island for the TFT (gate width and gate length) and the width of the wiring layer. The width of the source region 24 and the widths of b and c shown in FIG.

The breakdown voltage refers to the source of a MOS-structured TFT.
The breakdown voltage between the drains (the factors that determine the breakdown voltage are the size (gate length), thickness, impurity concentration, etc. of the Si island).

The same substrate corresponds to a Si wafer in a glass substrate LSI process, which is a first starting material in a TFT process.

When another substrate is placed adjacent to or bonded to another substrate,
It is possible to create a TFT on each substrate by a separate process.

The leak current refers to the off current of the TFT (source-drain current when a gate voltage (negative bias is applied in the n-channel)).

The batch exposure and the division exposure are originally a method in which the entire surface of a single substrate is subjected to a single alignment and exposure using a single photomask. A method that is performed separately from alignment exposure is division exposure.

In this case, the peripheral circuit region is divided into a single alignment and exposure, and the pixel region is divided into a plurality of alignments and exposures.

The wiring width means a scanning bus line and a signal bus line.

[0057]

According to the present invention, a table having excellent characteristics is provided.
The indicating device can be obtained relatively easily .

[Brief description of the drawings]

FIG. 1 is a schematic view of a TFT panel according to one embodiment of the present invention.

FIG. 2 is a schematic view of a TFT panel according to another embodiment of the present invention.

FIG. 3 is a diagram showing characteristics of a TFT formed by the method of the present invention.

FIG. 4 is a schematic sectional view of the TFT shown in FIG. 2 of the present invention.

FIG. 5 is a schematic view of a TFT panel according to another embodiment of the present invention.

FIG. 6 is a diagram illustrating a case where exposure is performed with a dimension equal to or larger than a wiring width according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a planar pattern of pixel division according to an embodiment of the present invention.

8 is a diagram showing a pattern of a region A shown in FIG.

9 is a diagram showing a pattern of a region B shown in FIG.

[Explanation of symbols]

10: glass substrate, 11: pixel area, 12: scanning line driving circuit, 13: signal line driving circuit.

Continuation of the front page (56) References JP-A-61-7871 (JP, A) JP-A-61-180275 (JP, A) IEICE Technical Report, October 1986, Vol. 86 No. 205, p. 59-64 IEICE Technical Report, October 1984, Vol. 84 No. 159, p. 21 −26

Claims (5)

(57) [Claims] A display area on the same substrate;
A display device having a peripheral circuit area for driving.
Te, the display area is a first plurality arranged in a matrix
A semiconductor element, wherein the peripheral circuit region has a plurality of second semiconductor elements, and a withstand voltage of the second semiconductor element is equal to that of the first semiconductor element.
A display device having a higher breakdown voltage. 2. The display area according to claim 1, wherein the display area and the periphery thereof are arranged.
The first and second semiconductor elements formed in the circuit area are
Display device characterized by being formed on the same plane layer
Place. 3. The method according to claim 1, wherein
The second semiconductor element is a thin film transistor
Display device. 4. The method according to claim 1, wherein
The first semiconductor element formed in the indicated area is polycrystalline silicon.
A display device comprising: an active layer. 5. The method according to claim 1, wherein
The liquid crystal layer is formed on the display area.
Display device.