JPH0325878B2 - - Google Patents
Info
- Publication number
- JPH0325878B2 JPH0325878B2 JP60196507A JP19650785A JPH0325878B2 JP H0325878 B2 JPH0325878 B2 JP H0325878B2 JP 60196507 A JP60196507 A JP 60196507A JP 19650785 A JP19650785 A JP 19650785A JP H0325878 B2 JPH0325878 B2 JP H0325878B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- bit line
- sense amplifier
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Read Only Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60196507A JPS6257196A (ja) | 1985-09-05 | 1985-09-05 | 半導体メモリ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60196507A JPS6257196A (ja) | 1985-09-05 | 1985-09-05 | 半導体メモリ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6257196A JPS6257196A (ja) | 1987-03-12 |
| JPH0325878B2 true JPH0325878B2 (cs) | 1991-04-09 |
Family
ID=16358901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60196507A Granted JPS6257196A (ja) | 1985-09-05 | 1985-09-05 | 半導体メモリ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6257196A (cs) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2617976B1 (fr) * | 1987-07-10 | 1989-11-10 | Thomson Semiconducteurs | Detecteur electrique de niveau logique binaire |
| JP3630847B2 (ja) * | 1996-05-16 | 2005-03-23 | 株式会社ルネサステクノロジ | ラッチ回路 |
| CN107657312B (zh) * | 2017-09-18 | 2021-06-11 | 东南大学 | 面向语音常用词识别的二值网络实现系统 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182194A (ja) * | 1982-04-20 | 1983-10-25 | Nec Corp | ダイナミツクメモリ集積回路 |
-
1985
- 1985-09-05 JP JP60196507A patent/JPS6257196A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6257196A (ja) | 1987-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3903674B2 (ja) | 半導体メモリ装置 | |
| US4612631A (en) | Static type semiconductor memory circuit | |
| JP4339532B2 (ja) | セルフタイミング回路を有するスタティックメモリ | |
| US6556471B2 (en) | VDD modulated SRAM for highly scaled, high performance cache | |
| US5015891A (en) | Output feedback control circuit for integrated circuit device | |
| JPH0253879B2 (cs) | ||
| JPH08279282A (ja) | 集積回路メモリ | |
| JPH0422318B2 (cs) | ||
| JPH087573A (ja) | 半導体記憶装置と、そのデータの読出および書込方法 | |
| JPH0713863B2 (ja) | ダイナミック型ランダムアクセスメモリ | |
| JP2001110187A (ja) | 改良型sramの方法と装置 | |
| US5883846A (en) | Latch type sense amplifier having a negative feedback device | |
| JPS63188887A (ja) | 半導体メモリ | |
| US6034915A (en) | Memory with variable write driver operation | |
| JPH09167493A (ja) | ビットラインプリチャージ回路 | |
| JPH0325878B2 (cs) | ||
| US6137715A (en) | Static random access memory with rewriting circuit | |
| JP2003030991A (ja) | メモリ | |
| JP3180883B2 (ja) | 半導体記憶装置 | |
| JP2580086B2 (ja) | スタテイック型半導体記憶装置 | |
| US7054210B2 (en) | Write/precharge flag signal generation circuit and circuit for driving bit line isolation circuit in sense amplifier using the same | |
| US5438551A (en) | Semiconductor integrated circuit device | |
| US7142465B2 (en) | Semiconductor memory | |
| JPH0330234B2 (cs) | ||
| TWI889299B (zh) | 記憶體裝置及其操作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |