JPH03258111A - Channel selection signal output device for fm receiver - Google Patents

Abstract

PURPOSE:To prevent malfunction of channel selection due to noise at weak electric field by controlling the output level of a 1F counter signal for channel selection in response to the signal intensity. CONSTITUTION:An output in response to an intermediate frequency input level exists at a signal intensity display output terminal 9. When a prescribed voltage is applied to a constant voltage terminal 10, a voltage divided by resistors R4, R5 is applied to a terminal 8 and inputted to the base of a transistor(TR) Q5 through an output resistor R3. When an intermediate frequency signal level is low, the TR Q5 is turned on and a current flows to a diode D1. A collector current flows to the collector of a TR Q3 to supply a current to the base of a TR Q1. As a result, the Tr Q1 is turned on and the TR Q2 is turned off and a 1F counter output is outputted from an output terminal 7 and when a signal level is large conversely, the 1F counter output is outputted. The base voltage of the TR Q5 controls the 1F counter output with a desired intensity display output by selecting resistors R4, R5. Thus, the 1F counter output level is decreased at the desired electric field strength or below to prevent malfunction of channel selection.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a tuning signal output device for an FM receiver.

BACKGROUND OF THE INVENTION FIG. 6 is a block diagram showing a portion of a conventional FM receiver. In Fig. 6, 13 is an intermediate frequency amplification
An amplitude limiter, 14 is an FM detector.

16 is a search stop clear (hereinafter referred to as 5S (2) circuit, 3
is an IP counter output amplifier. 12 is an FM intermediate frequency input terminal, and 15 is a detection output terminal.

7 is an IF counter output terminal, and 8 is an SSC input terminal. In FIG. 6, the FM intermediate frequency signal input from the FM intermediate frequency input terminal 12 is amplified and amplitude limited by the intermediate frequency amplification/amplitude limiter 13, and detected by the FM detector 14, and detected as a low frequency signal. It is output from the output terminal 15. In addition, the signal used when selecting a station by counting the FM intermediate frequency signal is supplied to the IF counter signal input terminal 1.
8 and the IP counter output amplifier 3 to the SSC circuit 16, and is output from the IP counter output terminal 7.

The SSC circuit 16 is a circuit for stopping the IF counter output except when selecting a channel, because if the IF counter output is output in a receiving state other than when selecting a channel, it may have an adverse effect on the receiving characteristics. Its operation/stopping is controlled by the voltage applied to the SSC input terminal 8.

FIG. 7 shows a part of a conventionally used SSC circuit 16. In FIG. 7, parts with the same functions as those in FIG. 6 are given the same numbers. 6 is a ground terminal, 5 is a power supply voltage terminal, Q+ is a switching transistor, Q2 is an emitter follower transistor (buffer) for IF counter output,
R1 is IF counter output resistance + R2 is transistor Q2
The emitter resistance +R3 is the base resistance of the transistor Q1.

In FIG. 7, F from the IF output counter intensifier 3
The M intermediate frequency signal is passed through the IF counter output emitter follower transistor Q2 and the output resistor R+! It is output from the F counter output terminal 7. In this case, if the voltage at the SSC input terminal 8 is at H level (necessary and sufficiently high voltage to cut off the transistor Q+), the transistor Q2 operates and the IF counter output is output from the IF counter output terminal 7. , the voltage of SSC input terminal 8 is L
level (transistor Q1 turns on, the collector current flows, and the emitter voltage of transistor Q2 rises, enough voltage to cut off transistor Q2), transistor Q2 turns off and the IF counter output terminal 7 will no longer be output. In this manner, in the conventional configuration, the output of the IF counter output terminal 7 is controlled by the voltage applied to the SSC input terminal 8.

Problem to be Solved by the Invention However, in the conventional configuration described above, when the gain of the receiver is sufficiently high or when the RF input level is low and the electric field is weak, the intermediate frequency component of the noise is detected by the IP counter as shown in Figure 5a. There is a problem in that the signal is output from the output terminal 7, and malfunctions in channel selection are likely to occur due to this.

The present invention solves these conventional problems,
FM that can prevent malfunctions in channel selection due to noise in weak electric fields.
The object of the present invention is to provide a channel selection signal output device for a receiver.

Means for Solving the Problems In order to achieve the above object, the present invention provides an SSC control circuit driven by the signal strength output obtained by detecting the amplitude limiter output, and adjusts the channel selection IF according to the signal strength. This is designed to control the output of the counter.

Effect: With this configuration, even if the IF counter output level does not decrease due to noise in a weak electric field and there is a risk of a malfunction in channel selection, the SSC control circuit can lower the IF counter output for channel selection. ,
Malfunctions in channel selection can be prevented.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to FIGS. 1 to 5.

FIG. 1 shows the main parts of an FM receiver according to an embodiment of the present invention, and parts having the same functions as those in FIG. 6 are given the same numbers. In FIG. 1, 1 is a signal strength detection circuit;
17 is an SSC control circuit, and 9 is a signal strength display output terminal. At the 11th g, the signal strength display output terminal 9 has the 4th
A signal strength display output corresponding to the intermediate frequency signal human power level as shown in FIG. f appears. The present invention uses this signal strength display output to drive the SSC control circuit, and uses the output to drive the SSC control circuit.
The circuit 16 is controlled to adjust the IF counter output level to 1il according to the intermediate frequency input level as shown in FIG. 5, c and d.
J90.

FIG. 2 shows a second embodiment of the present invention, which is a more concrete illustration of FIG. In Fig. 2, the same parts as in Fig. 7 are given the same numbers. Q4゜Q5 is a PNP) transistor that constitutes a differential amplifier, Dl, Q3 is a diode and NPN) transistor that constitutes a current mirror, R3 is an output resistance, I is a current source, 1 is a signal strength detection circuit, 2 is an inversion circuit , R4, and R5 are resistors for setting the intermediate frequency signal level for outputting the IF counter signal, 9 is a signal strength display output terminal, and 10 is a constant voltage terminal.

Next, the operation of the above embodiment will be explained. A signal strength display output corresponding to the intermediate frequency human power level is outputted to the signal strength display output terminal 9 as shown in FIG. 4f. Since this is extracted through the inverting circuit 2, an inverted output of f is obtained at the base of the transistor Q4 as shown in FIG. 4e. On the other hand, when a constant voltage is applied to the constant voltage terminal 10, a voltage VB divided by the resistors R4 and R5 is applied to the terminal 8.

This voltage V8 is expressed as Vs=(R5/(R4+R5)>XVIO.This voltage V8 is inputted to the base of transistor Q5 through output resistor R3.Transistor Q4.Q5
A differential amplifier consisting of the following operates as a switch circuit. Here, if the base voltage of the transistor Q4, that is, the inverted voltage of the signal strength display output, is higher than the base voltage V8 of the transistor Q5, that is, in a state where the intermediate frequency signal level is low, the transistor Q5 is turned on.
Current flows through diode D1. Since transistor Q3 constitutes a current mirror together with diode D+, the same collector current as the current flowing through diode D1 flows through the collector of transistor Q3 as well.
Apply current to the base of 1.

As a result, transistor Q1 turns on as in FIG.
Transistor Q2 is cut off, and no IF counter output is output from IF counter output terminal 7. Conversely, the base voltage of transistor Q4 is lower than the base voltage of transistor Q5.

That is, when the intermediate frequency signal level is high, the transistor Q5 is turned off, the transistor Q2 is turned on, and the IF counter output is output from the IF counter output terminal 7. The base voltage of transistor Q5 is resistor R
4. Since it can be set arbitrarily by appropriately selecting the value of Rs, the IP counter output can be turned on at the desired signal strength display output value.

Can be controlled to turn off. That is, IF counter outputs as shown in FIG. 5, c and d are obtained depending on the intermediate frequency signal human power level. Further, by applying conventional H and L levels to the constant voltage terminal 10, the same operation as shown in FIG. 7 is possible.

As described above, according to the above embodiment, the IF counter output level can be lowered when the electric field strength is below the desired level, and malfunctions in channel selection can be prevented.

FIG. 3 shows another embodiment of the present invention, and the same parts as in FIG. 2 are given the same numbers. The embodiment shown in FIG. 3 uses a differential amplifier composed of NPN transistors Qs and Q7, and it is easy to see that it operates in the same way as the embodiment shown in FIG. Furthermore, although in Fig. 3 the signal from the signal strength display output terminal 9 is input from another SSC control circuit input terminal 11, it goes without saying that it may be connected internally as shown in Fig. 2. Nor.

Effects of the Invention The present invention controls the output level of the IF counter signal for channel selection according to the signal strength, thereby providing IF control at any electric field strength.
The counter output can be cut off, and malfunctions in channel selection due to noise in a weak electric field can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a tuning signal output device of an FM receiver in an embodiment of the present invention, and FIG. 2 is a circuit diagram of a tuning signal output device of an FM receiver in a second embodiment of the invention. , FIG. 3 is a circuit diagram of a tuning signal output device of an FM receiver according to a third embodiment of the present invention, FIG. 4 is a characteristic diagram showing the signal strength display output in each of the above embodiments, and FIG. A characteristic diagram showing the IF counter output of each embodiment, FIG. 6 is a block diagram showing a conventional FM receiver tuning signal output device, and FIG.
The figure is a circuit diagram of a conventional tuning signal output device for an FM receiver. 1... Signal strength detection circuit, 2... Inverting circuit, 3... IF counter output amplifier, 5...
...Power supply voltage terminal, 6...Ground terminal, 7
...TF counter output terminal, 8...S
SC input terminal, 9... Signal strength display output terminal,
10... Constant voltage terminal, 11... SSC
Control circuit input terminal, 12...IF signal input terminal, 13...Amplitude limiter, 14...FM
Detector, 15...FM detection output terminal, 16...
...SSC (search stop clear circuit), 17
...SSC control circuit, 18...IF counter signal input terminal.

Claims (2)

[Claims] (1) Signal strength detection means for detecting the signal strength of a received signal; intermediate frequency signal output means for counting intermediate frequency signals and outputting an intermediate frequency signal for channel selection; A channel selection signal output device for an FM receiver, comprising means for blocking output of an intermediate frequency signal to the intermediate frequency signal output means based on the output of the detection means. (2) The tuning signal output device for an FM receiver according to claim 1, further comprising means for varying the signal strength for blocking intermediate frequency signals.