JPH03258105A - Emitter follower circuit - Google Patents

Abstract

PURPOSE:To obtain an emitter follower circuit to increase a descending speed of an output voltage without increasing the current consumption by employing a circuit comprising a 1st conduction transistor(TR) and 1st, 2nd other conduction TRs. CONSTITUTION:The circuit consists of a PNP TR 12 and NPN TRs 5, 7. Through the constitution above, when an input voltage drops rapidly, the TR 5 is cut off, In this case, a collector current of the TR 12 increases and a base current of the TR 7 increases via a capacitor 9. As a result, a pull-in current is increased and an output voltage drops rapidly, Since the flowing of a base current of the TR 7 is blocked by the capacitor 9 in the steady-state, the current consumption is not increased. Thus, through the constitution above, the descending speed of the output voltage is surely increased without increasing the current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an emitter follower circuit for a semiconductor integrated circuit.

BACKGROUND ART FIG. 3 shows a conventional emitter follower circuit, which will be explained. In Figure 3, 1 is the positive power supply, 2 is the input terminal, 3 is the bias terminal, 4 is the ground terminal, and 5 is the first N
PN ) transistor, 6 is the output terminal, 7 is the second NPN
) transistor, 8 is a resistor.

In Figure 3, bias terminal 3 and the second NPN)
The Langisthu and resistor 8 constitute a constant current source, and the whole constitutes an emitter follower circuit.

In the configuration shown in Figure 1, if the input voltage increases, the first
(NPN) transistor 5 supplies current to the output terminal 6 and the output voltage increases. On the other hand, when the input voltage decreases, the emitter current of the first NPN transistor 5 decreases, and the constant current source draws current from the output terminal 6, thereby decreasing the output voltage.

Problems to be Solved by the Invention In such a conventional configuration, when the input voltage suddenly drops, the first NPN transistor 5 enters the cut-off state. Therefore, the rate of fall of the output voltage is determined by the current value drawn by the constant current source. In order to increase the rate of fall of this output voltage, it is sufficient to increase the drawing current value. However, when the draw current is increased, the current flows even in a steady state where the input voltage does not change, resulting in an increase in current consumption.

The present invention has been made to solve these problems, and it is an object of the present invention to provide an emitter follower circuit that can increase the rate of fall of the output voltage without increasing current consumption.

Means for Solving the Problems In order to solve this problem, the present invention provides an emitter or a second
a first conductivity type transistor connected to a first constant potential via a resistor, connected to the base or input terminal, and connected to a second constant potential via the collector or constant current source; a first transistor of a second conductivity type, which is connected to a constant potential of the transistor, whose base is connected to the input terminal, and whose emitter is connected to the output terminal; a second second conductivity type transistor connected to a second constant potential, a base connected to a third constant power source, and a second conductivity type transistor connected to the collector of the first conductivity type transistor via a capacitor; A follower circuit is formed.

Further, in the present invention, instead of the second resistor and the transistor of the first conductivity type, the source is connected to the first constant potential, the gate is connected to the input terminal, and the drain is connected to the second resistor via the constant current source. An emitter 7107 circuit is formed using a MOS transistor connected to a constant potential.

According to the present invention, it is possible to reliably increase the rate of fall of the output voltage without increasing current consumption.

Embodiment An embodiment of the present invention is shown in FIG. 1 and will be explained. In Figure 1, 1 is the positive power supply terminal, 2 is the input terminal, and 3
is the bias terminal, 4 is the ground terminal, and 5 is the first NPN)
transistor, 6 is an output terminal, 7 is a second NPN transistor, 8 is a first resistor, 9 is a capacitor, 10 is a constant current source,
11 is a second resistor, and 12 is a PNP transistor.

Even in this configuration, if the input voltage suddenly drops, the first
The NPN transistor 5 is in a cut-off state. At this time, however, the collector current of the PNP transistor 12 increases, and the base current of the second NPN transistor 12 increases via the capacitor 9.

As a result, the current value increases and the output voltage drops rapidly. In addition, in the steady state, the second NP is
N) Current consumption does not increase because it is possible to prevent the mousse current from flowing to the Langistaph. Therefore, with this configuration, it is possible to reliably increase the rate of fall of the output voltage without increasing current consumption.

Note that the same effect can be obtained by using a P-type MOS transistor 13 instead of the PNP transistor 12 as shown in FIG. Further, the polarity of each transistor may be reversed from that of the embodiments shown in FIGS. 1 and 2.

Effects of the Invention As described above, according to the present invention, it is possible to reliably increase the rate of fall of the output voltage without increasing current consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an emitter-flat circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an emitter-flat circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional emitter-flat circuit.
FIG. 3 is a circuit diagram of a lower circuit. 1...Positive power supply terminal, 2...Input terminal, 3...Bias terminal, 4...Ground terminal, 5...No. 1 NPN transistor, 6...
...Output terminal, 7...2nd NPN) transistor, 8...1st resistor, 9...
Capacitance, 10... constant current source, 11... second resistor, 12-...-PNP) transistor, 13...
...P-type MOS transistor.

Claims (2)

[Claims] (1) A first conductivity type transistor whose emitter is connected to a first constant potential via a second resistor, whose base is connected to an input terminal, and whose collector is connected to a second constant potential via a constant current source. a first second conductivity type transistor having a collector connected to the first constant potential, a base connected to the input terminal, and an emitter connected to the output terminal; a second transistor connected to the second constant potential through a resistor, a base connected to a third constant power source, and connected to a collector of the transistor of the first conductivity type through a capacitor; An emitter follower circuit consisting of a conductive type transistor. (2) A MOS transistor whose source is connected to a first constant potential, whose gate is connected to an input terminal, and whose drain is connected to a second constant potential via a constant current source, and whose collector is connected to the first constant potential. a first transistor whose base is connected to the input terminal and whose emitter is connected to the output terminal; and a first transistor whose collector is connected to the output terminal and whose emitter is connected to the second constant potential via a resistor and whose base is connected to the second constant potential. and a second transistor connected to the constant power source of No. 3 and connected to the drain of the MOS transistor via a capacitor.