JPH03257557A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPH03257557A
JPH03257557A JP2056841A JP5684190A JPH03257557A JP H03257557 A JPH03257557 A JP H03257557A JP 2056841 A JP2056841 A JP 2056841A JP 5684190 A JP5684190 A JP 5684190A JP H03257557 A JPH03257557 A JP H03257557A
Authority
JP
Japan
Prior art keywords
codes
rom
code
circuit
bytes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2056841A
Other languages
Japanese (ja)
Inventor
Tetsuya Nishikubo
西久保 哲也
Yasuhiro Minamide
南出 靖宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2056841A priority Critical patent/JPH03257557A/en
Publication of JPH03257557A publication Critical patent/JPH03257557A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE:To protect the secrecy of a program by attaining a constitution where a coincidence detecting circuit outputs a grant signal when the coincidence is secured between the ROM codes and the external input codes by an amount equal to the number of bytes set previously. CONSTITUTION:A coincidence detecting circuit 6 compares the codes equivalent to three bytes and outputs an overflow signal only when the coincidence is secure among all codes. Then the circuit 6 is set in a test mode when the logic level of a test terminal 3 is set high. When the terminal 3 is set at a high level, the addresses of a ROM 1 are successively inputted to the circuit 6 at and after an address O. At the same time, the codes equal to the ROM codes equivalent to three bytes are successively inputted via an external input port 5 synchronously with input of the ROM codes. Thus the overflow signal given from the circuit 6 is inputted to a control circuit 2, and the ROM codes are outputted to an external output port 4 at and after the 4th code in a ROM code output state.

Description

【発明の詳細な説明】 (産業上の利用分野〕 この発明は、読み出し専用メモリを内蔵したマイクロコ
ンピュータに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microcomputer with a built-in read-only memory.

〔従来の技術〕[Conventional technology]

第2図に従来のマイクロコンピュータにかけるブロック
図を示す。図にかいて、(1)は読み出し専用メモリ(
J2を下ROMと起す) s (2)はFIOMコード
の出力を制御する制御回路、(8)は外部からテストモ
ードに切り換えるためのテスト端子、(4)は外部出力
ポートである。
FIG. 2 shows a block diagram of a conventional microcomputer. In the figure, (1) is read-only memory (
(2) is a control circuit that controls the output of the FIOM code, (8) is a test terminal for externally switching to the test mode, and (4) is an external output port.

次に動作について説明する。テスト端子(8)に、テス
トモードに入るための論理レベルを入力すると、制御回
路(2)によりROM (1)の内容がO番地から順に
外部出力ポート(4)にE’lOMコードが出力される
Next, the operation will be explained. When the logic level for entering the test mode is input to the test terminal (8), the control circuit (2) outputs the contents of the ROM (1) in order from address O to the external output port (4) as an E'lOM code. Ru.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のマイクロコンピュータは以上のように構成すれて
いるので、テスト端子の論理レベルにより簡単にROM
コードを読み出すことができるため機密を知られてしま
うという問題点があった。
Conventional microcomputers are configured as described above, so it is easy to read ROM by changing the logic level of the test terminal.
There was a problem that since the code could be read out, confidential information could be revealed.

この発明は上記のような問題点を解消するためになされ
たもので、ROMコードを知らない人に簡単にROMコ
ードを知られないようにするマイクロコンピュータを得
ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a microcomputer that can easily hide the ROM code from those who do not know the ROM code.

〔課題を解決するための手段〕[Means to solve the problem]

こ(2)Q明に−>けるマイクロコンピュータは、40
Mコードを読み出す場合に、ROMコードと同期して予
め決めてかいたバイト数だけ一致するコ−ドを外部から
入力しないとROMコードを読み出せないようにしたも
のである。
The microcomputer used in this (2) Q Ming is 40
When reading the M code, the ROM code cannot be read unless a code that matches the ROM code by a predetermined number of bytes is input from the outside in synchronization with the ROM code.

〔作用〕[Effect]

この発明にかける一致検出回路は、予め設定したバイト
数だけROMコードと外部入力コードが一致すると許可
信号を出力し、ROMコードを読み出せるようにする。
The match detection circuit according to the present invention outputs a permission signal when the ROM code and external input code match by a preset number of bytes, allowing the ROM code to be read.

〔実施例〕〔Example〕

以下に、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図にかいて、(1)ないしく4)は第2図の従来例
に示したものと同等であるので説明を省略する。
In FIG. 1, items (1) to 4) are the same as those shown in the conventional example of FIG. 2, so their explanation will be omitted.

(6)は外部入力ポート、(6)はROM (1)と外
部穴カポ−)(15!から入力されるコードを比較し一
致を検出する一致検出回路である。
(6) is an external input port, and (6) is a coincidence detection circuit that compares the codes input from the ROM (1) and the external hole capo (15!) and detects a coincidence.

ここで一致検出回路(6)は3バイト分のコードを比較
して、すべてが一致した時のみオーバーフォロー信号を
出力するものとし、テスト端子(8)の論理レベルがH
ighになった時にテストモードに入るようにする。
Here, the match detection circuit (6) compares 3 bytes worth of codes and outputs an overfollow signal only when all codes match, and the logic level of the test terminal (8) is set to H.
Enter test mode when it becomes ``high''.

次に動作について説明する。Next, the operation will be explained.

マイクロコンピュータを動作状態とし、テスト端子(8
)をEigh レベルにするとROM (1)の0番地
から順に、一致検出回路(6)に入力される。この時こ
のROMコードが入力されるのと同期して順に3バイト
分のROMコードと同じコードを外部入力ポート(5)
から入力すると、一致検出回路(6)からのオーバーフ
ォロー信号が制御回路(2)に入力され、ROMコード
出力状魅となり、4バイト目のROMコードから外部出
力ポート(4)に出力される。
Put the microcomputer into operation state and connect the test terminal (8
) is set to Eight level, the data is sequentially input to the coincidence detection circuit (6) starting from address 0 of the ROM (1). At this time, in synchronization with the input of this ROM code, the same code as the 3-byte ROM code is input to the external input port (5).
When input from the 4th byte, the overfollow signal from the coincidence detection circuit (6) is input to the control circuit (2), becomes the ROM code output state, and is output from the 4th byte of the ROM code to the external output port (4).

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、テストモードによっ
て、正しいROMコードを知らない人がROMコードを
読み出すことが出来なくなり、プログラムの機密を保護
することができる効果がある。
As described above, according to the present invention, the test mode prevents a person who does not know the correct ROM code from reading out the ROM code, thereby protecting the confidentiality of the program.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるマイクロコンピュー
タのブロック図、第2図は従来のマイクロコンピュータ
のブロック図である。 (1)はROM、(2)は制御回路、(8)はテスト端
子、(4)は外部出力ポート、+5)は外部入力ポート
%(6)は一致検出回路であろう なか、図中、同一符号は同一 又は相当部分を示す。
FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional microcomputer. (1) is the ROM, (2) is the control circuit, (8) is the test terminal, (4) is the external output port, +5) is the external input port, and (6) is the match detection circuit. The same symbols indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 読み出し専用メモリから出力されるコードと、それと同
期させて外部より入力するコードとを1バイト以上の予
め決められたバイト数比較を行う一致検出回路と、この
回路からの一致信号により外部に読み出し専用メモリか
ら出力されるコードを出力するか否かを制御する制御回
路を備えたマイクロコンピュータ。
A match detection circuit that compares the code output from the read-only memory and the code input from the outside in synchronization with the code by a predetermined number of bytes or more, and a match signal from this circuit that allows the code to be read-only to the outside. A microcomputer equipped with a control circuit that controls whether or not to output the code output from memory.
JP2056841A 1990-03-07 1990-03-07 Microcomputer Pending JPH03257557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2056841A JPH03257557A (en) 1990-03-07 1990-03-07 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2056841A JPH03257557A (en) 1990-03-07 1990-03-07 Microcomputer

Publications (1)

Publication Number Publication Date
JPH03257557A true JPH03257557A (en) 1991-11-18

Family

ID=13038629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2056841A Pending JPH03257557A (en) 1990-03-07 1990-03-07 Microcomputer

Country Status (1)

Country Link
JP (1) JPH03257557A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200287A (en) * 1993-12-16 1995-08-04 Internatl Business Mach Corp <Ibm> Protected program-type memory cartridge and computer system using it

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200287A (en) * 1993-12-16 1995-08-04 Internatl Business Mach Corp <Ibm> Protected program-type memory cartridge and computer system using it

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