JPH03257557A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPH03257557A
JPH03257557A JP2056841A JP5684190A JPH03257557A JP H03257557 A JPH03257557 A JP H03257557A JP 2056841 A JP2056841 A JP 2056841A JP 5684190 A JP5684190 A JP 5684190A JP H03257557 A JPH03257557 A JP H03257557A
Authority
JP
Japan
Prior art keywords
codes
rom
circuit
set
coincidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2056841A
Inventor
Yasuhiro Minamide
Tetsuya Nishikubo
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2056841A priority Critical patent/JPH03257557A/en
Publication of JPH03257557A publication Critical patent/JPH03257557A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To protect the secrecy of a program by attaining a constitution where a coincidence detecting circuit outputs a grant signal when the coincidence is secured between the ROM codes and the external input codes by an amount equal to the number of bytes set previously.
CONSTITUTION: A coincidence detecting circuit 6 compares the codes equivalent to three bytes and outputs an overflow signal only when the coincidence is secure among all codes. Then the circuit 6 is set in a test mode when the logic level of a test terminal 3 is set high. When the terminal 3 is set at a high level, the addresses of a ROM 1 are successively inputted to the circuit 6 at and after an address O. At the same time, the codes equal to the ROM codes equivalent to three bytes are successively inputted via an external input port 5 synchronously with input of the ROM codes. Thus the overflow signal given from the circuit 6 is inputted to a control circuit 2, and the ROM codes are outputted to an external output port 4 at and after the 4th code in a ROM code output state.
COPYRIGHT: (C)1991,JPO&Japio
JP2056841A 1990-03-07 1990-03-07 Microcomputer Pending JPH03257557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2056841A JPH03257557A (en) 1990-03-07 1990-03-07 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2056841A JPH03257557A (en) 1990-03-07 1990-03-07 Microcomputer

Publications (1)

Publication Number Publication Date
JPH03257557A true JPH03257557A (en) 1991-11-18

Family

ID=13038629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2056841A Pending JPH03257557A (en) 1990-03-07 1990-03-07 Microcomputer

Country Status (1)

Country Link
JP (1) JPH03257557A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200287A (en) * 1993-12-16 1995-08-04 Internatl Business Mach Corp <Ibm> Protected program type memory cartridge and computer system using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200287A (en) * 1993-12-16 1995-08-04 Internatl Business Mach Corp <Ibm> Protected program type memory cartridge and computer system using the same

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