JPH0325673A - Digital signal processor - Google Patents

Abstract

PURPOSE:To attain the connection to such a circuit as a public circuit, etc., which treats an 8-bit sound signal nonlinearly quantized and to reduce the program value together with improvement of the processing speed with a digital signal processor by using two arithmetic parts which perform the computing operations based on the data of prescribed bits received from the 1st and 2nd buses and sends the computing results of prescribed bits to both buses respectively. CONSTITUTION:An arithmetic part 6 receives the data of prescribed bits from the 1st and 2nd buses 1 and 2 of prescribed bits to perform the multiplication based on a prescribed nonlinear rule and sends the multiplication result of a prescribed bit to the 2nd bus 2. At the same time, an arithmetic part 7 performs the computing operations including the addition by a nonlinear rule based on the data of prescribed bits received from both buses 1 and 2 and sends the computing result of a prescribed bit to the 1st bus 1. Thus it is possible to obtain a digital signal processor which can also be applied to an 8-bit signal quantized and treated by a public circuit network, etc., and can reduce the power consumption owing to the omission of the linear/nonlinear conversion and the decrease of the number of necessary circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processor that handles data related to audio signals.

[Conventional technology]

This type of digital signal processor (DSP)
Some systems have been put into practical use that have built-in adders and multipliers that handle linearly expressed numerical values in floating-point or fixed-point format.

An example of such a digital signal processor is shown in Figure 4. This conventional digital signal processor is of a 16-bit fixed point format. This conventional digital signal processor has 16
Bit data path 21. 22, an instruction storage section 23, a general-purpose register 24, a memory section 25, a multiplication section 26, an addition section 27, and an input/output section 28:29. Furthermore, the instruction storage unit 23 includes an instruction storage memory 23A,
It consists of a program counter 23B and a stack 23C. The memory section 25 has 16 bits/word RAM (
Ran-dota Access Memory) 25
A and a 16-bit/word data storage memory 25B.゛The multiplication unit 26 includes a 16-bit multiplier register 26A and a 16-bit multiplicand register 26B.
and a multiplier 26C. The calculation unit 27 includes a selection circuit 27A, a 16-bit×2 register 27B, and an addition I! ALU (Ar
ithmeLic and Logic Unit)2
It is composed of 7C.

The input/output section 28 is composed of a serial input circuit 28A and a serial output circuit 28B, and the input/output section 29 is composed of a serial input circuit 28A and a serial output circuit 28B.
It consists of a parallel input circuit 29A and a parallel output circuit 29B.

By the way, when expressing a human voice waveform digitally,
In linear binary representation, if quantization is performed to about 12 and 13 bits, there is almost no loss in sound quality, so conventional digital signal processors with this structure can process data related to audio waveforms. can.

[It'M to be solved by the invention] The conventional digital signal processor described above is
Perform operations on linearly quantized numbers. On the other hand, CCITT
(International Telegraph and Telephone Advisory Committee) Recommendation G. If quantization is performed according to the nonlinear law called μ-Law or A-La- specified in 711, l2~ as mentioned earlier in sbttl childization
It is well known that sound quality equivalent to 13-bit linear quantization can be obtained. In most cases, this 8-bit signal is transmitted even on public telephone networks. When a conventional digital signal processor is connected to this public line, it is necessary to perform arithmetic processing on input data after nonlinear/linear conversion, and output the result after linear/nonlinear conversion. Therefore, it is necessary to provide an external conversion circuit to the digital signal processor or to perform the conversion process using the software of the digital signal processor.

Furthermore, since the internal processing of conventional digital signal processors is performed by linear conversion,
This involves bit operations, which has the disadvantage of increasing memory capacity and current consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processor that eliminates such drawbacks, does not require linear/nonlinear conversion, and can reduce circuitry and power consumption.

[! Means to solve the problem]

In the first invention, a first bus having a predetermined number of bits accommodates a memory section that accommodates data of a predetermined bit, a storage section that stores data processing instructions, and an input/output section that inputs and outputs data. A digital signal processor that performs an operation, which receives data of a predetermined bit from a second bus of a predetermined bit and the first bus, performs multiplication according to a predetermined nonlinear rule, and performs multiplication of a predetermined bit. an arithmetic unit that sends a result to the second bus; and an arithmetic unit that performs an arithmetic operation including addition according to the nonlinear rule based on predetermined bit data from the first and second buses, and transmits the predetermined bit arithmetic result to the predetermined bit data. It is characterized by having an arithmetic unit that sends data to the first bus.

In the second invention, a first bus of a predetermined bit accommodates a memory section that accommodates data of a predetermined bit, a storage section that stores a data processing instruction, and an input/output section that outputs data,
A digital signal processor that performs arithmetic operations on data, characterized by having an arithmetic unit that operates on data from the first bus using bit data including predetermined bits according to a predetermined nonlinear rule. There is.

In the third invention, a bus of a predetermined bit of flame 1 accommodates a memory section that accommodates data of a predetermined bit, a storage section that stores instructions for data processing, and an input/output section that outputs data,
A digital signal processor that performs data operations, which receives data of predetermined bits from a third bus of bits containing predetermined bits and the first bus, and performs multiplication according to a predetermined nonlinear rule. an arithmetic unit that sends bit data including a predetermined bit to the third bus; and a predetermined bit data from the first bus and a bit data including the predetermined bit from the third bus. and an arithmetic unit that performs an arithmetic operation including addition according to the nonlinear rule based on the above-mentioned nonlinear rule, and sends the arithmetic result of a predetermined bit to the first bus. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a structural diagram showing an embodiment of the present invention. The digital signal processor of this embodiment performs arithmetic processing on data related to audio signals. This digital signal processor is connected to 8-bit data buses 1 and 2 and data bus 1, and is connected to an instruction storage section 3 storing a program and data bus 1, and has an 8-bit x 2 general-purpose A register 4, a memory section 5 connected to the data bus l and holding data, a multiplication section 6 connected to the data bus l, and a multiplication section 6 connected to the data bus 1 and further connected to the data bus 2. It consists of an arithmetic unit 7 connected to the data bus 1, and input/output units 8 and 9 connected to the data bus 1 for outputting data.

Furthermore, the instruction storage unit 3 includes an instruction storage memory 3A in which a program is written and sends instructions to the data bus l;
It consists of a program counter 3B that sends addresses to the instruction storage memory 3A, and a stack 3C connected to the program counter 3B. The memory unit 5 receives an address from the data bus l,
An 8-bit/word RAM (Random Access Memo) that transmits data with the data bus l.
ry) 5A and the address is entered manually from the data bus l,
It consists of an 8-bit/word data storage memory 5B that sends data to the data bus 1. The multiplier 6 includes an 8-bit multiplier register 6A that receives a multiplier from the data bus 1, an 8-bit multiplicand register 6B that receives the multiplicand from the data bus 1, and a multiplicand that receives the multiplicand from the multiplier register 6A and the multiplicand from the multiplicand register 6B. and a multiplier 6C that performs nonlinear multiplication and sends 8-bit product data to the data bus 2. The arithmetic unit 7 includes a selection circuit 7A that selects data from the data bus 1 or 2, an 8-bit x 2 register 7B that transmits data to and from the data bus 1, and a selection circuit 7A that selects data from the selection circuit 7A and a register 7B. ALU (Arithmetic and
Logic Unit) 7C. The input/output section 8 includes a serial human power circuit 8A connected to the data bus 1 to which serial data and a shift clock are input, and a serial human circuit 8A connected to the data bus 1 to which the shift clock is input and outputs serial data. It is composed of output circuit 8B. The input/output section 9 consists of a parallel human circuit 19A connected to the data bus 1 and inputting 8-bit parallel data, and a parallel output circuit 9B connected to the data bus 1 outputting 8-bit parallel data. I'm being intimidated. Next, the operation of such a digital signal processor will be explained.

This digital signal processor sequentially reads and executes programs written in the instruction storage memory 3A according to instructions from the program counter 3B. The commands include various memories and people connected to the internal bus, output circuits,
Various transfer instructions between arithmetic circuits are available. for example,
The data stored at address 100 of rRAM5A is
It is possible to execute the command "Load into multiplicand register 6B, which is one input of multiplier 6C."

When a quantized signal waveform is input to this digital signal processor, a program corresponding to the purpose is prepared in the instruction storage memory 3A, and the signal is processed by digital signal processing such as filtering and Fourier transformation. It is possible to output. Such processing is completely common in conventional digital signal processors, but in the conventional technology, multipliers and ALUs perform operations on 16-bit linearly quantized numerical values. On the other hand, in the digital signal processor of this embodiment, CCrT
T RecommendationG. The difference is that it performs calculations on quantized numbers using the nonlinear law shown in 711, that is, the 8-bit μ-Law law. Here, we will explain the numerical values quantized using the μ-Law law. The numerical value of μ-Law law is expressed in 8 bits, which is expressed as b, ~
Let it be b0.

Further, b indicates polarity, and 1 means positive and 0 means negative.

b& bs b. indicates the segment number (k), 1
11 means segment 1, and 000 means segment 8. bs bt bt be indicates the step number (m), and 11l1 means step 1, and 0000 means step 16. Therefore, if we convert it into a linear expression, it becomes 下2.

Absolute value of linear value -2"X (m+15.5) -33 The multiplier 6C, which operates on 8-bit data in such an expression format, has a total of 16 bits of address, including 8 bits of the multiplier and 8 bits of the multiplicand. ROM (ReaOnly
It is clear that the ROM capacity can be further reduced by converting a portion into a logic circuit. Also, the adder is exactly the same as the multiplier.

By the way, when digital signal processing is performed using the digital signal processor shown in Figure 1, both multiplication and addition results are converted to 8 bits, so truncation occurs during calculation, and this truncation accumulates. This may result in large calculation errors.

FIG. 2 is a diagram showing an example of the second invention used in such a case. This adder. The multiplier attempts to expand and store the lower digit value, which is rounded down to 8 bits, to 9 bits or more according to the μ-Law rule. This adder. In the multiplier, 8 bits are expanded to 11 bits. That is, the adder and multiplier have 8 bits b1 to b, and 3 bits b-. -b. ．． An 11-bit number with , added is input. Then, the adder and multiplier process these numerical values and output an 11-bit numerical value.Letting the number of b-+b-zb-3 be n, and converting the numerical value into a linear representation, it becomes lower 2.

Absolute value of linear value = 2"x (m+15.5) +2t'
Xn-33 In this way, this adder and multiplier expands 8 bits to 11 bits by extended numerical expression. Note that when using an unexpanded 8-bit pLaw law value as an input numerical value, it is sufficient to assume that each bit of the expanded part is zero. Such adders and multipliers can be easily realized by a combination of ROM and logic circuits as in the previous example, and A-1 and ah techniques can also be applied.

FIG. 3 is a configuration diagram showing an example of the third invention. The digital signal processor of this embodiment is
An 8-bit data bus 11, a 13-bit data bus 12, an instruction storage section 13 connected to the data bus 11 and storing a program, and an 8-bit x 2 general-purpose register 14 connected to the data bus 1l. and data bus 1l
a memory unit 15 connected to the data bus 11 and holding data; a multiplication unit 16 connected to the data bus 11;
l and further connected to the multiplier l via the data bus l2.
an input/output section 18 connected to the data bus 11 and inputting and outputting data. It is made up of 19. Further, the instruction storage section l3 is connected to an instruction storage memory 13A in which a program is written and sends instructions to the data bus 1l, a program counter 13B that sends an address to the instruction storage memory 13A, and a program counter 13B. It is configured with stack 13C. The memory section 15 includes an 8-bit/word RAM 15A to which an address is input from the data bus 11 and transmits data to the data bus 11, and an 8-bit/word RAM 15A to which an address is input from the data bus 11 and transmits data to the data bus 11. It is composed of a word data storage memory 15B.

The multiplier 16 includes an 8-bit multiplier register 16A that receives a multiplier from the data bus 11, an 8-bit multiplicand register 16B that receives a multiplicand from the data bus 11, and a multiplicand between the multiplier from the multiplier register 16A and the multiplicand from the multiplicand register 16B. , and a multiplier 16c that performs nonlinear multiplication and sends 13-bit product data to the data bus 2.

The arithmetic unit 17 includes a selection circuit 17A that selects data from the data bus 11 or l2, a 13-bit x 2 register 17B that transmits data to and from the data bus 11, and a selection circuit 17A that selects data from the selection circuit 17A and a register 17B. AI that performs operations including non-linear addition with data. , U17C
It is strictly advisable to do so.

The input/output unit 18 includes a serial input circuit 18A connected to the data bus 1l, to which serial data and a shift clock are input, and a serial input circuit 18A connected to the data bus 11, to which the shift clock is input and outputs serial data. It is composed of an output circuit 18.

The input/output section 19 is connected to the data bus 11 and includes a parallel input circuit 19A into which 8-bit parallel data is input.
and a parallel output circuit 19B connected to the data bus 1 and outputting 8-bit parallel data.

A digital signal processor having such a structure is an example in which 8 bits are expanded to i3 bits as an extended representation. In other words, instead of expanding the memory section, input/output section, registers, data path, etc. to 13 bits,
A register 17 for temporarily storing the output of the multiplier 16, the input/output of the ALU 17C including the addition function, and the addition result.
Since only B is expanded, the entire data bus 11 and memory remain in an 8-bit configuration. Note that the 13-bit structure register (
When data is transferred from the accumulator 17B to the memory or output circuit, the portion exceeding 8 bits is discarded. Therefore, even if this digital signal processor is applied to digital signal processing where intermediate results of operations must be stored in memory, the accumulation of truncation errors is unavoidable. However, in this digital signal processor, accumulator 1
By taking advantage of the fact that there are two 7Bs, it is possible to leave the calculation in the accumulator 17B without transferring it to the memory during the calculation, and if the program is devised so that only the final result of the calculation is transferred to the memory or output circuit, the error can be reduced. There is no IAm. In this way, including digital numerical adders and multipliers, the input/output of the adder and the human output of the multiplier are all CCI
TT Recommendation G. μ-La rule or A-L shown in 711
It is possible to provide a digital signal processor with an aw-law Bbit number.

It also includes an adder and a multiplier for digital numbers, and the input/output of the adder and the input/output of the multiplier are all digital numbers of 9 bits or more, and the upper 8 bits of the digital number of 9 bits or more are CCIT numbers. Recommendation G. It is possible to provide a digital signal processor that is μ-La-law or ALa-law as shown in 711.

Furthermore, digital value adders, multipliers, data memories, logical operators, registers, and input circuits. It includes an output circuit and a data path connecting them, and the adder and multiplier have the above characteristics, and only the part of the data path that connects the adder, multiplier, and register is a bus of 9 bits or more. , the other datapath can provide a digital signal processor that is an 8bi-bus.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to perform linear/nonlinear conversion when connecting to a line that handles 8-bit nonlinear quantized audio signals, such as a public line. Compared to realizing linear/nonlinear conversion using hardware, this allows for a reduction in circuitry, and compared to realizing linear/nonlinear conversion using software, the amount of programs can be reduced.
It has the effect of improving processing speed.

Furthermore, since the internal input/output section, memory section, etc. only need to have an 8-bit structure, for example, there is an effect of reducing the number of circuits and reducing power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the first invention, FIG. 2 is an explanatory diagram of the adder and multiplier portions of a digital signal processor implementing the second invention, and FIG. 4 is a structural diagram showing an example of the third invention, and FIG. 4 is a structural diagram showing an example of a conventional digital signal processor. 1, 2... Data path 3... Instruction storage section 4... General purpose register 5... Memory section 6... Multiplying section 7... Arithmetic section 8 , 9... input/output section

Claims (3)

[Claims] (1) A first bus with a predetermined number of bits accommodates a memory section that stores data of a predetermined bit, a storage section that stores data processing instructions, and an input/output section that inputs and outputs data, and performs data operations. A digital signal processor that receives data of predetermined bits from a second bus of predetermined bits and the first bus, performs multiplication according to a predetermined nonlinear rule, and converts the multiplication result of the predetermined bits into the data of the predetermined bits. an arithmetic unit that sends data to a second bus; and performs an arithmetic operation including addition according to the nonlinear rule based on predetermined bit data from the first and second buses, and transfers the predetermined bit arithmetic result to the first bus. A digital signal processor comprising: an arithmetic unit that sends signals to a bus; (2) A first bus of a predetermined bit accommodates a memory section that accommodates data of a predetermined bit, a storage section that stores data processing instructions, and an input/output section that inputs and outputs data, and performs data operations. A digital signal processor, characterized in that it has an arithmetic unit that operates on data from the first bus using bit data including a predetermined bit according to a predetermined nonlinear rule. processor. (3) A first bus of a predetermined bit accommodates a memory section that accommodates data of a predetermined bit, a storage section that stores data processing instructions, and an input/output section that inputs and outputs data, and performs data operations. A digital signal processor, comprising: a third bus of bits including a predetermined bit; and a third bus of bits including the predetermined bit; an arithmetic unit that sends the data to the third bus; and an arithmetic unit that performs addition according to the nonlinear rule based on the predetermined bit data from the first bus and the bit data including the predetermined bit from the third bus. and an arithmetic unit that performs an arithmetic operation including the following and sends the arithmetic result of a predetermined bit to the first bus.