JPH03256365A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH03256365A
JPH03256365A JP5424390A JP5424390A JPH03256365A JP H03256365 A JPH03256365 A JP H03256365A JP 5424390 A JP5424390 A JP 5424390A JP 5424390 A JP5424390 A JP 5424390A JP H03256365 A JPH03256365 A JP H03256365A
Authority
JP
Japan
Prior art keywords
film
insulating film
silicon
silicon film
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5424390A
Other languages
Japanese (ja)
Inventor
Takashi Itoga
隆志 糸賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5424390A priority Critical patent/JPH03256365A/en
Publication of JPH03256365A publication Critical patent/JPH03256365A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To arrange that the inclination of an electron energy band in the depth direction directly under a gate insulating film becomes gentle and that a channel current flows even in a deep part of a silicon film whose influence by scattering is small by a method wherein a patterned conductive film of Al or the like and an insulating film are formed sequentially on a transparent glass substrate and the silicon film is formed on the insulating film to form a transistor. CONSTITUTION:A P-type polysilicon film 4 doped with boron is formed directly above an Al film 2 via a first insulating film 3 by an SiO2 film which has been arranged and installed on the whole surface of a transparent glass substrate 1 including the Al film 2 which has been arranged and installed in an element formation region S of the substrate 1. A gate electrode 5 of polysilicon doped with phosphorus at about 1020cm-3 which can form a channel on the p-type polysilicon film by applying a voltage is formed, via a gate insulating film 47, on a part directly above the central part of the silicon film. An Al interconnection part 6 reaching both end parts of the polysilicon film 4 is formed by passing a second insulating film 7 as an interlayer insulating film which has been arranged and installed, so as to cover the gate electrode, on the whole surface of the first insulating film 3 including the p-type polysilicon film 4.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は半導体装置およびその製造方法に関し、更に詳
しくは半導体装置を製造する分野で利用されるガラス基
板等の絶縁体基板上に半導体層である多結晶シリコン薄
膜を配設してむるWIllEトランジスタおよびその形
成方法に関するものである。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, it relates to a semiconductor layer on an insulating substrate such as a glass substrate used in the field of manufacturing semiconductor devices. The present invention relates to a WIllE transistor in which a polycrystalline silicon thin film is disposed, and a method for forming the same.

(ロ)従来の技術 従来より石英やガラス基板等の非晶質基板上にアモルフ
ァス若しくは多結晶等の非単結晶シリコン薄膜を形成し
た後、炉アニール等を行って多結晶または大結晶粒径の
シリコン薄膜を作製する技術が提業されている。
(b) Conventional technology Conventionally, after forming an amorphous or polycrystalline non-single crystal silicon thin film on an amorphous substrate such as a quartz or glass substrate, furnace annealing or the like is performed to form a polycrystalline or large crystal grain size film. Techniques for producing silicon thin films have been proposed.

このシリコン薄膜から形成した薄膜トランジス夕は、液
晶デイスプレィを動作する上で高度な性能が要求され、
盛んに研究されている。
Thin film transistors formed from this silicon thin film are required to have high performance when operating liquid crystal displays.
It is being actively researched.

従来、第3図に示すNチャネルMOSFET (TPT
)のように、透明ガラス基板21上に直接シリコン膜2
2が配設された構造のものが提案されている。
Conventionally, an N-channel MOSFET (TPT
), the silicon film 2 is directly deposited on the transparent glass substrate 21.
2 has been proposed.

なお、23はシリコン膜22の上面側(上方)にゲート
絶縁膜26を介して配設されたIQI?Cm−”程度の
不純物をドープしたポリシリコンのゲート電極であり、
24は層間絶縁膜25を貫通してシリコン膜22に至る
メタル配線部である。
Note that 23 is an IQI? It is a polysilicon gate electrode doped with impurities of about Cm-",
24 is a metal wiring portion that penetrates the interlayer insulating film 25 and reaches the silicon film 22.

この構造のものでは、シリコン膜22をその膜厚をto
oo人程度に薄く形成すると、数tooo人程度の厚さ
の時に比べて電界効果移動度(以下、移動度という)が
上昇し、性能がよい薄膜トランジスタが得られることが
知られている。これはシリコン膜22を薄く形成すると
ゲート絶縁膜26直下の電子のエネルギーバンドの勾配
が緩やかになり、チャネルがシリコン1122の深い処
まで形成されるために電荷の表面散乱が少なくなるため
だといわれている(日経マイクロデバイス1988年3
月1No、33 P、35〜37)。
In this structure, the thickness of the silicon film 22 is
It is known that if it is formed thinly for the OO person, the power effect transfer (hereinafter referred to as the degree of movement) will increase compared to the thickness of several TOOO people, and a thin film transistor with good performance will be obtained. This is said to be because when the silicon film 22 is formed thin, the gradient of the energy band of electrons directly under the gate insulating film 26 becomes gentler, and the channel is formed deep into the silicon 1122, resulting in less surface scattering of charges. (Nikkei Microdevice, March 1988)
Month 1 No. 33 P. 35-37).

第5図は第3図の構造を有するNチャネルMOSFET
のゲート絶縁膜直下の深さ方向の電子のエネルギーを示
す図てめり、チャネルが形成されている場合を示してい
る。第5図からエネルギーバンドEc、EA、Evの傾
きが急峻であることか分かる。そのため、チャネルを流
れろ電荷は表面散乱の影響を受は易い。
Figure 5 shows an N-channel MOSFET with the structure shown in Figure 3.
This diagram shows the electron energy in the depth direction directly under the gate insulating film, and shows the case where a channel is formed. It can be seen from FIG. 5 that the slopes of the energy bands Ec, EA, and Ev are steep. Therefore, charges flowing through the channel are susceptible to surface scattering.

さらに移動度を上昇させるために、シリコン膜の下面側
(下方)にもゲート電極を形成したMOSFETの構造
を第4図に示す。
FIG. 4 shows the structure of a MOSFET in which a gate electrode is also formed on the lower surface side (below) of the silicon film in order to further increase the mobility.

すなわち、第4図において、薄膜トランジスタTは、例
えば、非単結晶のシリコン膜32の上・下両面側にそれ
ぞ膜上ゲート電極33、下ゲート電極34を形成し、そ
れによって上ゲート電極33の直下の深さ方向の電子の
エネルギーバンドの勾配を緩やかにし、薄膜トランジス
タの電子の高移動度化をおこなうようにしたものである
That is, in FIG. 4, the thin film transistor T has, for example, an upper gate electrode 33 and a lower gate electrode 34 formed on the upper and lower surfaces of a non-single crystal silicon film 32, respectively. The gradient of the electron energy band in the depth direction directly below is made gentler, thereby increasing the electron mobility of the thin film transistor.

(ハ)発明が解決しようとする課題 しかしこの方法て得あれろ薄膜トランジスタT:よ、特
に低温プロセスの場合には、シリコン膜32の上面のゲ
ート絶縁膜37のみならず下面のゲート絶h1膜36に
も上面のゲート絶縁膜37と同様に前処理、後処理を施
して絶縁@36の緻密化や界面単位密度の制御を行わね
ばならないのに加えて下ゲート電極34上の平坦化をお
こなうためのプロセスが非常に煩雑にむる。
(c) Problems to be Solved by the Invention However, what can be achieved with this method? Especially in the case of a low-temperature process, not only the gate insulating film 37 on the upper surface of the silicon film 32 but also the gate insulating film 37 on the lower surface Similarly to the gate insulating film 37 on the upper surface, pre-treatment and post-treatment must be performed on the upper gate insulating film 37 to make the insulation @ 36 denser and to control the interface unit density. The process becomes very complicated.

(ニ)課題を解決する几めの手段1f17−出この発明
は、透明ガラス基板と、その透明ガラス基板上の素子形
成領域に配設された導電膜と、その導電膜を含む透明ガ
ラス基板全面に配設されL第1絶縁膜と、その第1絶縁
膜を介して導電膜の直上に形成さr3た実質的に薄膜の
シリコン膜と、そのシリコン膜の中央部直上にゲート絶
縁膜を介して配設され、電圧の印加によってシリコン膜
上にチャネル部を形成しうるゲート電極と、シリコン叡
を含む第1絶縁膜上の全面にゲート電極を覆うように配
設された第2絶縁膜と、その第2絶縁膜を貫通してシリ
コン膜の両端部に至る配線部とからなる半導体装置が提
供される。
(D) Elaborate means for solving the problem 1f17-Depart This invention comprises a transparent glass substrate, a conductive film disposed in an element formation area on the transparent glass substrate, and an entire surface of the transparent glass substrate including the conductive film. a substantially thin silicon film formed directly above the conductive film via the first insulating film, and a gate insulating film disposed directly above the center of the silicon film. a gate electrode disposed on the silicon film and capable of forming a channel portion on the silicon film by applying a voltage; and a second insulating film disposed on the entire surface of the first insulating film including silicon to cover the gate electrode. , and a wiring portion that penetrates the second insulating film and reaches both ends of the silicon film.

すなわち、この発明は、シリコン膜の上面側にゲート電
極が配設された半導体装置であって、シリコン膜の下面
側に第1絶縁膜を介して導電膜が配設されたものであり
、シリコン膜下面のシリコン膜側の深さ方向の電子のエ
ネルギーバンドがベンディングを起こし、上面側のゲー
ト電極から電圧が印加されてチャネルが形成された時に
ゲート絶縁膜直下におけるシリコン膜の深さ方向の電子
のエネルギーバンドの傾きが緩やかになり、チャネルが
ゲート絶縁膜直下におけるシリコン膜の表面だけではな
く、シリコン膜の深いところまでわたって形成されるた
め、チャネルを流れる電荷が散乱を受は易いシリコン膜
表面のみならず、散乱をあまり受けないシリコン膜中を
も流れる。
That is, the present invention is a semiconductor device in which a gate electrode is disposed on the upper surface side of a silicon film, and a conductive film is disposed on the lower surface side of the silicon film via a first insulating film. The energy band of electrons in the depth direction of the silicon film side on the lower surface of the film causes bending, and when a voltage is applied from the gate electrode on the upper surface side and a channel is formed, the electrons in the depth direction of the silicon film directly under the gate insulating film The slope of the energy band becomes gentle, and the channel is formed not only on the surface of the silicon film directly under the gate insulating film, but also deep within the silicon film, so the charge flowing through the channel is easily scattered in the silicon film. It flows not only on the surface but also in the silicon film, which is not subject to much scattering.

このために、例えば、石英等の透明ガラス基板上に非単
結晶シリコン膜を形成して薄膜トランジスタのMOSF
ETを作った時、高い電界効果移動度が得られ、トラン
ジスタの性能向上を図ることができる。
For this purpose, for example, a non-single-crystal silicon film is formed on a transparent glass substrate such as quartz, and a MOSFET of a thin film transistor is formed.
When an ET is fabricated, high field effect mobility can be obtained and the performance of the transistor can be improved.

また、この発明:i上記半導体装置の形成方法として、
透明ガラス基板上の素子形成領域に所定パターンの導i
ll!を形成し、その導電膜を含む透明ガラス基板全面
に第1絶縁膜を形成し、その第■絶縁膜を介して導電膜
の直上に所定パターンのシリコン膜を形成し、そのシリ
コン膜の中央部直上にゲート絶縁膜を介して所定パター
ンのゲート電極を形成し、その後シリコン膜を含む第t
IIiA縁嘆上全面にゲート電極を覆うように第2絶#
膜を形成し、シリコン膜の両端部に至る配線部を第2絶
縁膜を貫通して形成した半導体装置の製造方法が提供さ
れる。
In addition, this invention: i As a method for forming the above semiconductor device,
A predetermined pattern of conductors is formed on the element formation area on the transparent glass substrate.
ll! A first insulating film is formed on the entire surface of the transparent glass substrate including the conductive film, a silicon film in a predetermined pattern is formed directly above the conductive film via the first insulating film, and a silicon film is formed in the center of the silicon film. A gate electrode of a predetermined pattern is formed directly above the gate insulating film, and then a t-th electrode including a silicon film is formed.
A second insulator is placed on the entire surface of the IIIiA edge to cover the gate electrode.
A method of manufacturing a semiconductor device is provided in which a film is formed and a wiring portion extending to both ends of the silicon film is formed by penetrating the second insulating film.

すなわち、この発明は、石英等の透明ガラス基板上方に
シリコン薄膜を形成し、そのシリコン薄膜にトランジス
タを作成して半導体装置を形成する際に、シリコン膜の
下に、薄い第1絶縁膜を介してパターニングした導電膜
を形成することによりシリコン膜下面のシリコン膜側の
深さ方向の電子エネルギーバンドがベンディングを起こ
し、適切なゲート電圧の印加によりチャネルが形成され
た時にゲート絶縁膜直下の深さ方向の電子のエネルギー
バンドの傾きが緩やかになることによってチャネルがシ
リコン膜中の深いところまで形成され、高い移動度を有
するMOSFETを形成することができる。
That is, this invention forms a silicon thin film above a transparent glass substrate such as quartz, and when forming a semiconductor device by forming a transistor on the silicon thin film, a thin first insulating film is placed under the silicon film. By forming a patterned conductive film, the electron energy band in the depth direction of the silicon film side on the lower surface of the silicon film bends, and when a channel is formed by applying an appropriate gate voltage, the depth directly below the gate insulating film Since the inclination of the electron energy band in the direction becomes gentle, a channel can be formed deep into the silicon film, and a MOSFET with high mobility can be formed.

この発明における透明ガラス基板としては、石英やアル
ミノ珪酸ガラス(A l *0s−S i O*−Rl
O:Rは1価のアルカリ)あるいはホウケイ酸ガラス(
B*Os  S i O*  RtO: Rは1価のア
ルカリ)が好ましいものとして挙げられる。
As the transparent glass substrate in this invention, quartz or aluminosilicate glass (A l *0s-S i O *-Rl
O:R is a monovalent alkali) or borosilicate glass (
B*OsSiO*RtO (R is a monovalent alkali) is preferred.

この発明における導電膜としては、AlやTiあるいは
W等の金属膜、WSt等の合金膜、さらにはポリシリコ
ンやゲルマニウム等の非金属の導電性膜が好ましいもの
として挙げられる。そして、膜厚は0.2〜1.0μm
が好ましく、0.5μmがより好ましい。
Preferred examples of the conductive film in the present invention include metal films such as Al, Ti, or W, alloy films such as WSt, and nonmetallic conductive films such as polysilicon and germanium. And the film thickness is 0.2 to 1.0 μm
is preferable, and 0.5 μm is more preferable.

この発明における第1絶縁膜としては、5ins膜ある
いは5isN*II等が好ましいものとして挙げられる
。その膜厚は、0.05〜1 、0gg+が好ましく、
0.1μ−がより好ましい。
Preferred examples of the first insulating film in the present invention include a 5ins film, 5isN*II, and the like. The film thickness is preferably 0.05 to 1.0 gg+,
0.1 μ- is more preferable.

この発明におけるシリコン膜の材料として:よ、非単結
晶や多結晶どち与のシリコンを用いても良く、その際の
不純物ドープのための材料は、公知のp型、n型不純物
が用いられ、そのドープ量は、10 ”〜10 ”am
−3が好ましい。
As the material for the silicon film in this invention, either non-monocrystalline or polycrystalline silicon may be used; in this case, the impurity doping material may be a known p-type or n-type impurity. , the doping amount is 10”~10”am
-3 is preferred.

この発明において、実質的に薄膜のシリコン膜とは、膜
厚が0.O1〜0.3μ−の薄膜のものを意味し、それ
によって電子の移動度を上昇させうる。
In this invention, a substantially thin silicon film is defined as having a film thickness of 0. It means a thin film of O1 to 0.3μ, which can increase the mobility of electrons.

このシリコン膜は、LPGVD (減圧化学気相成長)
法やPlasma CVD法等の公知の方法を用いて第
1絶縁膜上に薄膜形成できる。
This silicon film is made by LPGVD (low pressure chemical vapor deposition)
A thin film can be formed on the first insulating film using a known method such as a plasma CVD method or a plasma CVD method.

また、上記第!絶縁膜及び導電膜も公知技術を用いて形
成できる。
Also, the above! The insulating film and the conductive film can also be formed using known techniques.

この発明におけるゲート絶縁膜および第2絶縁膜として
はStow膜あるいは5isN+膜等が好ましいものと
して挙げられる。
As the gate insulating film and the second insulating film in this invention, a Stow film, a 5isN+ film, etc. are preferably used.

この発明におけるゲート電極としては、例えば、燐をI
 O”am−3ドープしたポリシリコンやAtあるいは
Tt等の導電性材料を用いるのが好ましい。
As the gate electrode in this invention, for example, phosphorus can be used as I.
It is preferable to use a conductive material such as O''am-3 doped polysilicon, At or Tt.

また、WSiを用いても良い。Alternatively, WSi may be used.

(ホ)実施例 以下図に示す実施例に基づいてこの発明を詳述する。な
お、これによってこの発明は限定を受けるものではない
(e) Examples The present invention will be described in detail below based on examples shown in the drawings. Note that this invention is not limited by this.

第1図において、Nチャネルlll0sFETは、石英
の透明ガラス基板(以下単に基板という)lと、その基
板上の素子形成領域Sに配設されたAI膜2と、そのA
1膜を含む基板1の全面に配設された5ins膜の第1
絶縁膜3と、その第1絶縁膜を介してAll12の直上
に形成された、厚さ2000人の薄膜で、ホウ素(B)
が10 ”am−”程度ドープされたp型ポリシリコン
膜4と、そのシリコン膜の中央部直上にゲート絶縁膜4
7を介して配役され、電圧の印加によってp型ポリシリ
コン膜上にチャネルを形成しうる1 g 10012程
度の燐をドープしたポリシリコンのゲート電極5と、p
型ポリシリコン膜4を含む第1絶縁膜3上の全面にゲー
ト電極5を覆うように配設された眉間絶縁膜としての第
2絶縁膜7と、その第2絶縁膜を貫通してポリシリコン
膜4の両端部に至るAIの配線tI56とから主として
なる。
In FIG. 1, an N-channel lll0sFET consists of a quartz transparent glass substrate (hereinafter simply referred to as a substrate) l, an AI film 2 disposed in an element formation area S on the substrate, and an
The first 5ins film is disposed on the entire surface of the substrate 1 including one film.
Boron (B) is a thin film of 2000 mm thick formed directly on the All 12 through the insulating film 3 and the first insulating film.
A p-type polysilicon film 4 doped with approximately 10 am− and a gate insulating film 4 directly over the center of the silicon film.
A gate electrode 5 made of polysilicon doped with about 1 g of phosphorus, which can form a channel on the p-type polysilicon film by applying a voltage, and a p
A second insulating film 7 as a glabellar insulating film is disposed on the entire surface of the first insulating film 3 including the polysilicon film 4 so as to cover the gate electrode 5, and a polysilicon film is formed by penetrating the second insulating film. It mainly consists of the AI wiring tI56 reaching both ends of the film 4.

このように、本実施例では、石英の基板上にシリコン膜
による薄膜トランジスタを形成する際に、シリコン膜の
下面に絶縁膜を介してパターニングしたAIのメタル層
を形成したものであり、以下その製造方法について説明
する。
As described above, in this example, when forming a thin film transistor using a silicon film on a quartz substrate, a patterned AI metal layer was formed on the bottom surface of the silicon film through an insulating film. Explain the method.

基板!上の素子形成領域Sに所定パターンのAt膜2を
スパッタ法で形成し、そのAt膜を含む基板全面に5i
nsの第1絶縁膜3をCVD法で形成し、その第1絶縁
膜を介してA1膜2の直上に所定パターンのポリシリコ
ン膜をLPCVD法で形成し、p型不純物をドープした
後そのp型ポリシリコン膜4の中央部直上にゲート絶縁
膜47を介して所定パターンのゲート電極5を形成し、
その後p型ポリシリコン膜4を含む第1絶縁膜上全面に
ゲート電極5を覆うように第2絶縁膜7を形成し、p型
ポリシリコン114の両端部に至るAlの配線部6を第
2絶縁膜7を貫通して形成する。
substrate! An At film 2 with a predetermined pattern is formed in the upper element formation region S by sputtering, and a 5i film is deposited on the entire surface of the substrate including the At film.
ns first insulating film 3 is formed by the CVD method, a polysilicon film with a predetermined pattern is formed by the LPCVD method directly on the A1 film 2 via the first insulating film, and after doping with p-type impurities, the p-type impurity is doped. Forming a gate electrode 5 in a predetermined pattern directly above the center of the mold polysilicon film 4 with a gate insulating film 47 interposed therebetween,
Thereafter, a second insulating film 7 is formed on the entire surface of the first insulating film including the p-type polysilicon film 4 so as to cover the gate electrode 5, and the Al wiring portions 6 reaching both ends of the p-type polysilicon 114 are connected to the second insulating film 7 so as to cover the gate electrode 5. It is formed to penetrate through the insulating film 7.

以下、動作をゲート絶縁膜直下の深さ方向のエネルギー
バンド図(第2図参照)を用いて説明す第2図は第1図
の構造を有するNチャネルMOSFETのゲート絶縁膜
直下の深さ方向の電子エネルギーバンドを示す図であり
、チャネルが形成されている場合を示している。
Below, the operation will be explained using an energy band diagram (see Figure 2) in the depth direction directly under the gate insulating film. FIG. 3 is a diagram showing the electron energy band of , and shows the case where a channel is formed.

第2WJにおいて、8はゲート絶縁膜47中の電子のエ
ネルギーバンドを示し、9はp型ポリシリコン膜4中の
電子のエネルギーバンド、IOはp型ポリシリコン膜下
面の第1絶縁膜3中の電子のエネルギーバンド、11は
第1絶縁膜3下面のAt膜2中の電子のエネルギーバン
ドをそれぞれ示す。また、12はチャネル部の電子であ
る。
In the second WJ, 8 indicates the energy band of electrons in the gate insulating film 47, 9 indicates the energy band of electrons in the p-type polysilicon film 4, and IO indicates the energy band of electrons in the first insulating film 3 on the lower surface of the p-type polysilicon film. The electron energy band 11 indicates the electron energy band in the At film 2 on the lower surface of the first insulating film 3, respectively. Further, 12 is an electron in the channel portion.

一方、第5図は第3図の構造を有するNチャネルMOS
FETのゲート絶縁膜直下の深さ方向の電子のエネルギ
ーを示す図で、第2図同様チャネルが形成されている場
合を示している。
On the other hand, FIG. 5 shows an N-channel MOS having the structure shown in FIG.
This is a diagram showing the energy of electrons in the depth direction directly under the gate insulating film of the FET, and shows the case where a channel is formed like in FIG. 2.

第2図から、第5図に示す従来例のポリシリコン膜22
中の電子エネルギーバンドにおける等エネルギー線に比
較して、p型ポリシリコン膜4中のチャネル直下の深さ
方向の電子のエネルギーバンドにおける等エネルギー線
の方が、傾きが緩やかであることが分かる。それによっ
て、チャネルを流れる電荷は表面散乱の影響を受は難く
、チャネル電流が、散乱の影響が少ないp型ポリシリコ
ンI[4の深い処でも流れるようにでき、高い移動度を
有するMOSFETを提供できる。
The polysilicon film 22 of the conventional example shown in FIG. 2 to FIG.
It can be seen that the iso-energy lines in the electron energy band in the depth direction directly below the channel in the p-type polysilicon film 4 have a gentler slope than the iso-energy lines in the middle electron energy band. As a result, the charges flowing through the channel are not easily affected by surface scattering, and the channel current can flow even deep in the p-type polysilicon I [4] where the influence of scattering is small, providing a MOSFET with high mobility. can.

すなわち、従来例では、ゲート電極5にポリシリコンを
用い、素子部のポリシリコン膜が厚さ2000人、NA
s=10”am−”程度のp型半導体であるNチャネル
MOSFETの場合、ゲート電極5に十分な不純物を入
れても、ゲート絶縁膜直下の空乏層の厚さは1500〜
2000人程度であるが、第1図に示す本実施例のよう
に、第1絶縁膜を介してp型ポリシリコン膜4下層にA
l1I2を形成した場合、空乏層の厚さは確実に素子部
Sのp型ポリシリコン膜下面にまで達し、チャネルが形
成される深さが深くなり、それによって移動度の上昇が
図れる。
That is, in the conventional example, polysilicon is used for the gate electrode 5, and the polysilicon film in the element part has a thickness of 2000 nm and a NA of 2,000.
In the case of an N-channel MOSFET, which is a p-type semiconductor with s = 10 "am-", even if sufficient impurity is added to the gate electrode 5, the thickness of the depletion layer directly under the gate insulating film is 1500 ~
Although the number of people is about 2,000, as in this embodiment shown in FIG.
When l1I2 is formed, the thickness of the depletion layer reliably reaches the bottom surface of the p-type polysilicon film in the element portion S, and the depth at which the channel is formed increases, thereby increasing the mobility.

このように本実施例では、石英の基板l上にポリシリコ
ン薄膜4を形成し、そのシリコン薄膜上にゲート電極5
を配設して薄膜トランジスタを形成する薄膜トランジス
タにおいて、基板l上にAlのメタル膜2を形成する工
程と、該メタル膜上にSingの第1絶縁膜3を形成す
る工程と、該第1絶縁膜上にシリコン薄[4を形成する
工程を具備し、それによってポリシリコン膜4をパター
ニングしたAIのメタル膜2上の第1絶縁膜3上に形成
する事により、チャネル直下の深さ方向の電子のエネル
ギーバンドの傾きを緩やかにでき、ポリシリコン膜4の
深さの深い処までチャネルが藍び、チャネルを流れる電
荷の表面の散乱の影響を受けにくくなり、ポリシリコン
膜4の深い処でも電流が流れるようにする事により高い
移動度を有するMOSFETを得ることができる。
In this embodiment, the polysilicon thin film 4 is formed on the quartz substrate l, and the gate electrode 5 is formed on the silicon thin film.
In a thin film transistor in which a thin film transistor is formed by disposing a thin film transistor, a step of forming a metal film 2 of Al on a substrate l, a step of forming a first insulating film 3 of Sing on the metal film, and a step of forming a first insulating film 3 of Sing on the metal film. By forming a polysilicon film 4 on the first insulating film 3 on the patterned AI metal film 2, electrons in the depth direction directly under the channel are formed. The slope of the energy band can be made gentler, the channel extends deep into the polysilicon film 4, and the charge flowing through the channel is less affected by scattering on the surface, and the current flow even deep in the polysilicon film 4. A MOSFET with high mobility can be obtained by allowing the current to flow.

(へ)発明の効果 以上のようにこの発明によれば、石英等の透明ガラス基
板上にシリコン薄膜を形成し、そのシリコン薄膜上にゲ
ート電極を配設して薄膜トランジスタを形成してなる半
導体装置において、透明ガラス基板上にA1等のパター
ニングされた導電膜及び絶縁膜を順次形成し、その絶縁
膜上にシリコン膜を形成してトランジスタを形成する事
により、ゲート絶縁膜直下の深さ方向の電子エネルギー
バンドの勾配を暖やかにでき、チャネル電流が、散乱の
影響が少ないシリコン膜の深い処でも流れるようにして
MOSFETの電界効果移動度を上昇できる効果がある
(F) Effects of the Invention As described above, according to the present invention, a semiconductor device is formed by forming a silicon thin film on a transparent glass substrate such as quartz, and disposing a gate electrode on the silicon thin film to form a thin film transistor. In this method, a patterned conductive film and an insulating film such as A1 are sequentially formed on a transparent glass substrate, and a silicon film is formed on the insulating film to form a transistor. This has the effect of increasing the field effect mobility of the MOSFET by making the slope of the electron energy band warmer and allowing the channel current to flow deep into the silicon film where it is less affected by scattering.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す構成説明図、第2図
は上記実施例におけるゲート絶縁膜直下の深さ方向のエ
ネルギーバンド図、第3.4図は従来例を示す構成説明
図、第5図は第3図で示す従来例のエネルギーバンド図
である。 l・・・・・・石英の透明ガラス基板、2・・・・・・
A11y(導電膜)、 3・・・・・・9i0*膜(第1絶縁膜)、4・・・・
・・p型ポリシリコン膿、 5・・・・・・ゲート電極、6・・・・・・配線部、7
・・・・・・S i O*Wi (第2絶縁膜)、第1
図 第2図 15図
Fig. 1 is an explanatory diagram of the configuration showing one embodiment of the present invention, Fig. 2 is an energy band diagram in the depth direction directly under the gate insulating film in the above embodiment, and Fig. 3.4 is an explanatory diagram of the configuration of a conventional example. , FIG. 5 is an energy band diagram of the conventional example shown in FIG. l...Quartz transparent glass substrate, 2...
A11y (conductive film), 3...9i0* film (first insulating film), 4...
... p-type polysilicon pus, 5 ... gate electrode, 6 ... wiring part, 7
...S i O * Wi (second insulating film), first
Figure 2 Figure 15

Claims (1)

【特許請求の範囲】 1、透明ガラス基板と、その透明ガラス基板上の素子形
成領域に配設された導電膜と、その導電膜を含む透明ガ
ラス基板全面に配設された第1絶縁膜と、その第1絶縁
膜を介して導電膜の直上に形成された実質的に薄膜のシ
リコン膜と、そのシリコン膜の中央部直上にゲート絶縁
膜を介して配設され、電圧の印加によってシリコン膜上
にチャネル部を形成しうるゲート電極と、シリコン膜を
含む第1絶縁膜上の全面にゲート電極を覆うように配設
された第2絶縁膜と、その第2絶縁膜を貫通してシリコ
ン膜の両端部に至る配線部とからなる半導体装置。 2、透明ガラス基板上の素子形成領域に所定パターンの
導電膜を形成し、その導電膜を含む透明ガラス基板全面
に第1絶縁膜を形成し、その第1絶縁膜を介して導電膜
の直上に所定パターンのシリコン膜を形成し、そのシリ
コン膜の中央部直上にゲート絶縁膜を介して所定パター
ンのゲート電極を形成し、その後シリコン膜を含む第1
絶縁膜上全面にゲート電極を覆うように第2絶縁膜を形
成し、シリコン膜の両端部に至る配線部を第2絶縁膜を
貫通して形成した半導体装置の製造方法。
[Claims] 1. A transparent glass substrate, a conductive film disposed in an element formation region on the transparent glass substrate, and a first insulating film disposed on the entire surface of the transparent glass substrate including the conductive film. , a substantially thin silicon film formed directly above the conductive film via the first insulating film, and a substantially thin silicon film disposed directly above the central part of the silicon film via the gate insulating film, and the silicon film is formed by applying a voltage. A gate electrode on which a channel portion can be formed, a second insulating film disposed on the entire surface of the first insulating film including a silicon film so as to cover the gate electrode, and a silicon film passing through the second insulating film. A semiconductor device consisting of a wiring section that reaches both ends of a film. 2. Form a conductive film in a predetermined pattern in the element formation area on a transparent glass substrate, form a first insulating film on the entire surface of the transparent glass substrate including the conductive film, and directly above the conductive film via the first insulating film. A silicon film with a predetermined pattern is formed on the silicon film, a gate electrode with a predetermined pattern is formed directly over the center of the silicon film via a gate insulating film, and then a first silicon film containing the silicon film is formed.
A method for manufacturing a semiconductor device, in which a second insulating film is formed on the entire surface of the insulating film so as to cover a gate electrode, and a wiring portion extending to both ends of the silicon film is formed by penetrating the second insulating film.
JP5424390A 1990-03-06 1990-03-06 Semiconductor device and its manufacture Pending JPH03256365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5424390A JPH03256365A (en) 1990-03-06 1990-03-06 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5424390A JPH03256365A (en) 1990-03-06 1990-03-06 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH03256365A true JPH03256365A (en) 1991-11-15

Family

ID=12965105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5424390A Pending JPH03256365A (en) 1990-03-06 1990-03-06 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH03256365A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07312426A (en) * 1994-05-18 1995-11-28 Casio Comput Co Ltd Thin film transistor and its manufacture
US5917221A (en) * 1992-06-09 1999-06-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6501097B1 (en) 1994-04-29 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US6835586B2 (en) 1998-12-25 2004-12-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6914302B2 (en) 1998-12-18 2005-07-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7276730B2 (en) 1998-12-28 2007-10-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
US8158980B2 (en) 2001-04-19 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917221A (en) * 1992-06-09 1999-06-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6340830B1 (en) 1992-06-09 2002-01-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6528852B2 (en) 1992-06-09 2003-03-04 Semiconductor Energy Laboratory Co., Ltd. Double gated electronic device and method of forming the same
US6815772B2 (en) 1992-06-09 2004-11-09 Semiconductor Energy Laboratory Co., Ltd. Dual gate MOSFET
US6501097B1 (en) 1994-04-29 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
JPH07312426A (en) * 1994-05-18 1995-11-28 Casio Comput Co Ltd Thin film transistor and its manufacture
US6914302B2 (en) 1998-12-18 2005-07-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6835586B2 (en) 1998-12-25 2004-12-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7276730B2 (en) 1998-12-28 2007-10-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
US8643015B2 (en) 1998-12-28 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
US8158980B2 (en) 2001-04-19 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor

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