JPH03256333A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03256333A JPH03256333A JP5364590A JP5364590A JPH03256333A JP H03256333 A JPH03256333 A JP H03256333A JP 5364590 A JP5364590 A JP 5364590A JP 5364590 A JP5364590 A JP 5364590A JP H03256333 A JPH03256333 A JP H03256333A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon film
- amorphous silicon
- single crystal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 44
- 239000013078 crystal Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract 3
- 239000010408 film Substances 0.000 claims description 122
- 238000000034 method Methods 0.000 claims description 39
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 239000012298 atmosphere Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims 3
- 239000011261 inert gas Substances 0.000 claims 2
- 230000007547 defect Effects 0.000 abstract description 7
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 238000010894 electron beam technology Methods 0.000 abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 2
- 239000007787 solid Substances 0.000 abstract 3
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 239000007790 solid phase Substances 0.000 description 18
- 230000005669 field effect Effects 0.000 description 9
- 239000012071 phase Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000280 densification Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000007791 liquid phase Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000002109 crystal growth method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁膜上の超薄膜単結晶シリコン膜を能動領域
とする電気特性の良好なMOSトランジスタの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a MOS transistor having good electrical characteristics and having an ultra-thin single-crystal silicon film on an insulating film as an active region.
従来、半導体基板表面に形成した絶縁膜上に半導体単結
晶薄膜を形成する方法は、エフ・イー・デイ3デイ ワ
ークショップ エクステンデッドアブストラクト(19
88年)第113頁から第118頁(Extended
Abstracts of 5thInternat
ional Workshop on Future
ElectoronDevices−THree Di
mensional Integration−[FE
D3D WORKSHOP]、May30 to
June 1,1988.Miyagi−Zao。Conventionally, the method of forming a semiconductor single crystal thin film on an insulating film formed on the surface of a semiconductor substrate is described in F.E.D. 3-Day Workshop Extended Abstracts (19).
1988) pages 113 to 118 (Extended
Abstracts of 5thInternat
ional Workshop on Future
ElectronDevices-THree Di
Mensional Integration-[FE
D3D WORKSHOP], May 30 to
June 1, 1988. Miyagi-Zao.
pp、1.13−118)に記載のように形成されてい
る。その工程は、次のようであった。■単結晶シリコン
基板の表面に通常の選択酸化法により熱酸化膜を形成す
る。この時に酸化膜の形成されない領域は。pp. 1.13-118). The process was as follows. ■A thermal oxide film is formed on the surface of a single-crystal silicon substrate by the usual selective oxidation method. At this time, the area where the oxide film is not formed is as follows.
後の横方向の結晶成長の種(シード)となる。■選択酸
化に用いた窒化膜とその下に敷いた酸化膜とを除去し、
試料表面に堆積シリコン膜(800nrn)を被着する
。■堆積シリコン膜上に結晶成長の保護膜(500nm
)を堆積し、電子線照射により堆積シリコン膜の単結晶
化を行なう。この電子線照射により堆積シリコン膜とシ
ード表面が一旦融解し、その後の再固化過程において単
結晶成長がシード表面から酸化膜上の領域へと横方向に
進行し、酸化膜上の堆積シリコン膜が単結晶化される。It becomes a seed for later lateral crystal growth. ■Remove the nitride film used for selective oxidation and the oxide film laid underneath it,
A deposited silicon film (800 nrn) is applied to the sample surface. ■ Crystal-grown protective film (500 nm) on the deposited silicon film
) is deposited, and the deposited silicon film is single crystallized by electron beam irradiation. The deposited silicon film and the seed surface are once melted by this electron beam irradiation, and during the subsequent resolidification process, single crystal growth progresses laterally from the seed surface to the region above the oxide film, and the deposited silicon film on the oxide film is Single crystallized.
■絶縁膜上に形成した単結晶膜を、エツチングにより所
望の膜厚の超薄膜単結晶シリコン層にする。■超薄膜単
結晶シリコン層に通常の多結晶シリコンゲートMOSト
ランジスタ形成工程を用いて素子を作製する。(2) The single crystal film formed on the insulating film is etched into an ultra-thin single crystal silicon layer with a desired thickness. (2) Fabricate a device using a normal polycrystalline silicon gate MOS transistor formation process on an ultra-thin single-crystal silicon layer.
また、非晶質シリコン膜の固相成長を利用して形成した
多結晶シリコン層を活性層とする電界効果薄膜トランジ
スタ(TPT)については特開昭62−39070に提
案されている。Further, a field effect thin film transistor (TPT) whose active layer is a polycrystalline silicon layer formed by solid-phase growth of an amorphous silicon film has been proposed in Japanese Patent Laid-Open No. 39070/1983.
絶縁膜上に単結晶シリコン膜の形成法には、上記のよう
に堆積した多結晶シリコン膜に電子線を照射することに
より多結晶シリコン膜の融解・再固化を用いてS○■構
造を形成する結晶成長法(液相成長法)がある。液相成
長法には、この他にストリップ・ヒータ、レーザ照射を
用いる方法があるが、これらの方法はいずれも局所的高
温加熱を用いる結晶成長法であり、下地損傷の問題があ
る。また、プロセス条件が下地構造の影響を受けるため
、その適正領域の選択やプロセスの再現性に問題がある
。The method for forming a single crystal silicon film on an insulating film involves melting and resolidifying the polycrystalline silicon film by irradiating the polycrystalline silicon film deposited as described above with an electron beam to form an S○■ structure. There is a crystal growth method (liquid phase growth method) that does this. Other liquid phase growth methods include methods using a strip heater and laser irradiation, but all of these methods are crystal growth methods that use localized high-temperature heating and have the problem of damage to the base. Furthermore, since the process conditions are influenced by the underlying structure, there are problems in selecting an appropriate area and in reproducibility of the process.
これに対して、低温プロセスによるS○工構造の形成法
として非晶質シリコン膜の固相成長を利用する固相成長
法がある。これは、堆積シリコン膜とし、て非晶質膜を
用い、試料を600℃程度の窒素雰囲気中で熱処理する
ことにより結晶成長領域を得る方法である。したがって
、温度差による結晶成長の不均一性、再現性については
問題無い。On the other hand, there is a solid-phase growth method that utilizes solid-phase growth of an amorphous silicon film as a method for forming an S○ structure using a low-temperature process. This method uses an amorphous film as the deposited silicon film and heat-treats the sample in a nitrogen atmosphere at about 600° C. to obtain a crystal growth region. Therefore, there is no problem with non-uniformity and reproducibility of crystal growth due to temperature differences.
ところが、この同相成長法では非晶質シリコン膜の膜厚
を薄くすると、横方向の結晶成長距離が短くなるという
問題点がある。そのため、固相成長法を用いて絶縁膜上
に単結晶薄膜を形成するためじは、液相成長法で用いら
れているように、予め厚い単結晶シリコン膜を形成し、
た後、エツチングにより超薄膜単結晶シリコン層とする
方法が゛考えられる。然るに、固相成長法により形成さ
れる単結晶膜の絶、縁膜との界面近傍には高密度の欠陥
が存在するのでこのような方法を用いることはできず、
低温プロセスを用いて形成した結晶性の良い超薄膜SO
I構造をデバイスの形成に用いることは難かしい、
〔課題を解決するための手段〕
超高真空中で堆積、緻密化した非晶質シリコン膜を試料
表面の平坦化が可能なエツチング(例えば、バイアスス
パッタ)を用いて所望の膜厚とした後、固相成長するこ
とによって形成した超薄膜SOI層をMoSトランジス
タの能動領域に用いる。However, this in-phase growth method has a problem in that when the thickness of the amorphous silicon film is reduced, the lateral crystal growth distance becomes shorter. Therefore, in order to form a single-crystal thin film on an insulating film using solid-phase growth, a thick single-crystalline silicon film is formed in advance, as is used in liquid-phase growth.
After that, a method of forming an ultra-thin single crystal silicon layer by etching may be considered. However, this method cannot be used because a high density of defects exists near the interface between the single crystal film formed by solid-phase growth and the edge film.
Ultra-thin SO film with good crystallinity formed using a low-temperature process
It is difficult to use the I structure for device formation. [Means to solve the problem] Etching (e.g., An ultra-thin SOI layer formed by solid-phase growth after obtaining a desired film thickness using bias sputtering is used for the active region of the MoS transistor.
超高真空中で堆積し、た非晶質シリコン膜を引き続き真
空中で熱処理する膜の緻密化は、非晶質シリコン膜の膜
質を変化するものであり、この膜質変化が横方向固相成
長距離を決定する。従って、緻密化した非晶質シリコン
膜を薄くした後、固相成長を行っても堆積膜厚に相当す
る横方向同相成長距離が得られる。The densification of an amorphous silicon film deposited in an ultra-high vacuum and subsequently heat-treated in a vacuum changes the film quality of the amorphous silicon film, and this change in film quality is the result of lateral solid-phase growth. Determine the distance. Therefore, even if solid-phase growth is performed after thinning a densified amorphous silicon film, a lateral in-phase growth distance corresponding to the thickness of the deposited film can be obtained.
また、同相成長によって得られるSOI構造内に生じる
高密度の結晶欠陥は、同相成長の時に生じるもので、結
晶成長時の膜内ストレスが起因する。この結晶欠陥を低
減するためには、非晶質シリコン膜を薄くしてから固相
成長することが必要である。Furthermore, the high density of crystal defects that occur in the SOI structure obtained by in-phase growth occurs during in-phase growth, and is caused by stress within the film during crystal growth. In order to reduce these crystal defects, it is necessary to thin the amorphous silicon film and then perform solid phase growth.
更に、緻密化した非晶質シリコン膜の薄膜化に関しては
、非晶質シリコン膜の固相成長による絶縁膜上への単結
晶成長が非晶質シリコン膜と基板との接触部から開始し
、最初に表面方向に進行し。Furthermore, regarding the thinning of a dense amorphous silicon film, single crystal growth on the insulating film by solid phase growth of the amorphous silicon film starts from the contact area between the amorphous silicon film and the substrate. First proceed toward the surface.
次に絶縁膜段差部を乗り越えた後、横方向に進むため、
段差部を乗り越え易いように非晶質シリコン膜表面が平
坦になる薄膜化法を用いることによって段差部の結晶成
長が容易になる。Next, after getting over the insulating film step part, it moves laterally, so
By using a thinning method in which the surface of the amorphous silicon film becomes flat so that it can easily climb over the stepped portion, crystal growth at the stepped portion is facilitated.
上記のような超薄膜S○工構造の形成法を用いることに
よって、超薄膜シリコン層においても広い単結晶シリコ
ン薄膜が形成でき、更に、単結晶成長が薄い膜で進行す
るため、絶・縁膜との界面近傍での単結晶膜中に生じる
欠陥の数も減少することが可能であるため、この超薄膜
SOI層を能動領域とするMOSトランジスタの電気特
性を向上することができる。By using the method for forming an ultra-thin film S○ structure as described above, a wide single-crystal silicon thin film can be formed even in an ultra-thin silicon layer, and furthermore, since the single-crystal growth progresses in a thin film, it is possible to form an insulating/insulating film. Since the number of defects occurring in the single crystal film near the interface with the SOI layer can also be reduced, the electrical characteristics of a MOS transistor using this ultra-thin SOI layer as an active region can be improved.
以下、本発明の詳細な説明する。 The present invention will be explained in detail below.
〈実施例1〉
実施例1を第1図により説明する。p型車結晶シリコン
基板1を1000℃の酸素雰囲気中で18分間の熱処理
し、約20nmの酸化膜2を形成した。次に、CVD法
により約120nmの窒化膜3を被着した。その後、通
常のホト・エツチング工程により窒化膜3を選択的に除
去した。この時のパターン部は、後に行なう単結晶成長
における種(シード)となるもので、基板1表面の<1
00>方向に垂直なストライプ状のものとした。この試
料を1000℃のウェット酸素雰囲気中で24分間の熱
処理し、約200nmの酸化膜4を形成した(a)。<Example 1> Example 1 will be described with reference to FIG. A p-type crystal silicon substrate 1 was heat treated in an oxygen atmosphere at 1000° C. for 18 minutes to form an oxide film 2 of about 20 nm. Next, a nitride film 3 of about 120 nm was deposited by CVD. Thereafter, the nitride film 3 was selectively removed by a normal photo-etching process. The pattern portion at this time serves as a seed for the single crystal growth that will be performed later, and is
The stripes were shaped perpendicular to the 00> direction. This sample was heat-treated for 24 minutes in a wet oxygen atmosphere at 1000° C. to form an oxide film 4 of about 200 nm (a).
次に、窒化膜3及び酸化膜2を除去し基板露出部5(シ
ード)を形成した。その後、真空蒸着装置内で低エネル
ギーAr(アルゴン)イオンビーム・スパッタ及び68
0℃、60分間の熱処理工程による試料の表面クリーニ
ングを行ない清浄な試料表面を形成した後、超高真空中
(IXlo−’Pa以下〉で電子ビーム蒸着により膜厚
が約800nmの非晶質シリコン膜6を堆積した(b)
。引き続き真空中で450℃、1時間の熱処理による非
晶質シリコン膜6の緻密化を行なった。その後、試料を
真空中から取りだし、通常のバイアス・スパッタ法によ
る試料表面のエツチングを行うことにより絶縁膜上の非
晶質シリコン膜6を約300nmとした。更に、バイア
ス・スパッタ法により生じた非晶質シリコン膜6表面の
ダメージ層を除去するため弗酸と硝酸の混合液により非
晶質シリコン膜6表面を約50nmエツチングした(c
)。Next, the nitride film 3 and oxide film 2 were removed to form a substrate exposed portion 5 (seed). After that, low energy Ar (argon) ion beam sputtering and 68%
After cleaning the surface of the sample through a heat treatment process at 0°C for 60 minutes to form a clean sample surface, amorphous silicon with a thickness of approximately 800 nm was deposited by electron beam evaporation in an ultra-high vacuum (less than IXlo-'Pa). Film 6 was deposited (b)
. Subsequently, the amorphous silicon film 6 was densified by heat treatment in vacuum at 450° C. for 1 hour. Thereafter, the sample was taken out of the vacuum, and the surface of the sample was etched by the usual bias sputtering method, so that the thickness of the amorphous silicon film 6 on the insulating film was about 300 nm. Furthermore, in order to remove the damaged layer on the surface of the amorphous silicon film 6 caused by the bias sputtering method, the surface of the amorphous silicon film 6 was etched by approximately 50 nm using a mixed solution of hydrofluoric acid and nitric acid (c
).
次に、薄膜化した非晶質シリコン膜6を600℃の窒素
雰囲気中で熱処理することにより同相成長を行ない、単
結晶化シリコンi@7を形成した(d)。この熱処理に
より、最初に試料のシード5から縦方向に結晶成長が開
始し、その後、゛酸化膜4のパターン・エツジを乗り越
え、そこから横方向に結晶成長が進行した。この横方向
の単結晶化シリコン膜7は、酸化膜4上の非晶質シリコ
ン膜6内に多結晶核が発生し、これが成長して非晶質シ
リコン膜6が多結晶シリコン膜8となるまでにシード5
からの単結晶成長が進行した領域である。Next, the thinned amorphous silicon film 6 was heat treated in a nitrogen atmosphere at 600° C. to perform in-phase growth to form single crystal silicon i@7 (d). As a result of this heat treatment, crystal growth first started in the vertical direction from the seed 5 of the sample, and then, after passing over the pattern edge of the oxide film 4, crystal growth progressed in the horizontal direction from there. In this horizontal single crystal silicon film 7, polycrystalline nuclei are generated in the amorphous silicon film 6 on the oxide film 4, and the amorphous silicon film 6 grows to become a polycrystalline silicon film 8. Seed 5 by
This is the area where single crystal growth has progressed from the beginning.
非晶質シリコン膜6を固相成長した時のシード端からの
単結晶成長は、結晶成長が終了する7時間で行ない、そ
の間に進行した距離は約5μmであった。この時、比較
のために行なった試料の単結晶成長距離を第1表に示す
。When the amorphous silicon film 6 was grown in a solid phase, single crystal growth from the seed end was carried out within 7 hours when the crystal growth was completed, and the distance traveled during that time was about 5 μm. At this time, Table 1 shows the single crystal growth distances of samples conducted for comparison.
第1表
傘:非晶質シリコン膜の薄膜化を等方エツチングにより
行った試料なお、これ等の結果は、各試料の結晶成長が
終了した後の距離である。表から、次のことが分かる。Table 1 Umbrella: Samples in which the amorphous silicon film was thinned by isotropic etching Note that these results are the distances after the crystal growth of each sample was completed. From the table, we can see the following:
■堆積膜の膜厚が薄いと緻密化を行なっても横方向の結
晶成長は生じない(試料1)。■堆積膜の膜厚が厚くて
も緻密化を行なわなければ横方向の結晶成長の距離は短
く(試料2)、緻密化を行なわなかった試料を薄くする
と横方向の結晶成長は全く生じない(試料3)。■堆積
膜の膜厚が厚く緻密化を行なった試料では、その後の薄
膜化の有無にかかわらず横方向の結晶成長の距離は最も
長くなった(試料4、試料5[試料5は本発明の製造方
法で形成した試料])。■非晶質シリコン膜の薄膜化を
等方エツチングを用いて行った試料では1段差部の影響
を受は横方向同相成長距離が短かった(試料6)。なお
、試料5及び試料6については、その断面構造図を第2
図に示す。■If the thickness of the deposited film is thin, no lateral crystal growth will occur even if densification is performed (Sample 1). ■ Even if the thickness of the deposited film is thick, if densification is not performed, the distance of lateral crystal growth will be short (sample 2), and if the sample without densification is made thinner, lateral crystal growth will not occur at all ( Sample 3). ■In the samples in which the deposited film was thick and densified, the distance of lateral crystal growth was the longest regardless of whether or not there was subsequent thinning (Sample 4, Sample 5 [Sample 5 is the method of the present invention] sample formed by the manufacturing method]). ■In the sample in which the amorphous silicon film was thinned using isotropic etching, the lateral in-phase growth distance was short due to the influence of the one-step difference (sample 6). Regarding samples 5 and 6, the cross-sectional structure diagrams are shown in the second
As shown in the figure.
以上に示すように、固相成長を用いて絶縁膜上に単結晶
シリコン薄膜を形成する際、非晶質シリコン膜を堆積し
た時の膜厚に依存し、固相成長時の膜厚の影響は受は難
いことが分かる。また、緻密化した非晶質シリコン膜を
薄膜化した試料5としなかった試料4の絶縁膜との界面
から200nmまでの単結晶成長内の結晶性を調べると
薄膜化した試料5の方が試料4に比べて欠陥が少なかっ
た。As shown above, when forming a single crystal silicon thin film on an insulating film using solid phase growth, it depends on the thickness of the amorphous silicon film when it is deposited, and the influence of the film thickness during solid phase growth. It turns out that it is difficult to receive. In addition, when examining the crystallinity within the single crystal growth up to 200 nm from the interface with the insulating film of Sample 5, which had a thinned densified amorphous silicon film, and Sample 4, which did not have a thinner densified amorphous silicon film, it was found that Sample 5, which had a thinner densified amorphous silicon film, was better than the other sample. There were fewer defects compared to 4.
次に、上記のように形成した単結晶化シリコン膜7内に
形成する素子の分離のため、通常のホト・エツチング工
程により素子形成領域以外の単結晶シリコン膜を選択的
に除去した。その後、単結晶化シリコン膜7の素子形成
領域をp型にするためボロン(B)イオン打ち込み(4
0keV、 I X 10”c「2)を行った(e)。Next, in order to separate the elements to be formed in the single crystal silicon film 7 formed as described above, the single crystal silicon film outside the element formation region was selectively removed by a normal photo-etching process. Thereafter, boron (B) ions are implanted (4
0 keV, I x 10”c “2) was performed (e).
以後の工程は、通常の多結晶シリコンゲートMO8)−
ランジスタの形成プロセスを用いた。なお、素子のゲー
ト酸化膜は35nm、トレインおよびソースの形成は砒
素(As)イオン打ち込み(80keV、 5 X 1
0”cm−2)とした。The subsequent steps are a normal polycrystalline silicon gate MO8)-
A transistor formation process was used. The gate oxide film of the device is 35 nm thick, and the train and source are formed by arsenic (As) ion implantation (80 keV, 5 x 1
0"cm-2).
上記のように形成したnチャネルMOSトランジスタ(
ゲート長:2μm、ゲート幅:2μm)の電界効果移動
度は、約720cm+”/V−sであり、単結晶シリコ
ンに同様のプロセスで形成した素子の電界効果移動度(
約600cm”/V−s )の1.2倍の値が得られた
。なお、形成した素子の単結晶シリコン膜厚は約90n
mであった。The n-channel MOS transistor (
The field effect mobility of a device (gate length: 2 μm, gate width: 2 μm) is approximately 720 cm+”/V−s, which is similar to the field effect mobility (
A value 1.2 times that of approximately 600 cm"/V-s) was obtained. The thickness of the single crystal silicon film of the formed device was approximately 90 nm.
It was m.
また、本実施例では素子間の分離に単結晶シリコン層の
エツチングを用いたが、選択酸化法を用いても同様な効
果が得られる。Further, in this embodiment, etching of the single crystal silicon layer was used to separate the elements, but the same effect can be obtained by using selective oxidation.
以上は、緻密化した非晶質シリコン膜を固相成長するこ
とによって形成した横方向の単結晶成長領域に作製した
MOSトランジスタについて゛の夫施例である。The above is an example of a MOS transistor manufactured in a lateral single crystal growth region formed by solid phase growth of a dense amorphous silicon film.
次に、緻密化した非晶質シリコン膜の同相成長で形成さ
れる多結晶シリコン領域の素子に関する実施例を示す。Next, an example of an element in a polycrystalline silicon region formed by in-phase growth of a dense amorphous silicon film will be described.
〈実施例2〉
実施例1と同様な手順によって、緻密化した非晶質シリ
コン膜6を形成した(第2図C参照)後、600℃の窒
素雰囲気中で熱処理する固相成長を行ない、多結晶シリ
コン膜8にした(第2図す参照)。この熱処理により、
シードから10μrn以上離れた領域では、酸化膜4上
の非晶質シリコン膜6内に多結晶核が発生し、これが成
長して非晶質シリコン膜6が多結晶シリコン膜8となっ
た。<Example 2> After forming a densified amorphous silicon film 6 by the same procedure as in Example 1 (see FIG. 2C), solid phase growth was performed by heat treatment in a nitrogen atmosphere at 600°C. A polycrystalline silicon film 8 was used (see FIG. 2). With this heat treatment,
In a region 10 μrn or more away from the seed, polycrystalline nuclei were generated in the amorphous silicon film 6 on the oxide film 4, and the amorphous silicon film 6 grew to become the polycrystalline silicon film 8.
次に、多結晶シリコン膜8内に形成する素子の分離のた
め、通常のホト・エツチング工程により素子形成領域以
外の多結晶シリコン膜を選択的に除去した。その後、多
結晶シリコン膜8の素子形成領域をp型にするためボロ
ン(B)イオン打ち込みを行った(第2図C参照)。以
後の工程は。Next, in order to separate the elements to be formed in the polycrystalline silicon film 8, the polycrystalline silicon film outside the element forming region was selectively removed by a normal photo-etching process. Thereafter, boron (B) ions were implanted to make the element formation region of the polycrystalline silicon film 8 p-type (see FIG. 2C). What are the subsequent steps?
通常の多結晶シリコンゲートMO8)−ランジスタの形
成プロセスを用いた。なお、素子のゲート酸化膜は35
nm、トレインおよびソースの形成は砒素(As)イオ
ン打ち込みとした。A conventional polycrystalline silicon gate MO8)-transistor formation process was used. Note that the gate oxide film of the device is 35
Arsenic (As) ion implantation was used to form trains and sources.
上記のように形成したnチャネルMOSトランジスタの
電界効果移動度は、約15001/v−5であり、従来
のCVDによって堆積した多結晶シリコン膜に同様のプ
ロセスで形成した素子の電界効果移動度(< 10cm
2/V−s )の15倍以上の値が得られた。なお、本
実施例では素子間の分離に多結晶シリコン層のエツチン
グを用いたが、選択酸化法を用いても同様な効果が得ら
れる。The field effect mobility of the n-channel MOS transistor formed as described above is approximately 15001/v-5, and the field effect mobility of the device formed by a similar process on a polycrystalline silicon film deposited by conventional CVD ( <10cm
2/V-s) was obtained. In this embodiment, etching of the polycrystalline silicon layer was used to separate the elements, but the same effect can be obtained by using selective oxidation.
〈実施例3〉
実施例1と同様な工程で緻密化した非晶質シリコン膜6
を600℃の窒素雰囲気中で熱処理することにより固相
成長を行ない、多結晶シリコン膜8にした後、更に、高
温(1000℃、4時間)の熱処理を行った。その後、
実施例1と同様な工程でnチャネルMOSトランジスタ
を作製し、素子の電界効果移動度を測定すると約160
cm2/V・Sであった。なお、従来のCVDによって
堆゛積した多結晶シリコン膜を高温熱処理しても形成し
たnチャネルMOSトランジスタの電界効果移動度には
変化は見られなかった。<Example 3> Amorphous silicon film 6 densified in the same process as Example 1
After solid-phase growth was performed by heat-treating in a nitrogen atmosphere at 600° C. to form a polycrystalline silicon film 8, heat treatment was further performed at a high temperature (1000° C., 4 hours). after that,
An n-channel MOS transistor was manufactured using the same process as in Example 1, and the field effect mobility of the device was measured to be approximately 160.
cm2/V・S. Note that even when a polycrystalline silicon film deposited by conventional CVD was subjected to high temperature heat treatment, no change was observed in the field effect mobility of the formed n-channel MOS transistor.
〈実施例4〉
第3図により実施例4を説明する。実施例1と同様な工
程で緻密化した非晶質シリコン膜6を(第3図C参照)
シリコンのエツチングを用いて約250nmに薄くした
後(第3図す参照)、600℃の窒素雰囲気中で熱処理
することにより固相成長を行ない、多結晶シリコン膜8
にした(第3図C参照)。その後、実施例1と同様な工
程でnチャネルMOSトランジスタを作製した(第3図
C参照)。素子の電界効果移動度を測定すると約180
c1/V−sであり、素子の特性が向上した。なお、緻
密化した非晶質シリコン膜6を600℃の窒素雰囲気中
で熱処理して多結晶シリコン膜にした後にシリコンのエ
ツチングを用いて約1100nにした膜に作製した素子
の電界効果移動度は増加しなかった。<Example 4> Example 4 will be explained with reference to FIG. An amorphous silicon film 6 densified in the same process as in Example 1 (see FIG. 3C)
After etching the silicon to a thickness of approximately 250 nm (see Figure 3), solid phase growth is performed by heat treatment in a nitrogen atmosphere at 600°C to form a polycrystalline silicon film 8.
(See Figure 3C). Thereafter, an n-channel MOS transistor was manufactured using the same steps as in Example 1 (see FIG. 3C). When measuring the field effect mobility of the element, it is approximately 180
c1/V-s, and the characteristics of the device were improved. Note that the field effect mobility of a device fabricated using a polycrystalline silicon film obtained by heat-treating the densified amorphous silicon film 6 in a nitrogen atmosphere at 600° C. and then etching the film to approximately 1100 nm is as follows. It did not increase.
本発明によれば、絶縁膜上に形成した単結晶薄膜を能動
領域とするMOSトランジスタにおいて、緻密化した非
晶質シリコン膜を表面平坦化の可能なエツチングを用い
て薄膜化した後に同相成長することによって、シードか
らの固相成長が容易になり単結晶成長領域の拡大、また
、単結晶成長時の膜内のストレス低減による結晶欠陥の
減少ができる。従って、この領域に形成した素子では良
好な電気特性を有するMOS)−ランジスタが得られる
。更に、本発明の効果は、nチャネルMOSトランジス
タの製造のみに限らず、PチャネルMOSトランジスタ
、CMO5構造の製造、さらに、それらの素子を集めた
集積回路の製造にも適用が可能である。According to the present invention, in a MOS transistor whose active region is a single crystal thin film formed on an insulating film, a densified amorphous silicon film is thinned using etching that can flatten the surface, and then in-phase growth is performed. This facilitates solid-phase growth from seeds, expands the single crystal growth region, and reduces crystal defects by reducing stress within the film during single crystal growth. Therefore, a MOS transistor having good electrical characteristics can be obtained from an element formed in this region. Furthermore, the effects of the present invention are applicable not only to the manufacture of n-channel MOS transistors, but also to the manufacture of P-channel MOS transistors, CMO5 structures, and even to the manufacture of integrated circuits in which these elements are assembled.
第工図〜第3図は本発明の製造工程を示す断面図、第1
表は各単結晶成長の製造工程で形成される横方向単結晶
成長距離を示す表である。Figures 1 to 3 are cross-sectional views showing the manufacturing process of the present invention.
The table shows the lateral single crystal growth distance formed in each single crystal growth manufacturing process.
Claims (1)
薄膜MOSトランジスタの製造において、(1)単結晶
半導体基板の少なくとも一部に絶縁膜を形成する工程、
(2)単結晶半導体基板と絶縁膜を連続して覆う非晶質
シリコン膜を超高真空中で堆積する工程、(3)上記非
晶質シリコン膜の堆積後、引き続き真空中で500℃以
下の熱処理を行うことにより非晶質シリコン膜を緻密化
する工程、(4)緻密化した非晶質シリコン膜を表面の
平坦化が可能なエッチング処理により所望の膜厚にする
工程、その後、(5)1200℃以下の窒素ガスあるい
は不活性ガス雰囲気中で熱処理を行うことにより非晶質
シリコン膜を単結晶化させる工程、更に、(6)絶縁膜
上に形成した薄膜シリコン層を能動領域とする素子を形
成する工程を具備することを特徴とする半導体装置の製
造方法。 2、上記特許請求の範囲第1項記載の絶縁膜層として、
酸化膜、窒化膜あるいは双方の積層構造で構成すること
を特徴とする半導体装置の製造方法。 3、上記特許請求の範囲第1項および第2項記載の非晶
質シリコン膜を単結晶化する熱処理として、550℃以
上、800℃以下の窒素ガスあるいは不活性ガス雰囲気
を用いることを特徴とする半導体装置の製造方法。 4、上記特許請求の範囲第1項ないし第3項記載の非晶
質シリコン膜を単結晶化する熱処理雰囲気として窒素ガ
スを用いることを特徴とする半導体装置の製造方法。 5、上記特許請求の範囲第3項記載の非晶質シリコン膜
を単結晶化した後、更に1000℃以上、1時間以上の
高温熱処理を行なうことを特徴とする半導体装置の製造
方法。[Claims] 1. In the production of an ultra-thin film MOS transistor whose active region is a single-crystal silicon thin film on an insulating film, the steps include: (1) forming an insulating film on at least a portion of a single-crystal semiconductor substrate;
(2) Depositing an amorphous silicon film that continuously covers the single crystal semiconductor substrate and the insulating film in an ultra-high vacuum; (3) After depositing the amorphous silicon film, continue in a vacuum at temperatures below 500°C. (4) a step of etching the densified amorphous silicon film to a desired thickness by performing an etching process that can flatten the surface; 5) A step of converting the amorphous silicon film into a single crystal by performing heat treatment in a nitrogen gas or inert gas atmosphere at 1200° C. or lower; and (6) converting the thin silicon layer formed on the insulating film into an active region. 1. A method of manufacturing a semiconductor device, comprising a step of forming an element. 2. As the insulating film layer according to claim 1 above,
1. A method of manufacturing a semiconductor device, characterized in that it is constructed of an oxide film, a nitride film, or a laminated structure of both. 3. The heat treatment for single-crystallizing the amorphous silicon film according to claims 1 and 2 above is characterized by using a nitrogen gas or inert gas atmosphere at 550° C. or higher and 800° C. or lower. A method for manufacturing a semiconductor device. 4. A method for manufacturing a semiconductor device, characterized in that nitrogen gas is used as a heat treatment atmosphere for monocrystallizing the amorphous silicon film according to claims 1 to 3 above. 5. A method for manufacturing a semiconductor device, which comprises monocrystallizing the amorphous silicon film according to claim 3, and then further performing high temperature heat treatment at 1000° C. or higher for 1 hour or longer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP5364590A JPH03256333A (en) | 1990-03-07 | 1990-03-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5364590A JPH03256333A (en) | 1990-03-07 | 1990-03-07 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03256333A true JPH03256333A (en) | 1991-11-15 |
Family
ID=12948629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5364590A Pending JPH03256333A (en) | 1990-03-07 | 1990-03-07 | Manufacture of semiconductor device |
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Country | Link |
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JP (1) | JPH03256333A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470619A (en) * | 1993-09-07 | 1995-11-28 | Korea Advanced Institute Of Science And Technology | Method of the production of polycrystalline silicon thin films |
-
1990
- 1990-03-07 JP JP5364590A patent/JPH03256333A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470619A (en) * | 1993-09-07 | 1995-11-28 | Korea Advanced Institute Of Science And Technology | Method of the production of polycrystalline silicon thin films |
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