JPH0325533A - Microprocessor - Google Patents

Abstract

PURPOSE:To save and restore used registers with one instruction at the time of context switching by allowing logical registers and physical registers to correspond to each other on a register management table by a CPU and recognizing the number of used physical registers by a used register number management register. CONSTITUTION:When a call instruction 210 is executed, registers r0 to r2 out of physical registers are assigned to a user stack pointer 107, a user program counter 108, and a user status register 109. When a logical register which the physical register corresponding to is already registered appears in a program, the number of the physical register existing in a register management table 102 is referred to access data in the corresponding physical register. When a call instruction 211 appears, contents of the used register number management table are automatically referred to save contents of seven physical registers r0 to r6. Thus, context switching is performed without taking save and restore of registers into consideration, and programming is facilitated.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a microprocessor (hereinafter referred to as CPU) having a plurality of registers.

[Conventional technology]

FIG. 5 is a diagram showing an example of the register structure of a conventional 32-bit CPU. In the figure, 501 to 508 are data registers for reading and writing data, and 509 to 5 are data registers for reading and writing data.
16 is an address register used as a base address register or a stack pointer, and 517 to 527 are other registers. Next, the operation will be explained. Data registers 501-5
08 and the number (0) assigned to addresses 509-516
~(7) are physical numbers, which are directly specified in machine language. Therefore, in the program, for example, dO, di and d
4 may be used, but d2 and d3 may not be used. In this case, in order to save registers by context switching when performing multitasking, the registers dO, dl. d4
An order to evacuate is necessary. Furthermore, when restoring the saved registers, an instruction for restoring them in the reverse order of d4, di, and do is required.

[Problem to be solved by the invention]

Conventional CPUs are structured as described above, so each time a context blink occurs, the program must perform register saving and restoring processing, which poses problems such as extra processing time. - This invention was made to solve the above problems, and can be used as a continuous register regardless of which register logical number is used.
The purpose of the present invention is to provide a CPU capable of saving and restoring a used register with a single instruction when a context switch is performed.

[Means to solve the problem]

In the CPU according to the present invention, a physical register having a physically fixed number or name and a register logical number or register logical name used in a program are set, and a physical register corresponding to the register logical number or register logical name is set. It is equipped with a register management table that is registered by number or name, and a register usage number management register that counts the number of physical registers registered in this register management table.

[Effect]

The CPU in this invention registers a register logical number or a register logical name used in a program in a register management table in correspondence with the number or name of an unregistered physical register, and registers a logical register in which the corresponding physical register is already registered. When handling the physical register, the number or name of the corresponding physical register is obtained from the register management table, and the physical register is accessed.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 101 is a general-purpose register group from a plurality of physical registers having fixed numbers, 102 is a register management table having a logical register number area 110 and a physical register number area 111, and 103 is a register registered in the physical register number area 111. 105 is a data register area, 106 is an address register area, 107 is a user stack pointer, 10B is a user program counter, 1
09 is a user status register. Next, the operation will be explained. Figure 2 (A) shows an example of the program. Of the instructions shown in the figure, 210
．． 211 is a CALL that requires a context switch
Suppose it is a command. First, when executing the CALL instruction 210, the user stack pointer 107, user program counter 108, and user status register 1
Of the physical registers, rO, rl, and r2 are assigned to 09. Next, when a register-related instruction appears while executing the called func 1, physical registers are sequentially allocated. In this case, when executing instruction 201, the physical register of r3 is placed in the logical register of d2, and when executing the instruction 202, the physical register of r4 is placed in the logical register of a3, and the physical register of r5 is placed in the logical register of a1. Then, when executing instruction 203, the physical register of r6 is assigned to the logical register of do. This situation is shown in FIG. 2(B). At this stage, the content of the register usage number management register 103 becomes “7”, and ro-r
This means that 6 physical registers are used consecutively. After this, when a logical register for which a physical register has already been registered appears in the program, the CPU analyzes this, refers to the physical register number existing in the register management table 102, and registers the corresponding physical register. Access data. Furthermore, when the CALL instruction 211 appears, the contents of the register usage number management table are automatically referred to and the contents of seven physical registers rO to r6 are saved. Further, the register management table 102 and register usage number management register 103 are automatically saved. When the execution of func2 is completed, the contents of the saved register usage number management register 103 are referred to, and the contents of the seven physical registers rO to r6 are restored, and the contents of the register management table 103 are restored. And the register usage number management register 103 is also automatically restored. Note that in the above embodiment, physical registers are allocated in the order in which logical registers appear in the program, but information for optimizing the allocation of logical registers and physical registers may be created in advance in the program. It may be held in the module and written to the register management table 102 when the context switch is executed. FIG. 3(A) shows the executable module 30
1, and FIG. 3(B) shows an example in which the register optimization information section 305 is arranged for each unit in which context switching is performed. be. Here, 302 is a module header, 303 is a module execution part, and 304 is a symbol information part. Regarding the location of the register optimization information section 305, two examples as shown in FIG. For example, it may be in another position. Furthermore, in this case, there is no need to save or restore the register management table 102 when saving or restoring physical registers. Figure 4 shows the correspondence between logical registers and physical registers.
This shows an example realized by hardware outside the CPUO. In the figure, 401 is a programmable logic device (PLD), and 402 is a data path. In this case, instead of registering the physical address in the register management table 102, the relationship between the logical address and the physical address is programmed into the PLD 401. Then, when accessing a register, the logical address is automatically exchanged with a physical address, thereby eliminating the need for the CPU to refer to the register management table 102. In the above explanation, whether or not a context switch is necessary can be determined by subprogram control instructions such as the CALL instructions 210 and 211, but register saving, . A dedicated command corresponding to return may be provided. Moreover, the control method described above can be easily realized specifically by a microprogram or wiring logic.

【Effect of the invention】

As described above, according to the present invention, the CPU is configured so that logical registers and physical registers correspond to each other in the register management table, and the number of physical registers in use can be grasped in the register usage number management register. There is no need to consider saving and restoring registers when programming, which has the effect of making programming easier.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing the register structure of a CPU according to an embodiment of the present invention, and FIG. 2(A). (B) is an explanatory diagram showing an example of register allocation, FIG. 3 is an explanatory diagram showing the arrangement of register management information in another embodiment of the present invention, and FIG.
The figure is a block diagram of a PLD, registers, etc. in yet another embodiment of the present invention, and FIG. 5 is a structural diagram showing the register structure of a conventional CPU. 101 is a group of general-purpose registers, 102 is a register management table, and 103 is a register for managing the number of registers used. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A plurality of physical registers having physically fixed numbers or names, a register logical number or register logical name used in the program, and the fixed number of the physical register corresponding to this register logical number or register logical name. Alternatively, a microprocessor comprising a register management table in which names are registered, and a register usage number management register that counts the number of the physical registers registered in the register management table.