JPH04138528A - Common data accessing system in contracted instruction setting computer - Google Patents

Abstract

PURPOSE:To improve the execution speed of a program by fixedly storing a common data address in a register prior to the execution of the program. CONSTITUTION:A register storing means 14 is constituted of an execution program recognizing means 51 and a register value setting means 52. In the case of storing a connectionally edited executable type program in a memory in order to execute the program, the means 14 starts the means 51, 52 and extracts names in each translation unit from an allocating state table 80. At the time of transferring execution control to the translation unit, contents specified by the name are executed. Thus, the address of common data is fixedly allocated to a prescribed register by a register allocating means 12 and the contents of the register are set up prior to their execution. Thus, the execution speed of the program can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a common data access scheme in reduced instruction set computers.

[Conventional technology]

This type of conventional common data access method stores the logical address of the common data after link editing in memory, stores the logical address in a register when referencing the common data, and uses the logical address on the register as the starting point. The first method is to access the memory that is to be stored, and the second method is to generate relocation information for the area representing the memory in the machine language instruction, store the logical address after link editing in that area at the time of execution, and access common data. A second method is known.

[Problem to be solved by the invention]

In the case of the first conventional method described above, since a memory access instruction with a slow execution speed appears every time common data is referenced,
Programs that reference a lot of common data will run slower. Furthermore, in the second method, relocation information is generated each time common data is referenced, so there is a drawback that the translation unit file becomes large.

The present invention solves these conventional drawbacks by fixedly storing the address of common data in a register prior to program execution, thereby improving execution speed and reducing the file size of a translation unit. The purpose is to provide a method for register allocation that can be reduced.

[Means to solve the problem]

The common data access method of the present invention includes an access management means for measuring the number of accesses to common data of a program running on a reduced instruction set computer at the time of program translation, and information containing the number of accesses and the name of the common data. Register allocation is a method that uses an access management table to control the allocation of common data to registers during program translation, and a tape is used for register allocation that has the name of common data and the status of register allocation for that common data as information. When link editing a program using , the assignment that has the correspondence between logical addresses and registers on virtual memory as information generates a state table. When storing the logical address value in the memory, the allocation includes register storage means for storing the logical address value in a register using a state table.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, access management means 11 is activated as a compiler component, register allocation means 12 is activated as a compiler component, state information generation means 13 and register storage means are activated during linked editing. 14, an access management table 60, a register allocation table 70, an allocation status table 80, a translation unit file 90, an executable program file 100,
It consists of an execution memory 110. Solid line arrows indicate activation relationships, broken line arrows indicate table settings and reference relationships, and thick line arrows indicate data flow.

FIG. 2 is a block configuration diagram showing the internal configuration of the access management means 11. The access management means 11 includes a common data identification means 21, a table development means 22, and a reference count measurement means 23. Solid line arrows indicate activation relationships, and dashed line arrows indicate table settings and reference relationships.

Table 1 is a configuration example of the access management table 60 that waits for information such as the name of common data, the number of times the common data is referenced, and the reference section of the common data. Each element corresponds to common data.

Table 1 Item 1-1 is the name of the common data, Item 12 is the number of references to the common data, Item 1-3 is the position where the first reference appears, and Item 1-4 is the last reference. This is the position where it appeared.

FIG. 3 is a block diagram showing the internal structure of the register allocation means 12. As shown in FIG. Solid line arrows indicate activation relationships, dotted line arrows indicate table setting and reference relationships, and register allocation is comprised of means 12, register securing/releasing means 31, available register identifying means 32, and machine language instruction counting means 33.

Table 2 is a configuration example of the register allocation table 70 in which the register allocation indicates the status.

Item 1-1 in Table 2 is the name of common data, item 1-2 is a numerical value representing the register, item 1-3 is the first position in the machine language instruction to which the register is to be allocated, and item 1-2 is the name of the common data.
-4 is the last position in the machine language instruction where a register is to be allocated.

FIG. 4 is a block diagram showing the internal configuration of the state information generating means 13. As shown in FIG. Solid arrows indicate activation relationships;
Dashed arrows indicate table settings and reference relationships. As for the layout, the status information generation means 13, the translation unit identification means 41,
It is constituted by relocation means 42.

Table 3 shows an example of the layout of the state table 80. Item 2-1 is the logical address after relocation of the common data, and item 2-2 is the common data represented by item 2-1. It is a numerical value representing the register to be allocated, item 2-3 is the first logical address after relocation in the machine language instruction to which the register is to be allocated, and item 2-4 is the first logical address in the machine language instruction to which the register is to be allocated. is the last logical address after relocation. Furthermore, element 1 is the name of the translation unit.

(The following is a blank space) Table 3 FIG. 5 is a block configuration diagram showing the internal configuration of the register storage means 14. The register storage means is composed of an execution program recognition means 51 and a register value setting means 52. Solid line arrows indicate activation relationships, and broken line arrows indicate data setting relationships.

Now, the access management means 11 activates the common data recognition means 21 when the compiler detects data referred to during translation. The common data recognition means 21 determines whether the data of the program being translated is common data or not. If it is not common data, it does nothing; if it is common data, it performs the following processing.

If the data is for a name that appears for the first time, Table R
Activate the opening stage 23, find the element for which the name of item 1-1 is not set among the elements of the access management table 60 shown in Table 1, store the name, and store the name of item 1-3.
Stores the line number that appears in , and also stores the line number that appears in item 1-4.
Store the line number stored in -2. Further, item 1-2 stores a value 1 indicating the number of references. Further, if the common data name is already stored in item 1-1 of the access management table 60, the reference count measuring means 22 is activated, the value 1 is added to item 1-2, and the value is stored. -4 stores the line number where the common data appears.

The register allocation means 12 is activated during the machine language instruction generation process of the compiler, and always activates the machine language instruction counting means 33 to count the size of the generated machine language instructions.
When generating machine language that refers to common data, if the common data is stored in item 1-1 of the access management table 60 shown in Table 1, the usable register identifying means 32 is activated. The register allocation shown in Table 2 searches the table for the name stored in item 1-1, and if there is no matching name, stores the name of the common data in item 1-1. , a value indicating the register taken out by the usable register securing means 32 is stored in item 1-2.

Furthermore, the size of the machine language instruction obtained by the machine language instruction counting means 33 is stored in both item 1-3 and item 1-4. If there is a matching name, the size of the machine language instruction obtained by the machine language instruction counting means 33 is stored in the item 1-4 of that element. After 0 or more processing, the usable register identifying means 32 A machine language instruction that refers to the common data is generated using the register retrieved by , and the register used at this time is made unusable.

When an available register cannot be retrieved by the available register identifying means 32, a reference to common data generates a machine code for obtaining an address from memory.

The status information generation means 13 activates the translation unit identification means 41 to identify the name of the input translation unit, and the layout shown in Table 3 is determined as an item in the status table 80. Store in 1. Also, the relocation means 4
2, the register allocation shown in Table 2 is based on the logical addresses represented by items 1-3 and 1-4 of each element in the table 70 after the relocation of the machine language instructions rearranged in the linked editing process. The layouts shown in Table 3 are converted into logical addresses and stored in items 2-3 and 2-4 of the status table 80, respectively. In addition, in item 2-1, the register allocation shown in Table 2 stores the logical address after relocation of the common data represented by item 1-1 of each element in the table 70, and in item 2-1,
-2 stores a numerical value representing the register indicated by item 1-2 of table 70 in the register allocation shown in Table 2.

The register storage means 14 activates the execution program recognition means 51 and the register value setting means 52 when storing the linked-edited executable format program in the memory for execution, and the allocation shown in Table 3 is based on the status table. 80, the name of the translation unit is extracted from element 1, and when execution control is transferred to that translation unit, the name of the translation unit is stored in the register indicated by item 2-2 of elements 2 to n, as indicated by item 2-1 of each element. Stores the address of common data and executes it.

〔Effect of the invention〕

As explained above, the present invention improves the execution speed by fixedly assigning the address of common data to a specific register and setting the contents of the register before execution. It has the effect of reducing the size.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
3 is a block diagram showing the internal configuration of the access management means; FIG. 3 is a block diagram showing the internal configuration of the register allocation means; FIG. 4 is a block diagram showing the internal configuration of the state information generation means; FIG. 5 is a block configuration diagram showing the internal configuration of the register storage means. 11... Access management means, 12... Register allocation means, 13... Allocation information generation means, 14... Register storage means, 21... Common data identification means, 22
. . . Reference count measuring means, 23 . . . Table development means, 31 . . . Register securing/releasing means, 32 . Translation unit identification means, 42... Relocation means, 60... Access management table, 70... Register allocation table, 80... Allocation status table, 90... Translation unit file, 100... - Executable program file, 110... execution memory.

Claims (1)

[Scope of Claims] Access management means (11) for measuring the number of accesses to common data of a program running on a reduced instruction set computer at the time of program translation, and having the number of accesses and the name of the common data as information. A register allocation means (12) that uses an access management table to control the allocation of common data to registers at the time of program translation; and a register allocation table that has as information the name of common data and the allocation status of registers to the common data. Allocation status information generation means (13) for generating an allocation status table having the correspondence between logical addresses on virtual memory and registers as information during linked editing of a program using
and register storage means (which stores the logical address value in the register using the allocation state table when storing the linked-edited executable program in the memory prior to execution).
14) A common data access method in a reduced instruction set computer.