JPH03252702A - Serial communication system - Google Patents

Abstract

PURPOSE:To accelerate the transmission/reception of data between a velocity control part and a current control part by performing the transmission/reception of only prescribed number of frames setting the frame consisting of a start bit, a data bit, a discrimination bit, and a parity bit as one unit. CONSTITUTION:The frame consisting of the start bit of one bit, the data bit of prescribed number of bits, the discrimination bit of one bit, and the parity bit is set as one unit. Therefore, it is possible to easily identify whether what numbered bit counting from the start bit is the data bit, the discrimination bit, or the parity bit. In such a way, since the constitution of transmitted/ received data is simplified, a time required for the transmission/reception i.e. transmission speed can be remarkably increased, which accelerates the transmission/reception of the data between the velocity control part and the current control part.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a serial communication method for serially communicating digital data, and for example, a current control section and a position control section of a servo control system that drives and controls a servo motor. This invention relates to a serial communication method suitable for data communication between

[Prior art]

BACKGROUND ART In numerical control devices or positioning devices that control machine tools or automation equipment, servo motors are used to position each axis.

In order to control the drive of this servo motor, conventionally, each servo motor is provided with a servo driver with an output rating corresponding to the servo motor, and a position control section for controlling the servo driver. Hereinafter, this servo driver and position control section will be referred to as a servo control means, and the combination of this servo motor and servo control means will be referred to as a servo control system.

FIG. 8 is a diagram showing a schematic configuration of a conventional servo control system.

The servo motor 7 is, for example, an AC servo motor of alternating current drive type. The servo motor 7 is coupled with a position sensor 8 for absolutely detecting its current position and a speed sensor (pulse generator) 9 for detecting its current speed. Outputs P1 and F5 of each of these sensors are output to a position sensor conversion circuit 64 and a speed sensor conversion circuit (F/
The V converter) 63 converts the data into position data P2 and speed data F4, and outputs them to the position control section 51 and speed control section 61. Further, when a synchronous servo motor is used as the servo motor 7, the position sensor conversion circuit 64 outputs a phase signal P3 for controlling the field switching position from the output P1 of the position sensor 8 to the current control unit 62. .

The position control system 5 includes a position control section 51 and a D/A converter 52. The device control section 51 inputs position command data FO indicating the target position of the servo motor 7 from a higher-level controller (not shown). , and the above position data P2 indicating the current position of the servo motor 7. Then, the position control section 51
calculates the deviation between the position command data FO and the position data P2, and outputs the speed command signal F1 according to the position deviation to the D/A.
Output to converter 52. The D/A converter 52 converts the speed command signal F1 from the position control section 51 into an analog speed command signal F3 and outputs it to the servo driver 6.

The servo driver 6 includes a speed control section 61, a current control section 62,
It is composed of a speed sensor conversion circuit 63 and a position sensor 64.

The speed control section 61 receives a speed command signal F3 from the D/A converter 52 and a speed signal F4 indicating the current speed of the servo motor. The speed control section 61 determines the deviation between the speed command signal F3 and the speed signal F4, and outputs a torque signal (current command signal) Tl of the servo motor 7 according to this speed deviation to the current control section 62.

The current control unit 62 drives the power transistor with a three-phase PWM signal, and supplies drive current to each phase (U phase, ■ phase, and W phase) of the servo motor.

At this time, the current feedback signal T3 of the U-phase and V-phase current values is fed back to the current control section 62 by the current detection isolator CT. The current control unit 62 amplifies the deviation between the torque signal (current command signal) Tl of each phase and the current feedback signal T3 of each phase and outputs a drive current to the servo motor 7. Note that the position sensor conversion circuit 64
outputs a phase signal P3 from the output P1 of the position sensor 8 to the current control section 62 for controlling the rotational position of the field.

[Problem to be solved by the invention]

In the conventional servo control system as described above, the response speed between the position control system 5 and the speed control section 61 is several meters S e
It is of the order of Q, and the speed control section 61 and the current control section 6
2, the response speed is on the order of several tens of microseconds.

That is, the response speed between the position control system 5 and the servo driver 6 may be sufficiently slower than the response speed between the speed control section 61 and the current control section 62. Therefore, it is possible to separate the position control system 5 and the servo driver 6, connect them with a communication line such as R5232C, and transmit the speed command signal of the position control system 5 to the speed control section 61.

However, the communication line such as R8232C requires 10 μsec between the speed control section 61 and the current control section 62.
Since the response speed is not satisfied, the speed control unit 61
It has been considered impossible to apply this method between the current controller and the current controller 62. Therefore, although it is possible to separate the position control system 5 and the servo driver 6 and connect them with a communication line such as R8232C as in the past, the speed control section 61 and the current control section 62 can be They could not be separated and connected via communication lines.

Furthermore, since the communication protocol such as R3232C is a system in which 7 or 8 bit data is communicated in correspondence with one character information, there is a problem of the fifth order.

First, since the data format is bit-based information such as a binary number, there are cases where it is not possible to distinguish between the data itself and the communication control code (character). Not guaranteed.

Second, when serial communication lines are connected at multiple points, a control code is required to specify the station at each connection point, and as mentioned above, the data part and the control code part cannot be distinguished because of poor bit transparency. .

Thirdly, between the speed control section 61 and the current control section 62,
Although it is sufficient to transmit only numerical data, it is necessary to perform the unnecessary processing of transmitting character information and converting it into numerical data.

On the other hand, HDLC (High Level Data
The communication method represented by Link Control guarantees bit transparency of data and also has a station specification function, so it can be used as the communication method between the speed control section 61 and the current control section 62. is possible.

However, since this HDLC must control the number of consecutive 1'''s and the flag sequence to transmit and receive, and encode and decode each data, the hardware required to satisfy these functions is complicated and This method is expensive and requires large-scale communication hardware, making it unsuitable for use in servo control systems in terms of cost.

The present invention has been made in view of the above points, and is a serial communication method that is inexpensive and can be configured with simple hardware, and that allows data to be sent and received at high speed between a speed control section and a current control section. The purpose is to provide

[Means to solve the problem]

The serial communication system of the present invention includes a start bit consisting of one bit to indicate the start of a frame, data bits consisting of a predetermined number of bits provided next to the start bit, and a start bit consisting of a predetermined number of bits provided next to the start bit, and a start bit consisting of a predetermined number of bits provided next to the start bit. One unit is a frame consisting of a 1-bit determination bit provided to determine the type and a parity bit provided next to this determination bit, and a frame in which at least one station address is set in the data bit. is set as a start frame, a frame in which various data are set in the data bits is set as a data frame, and a predetermined number of the data frames are added next to the start frame and transmitted/received.

[Effect]

In the present invention, one unit is a frame consisting of a start bit consisting of 1 bit, data bits consisting of a predetermined number of bits, a discrimination bit consisting of 1 bit, and a parity bit. By detecting it, it is possible to easily identify which bit from the start bit is a data bit, discrimination bit, or parity bit.

Also, a predetermined number of frames with this configuration are transmitted, at least one station address is set in the data bits of the first frame, and this is used as the start frame, and various data are set in the data bits. Since the data frame is added next to the start frame and transmitted, even in the case of multi-point connection, it is possible to easily determine whether the transmitted data is for internal conflict.

Furthermore, since the structure of the data to be transmitted and received is simple, the time required for transmission and reception, that is, the transmission speed, can be significantly improved, and data transmission and reception between the speed control section and the current control section, which was previously considered impossible, is now possible. This can be done at high speed, and the interface for sending and receiving can be realized with inexpensive and simple hardware.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a diagram showing a schematic structure of transmitted and received data used in the communication system of the present invention. Figure 1(a) shows the order of transmitted frames, Figure 1(b) shows the configuration of one unit of the frame, and Figure 1(c) shows the configuration of the start frame SF transmitted from the master station. , FIG. 1(d) is a diagram showing the structure of a start frame SF transmitted from a slave station.

The data transmission speed in this example is 2 Mbps (at a clock frequency of 32 MHz), and the transmission format is NR.
Z, and the communication method is asynchronous full-duplex mode.

The number of frames transmitted in one transmission between the master station and the slave station is one start frame SF and the following eight data frames IF to 8F.

In this embodiment, a case will be described in which the data frame length (data length) is 8 frames, but this data length is determined in advance by a microprocessor (CPU) or an external switch when configuring the communication system, for example. The length can be changed to any length such as 2 frames, 4 frames, 8 frames, 16 frames, etc. depending on the size of the system.

Then, once the -degree data length is set, communication is performed using that data length.

Both the start frame SF and data frames IF to 8F have an 11-bit configuration. The first bit of the start frame SF and data frames IF to 8F is a start bit SB for indicating the start of the frame, and specifically, a high level "I II" is set. Therefore,
A low level "071" is set between data, that is, between data frame 8F and the start frame SF of the next data.

A data bit section BO-87 consisting of 8 bits is provided next to the start bit SB.

Data bit part BO to B7 of data frame IF to 8F
Bits indicating various data are set in , and the following data is set in the data pit portion BO-87 of the start frame SF.

That is, data bit part BO-8 of start frame SF
At least one station address is set in 7.

When the master station transmits data to the slave station, the first three bits BO, B1 and B2 of the data bit section BO-87
bits 5O1S1 and B indicating the destination station address.
2 is set. In addition, when the master station requests data transmission from the slave station, the primary 3 bits B3, B4 and B
Bits RO, R1, and R2 indicating the address of the station to which transmission is requested are set in bit 5.

Conversely, when the slave station transmits data to the master station, the first three bits BO, Bl, and B2 are set to bits AO, Al, and A2 indicating the address of the slave station. By transmitting and receiving such a start frame SF between the master station and the slave stations, it becomes possible to establish a multi-point connection between the master station and the slave stations.

A determination bit DB consisting of 1 bit for determining the type of frame is provided next to the data bit section BO-87. That is, when the frame type is a start frame SF, a high level "1" is set, and when the frame type is a data frame IF to 8F, a low level "'0" is set. Therefore, by determining this determination bit on the receiving side, it is possible to determine whether the frame is the start frame SF or not.
It is possible to determine whether the data frame is from IF to 8F.

A parity bit PB consisting of 1 pin 1- is provided next to the discrimination bit DB. This parity bit PB
is set to a high level "1" when the number of high levels "1" in the data bit section BO-87 is an even number.

Although not shown, an idle signal of one frame length or two frame length can be placed before the start frame SF. This idle signal has a high level “1”,
This is a signal in which low levels II and OI+ are alternately repeated, and the receiving side detects a failure in one communication line depending on whether or not this idle signal pattern is transmitted normally. That is, if the transmission format is NRZ,
Such an idle frame is a precise square wave with a duty of 50 percent. Therefore, if an abnormality occurs in the communication line, such as a disconnection, short circuit, or noise intrusion, the accurate idle waveform will change, so if you detect this change heart-wise, you can easily detect an abnormality in the communication line. .

Next, a servo control system to which the communication method of the present invention is applied will be explained. FIG. 2 is a diagram showing a schematic configuration of a servo control system to which the communication method of the present invention is applied.

The communication method of the present invention is applied to data transmission between the serial communication interface 13 of the position and speed control system 1 and the serial communication interface 21 of the current control system 2.

The servo motor 3 is, for example, a synchronous AC servo motor. A position sensor 4 is coupled to the servo motor 3 to absolutely detect its current position. As this position sensor 4, for example, Japanese Patent Application Laid-Open No. 57-7040
An inductive phase shift type position sensor as shown in Publication No. 6 is used, and its output P1 is sent to the position sensor conversion circuit 14.
and converts it into digital position data P2.

The host controller 10 is connected to the position control unit 11 and receives position command data F indicating the target position of the servo motor 3.
O is output to the position control section 11.

Further, the host controller 10 is connected to a serial communication interface 13, and transmits and receives various data D1.

The position and speed control system 1 includes a position control section 11 and a speed control section 12.
The device control unit 11, which includes a serial communication interface 13, a 1-position sensor conversion circuit 14, and a speed calculation unit 15, is connected to the host controller 10 and position sensor conversion means 14, and is connected to the target position of the servo motor 3. Position command data FO indicating the current position of the servo motor 3 and position data P2 indicating the current position of the servo motor 3 are input.

The position control section 11 is connected to the speed control section 12, finds a deviation between the position command data FO and the position data P2, and outputs a speed command signal F1 to the speed control section 12 according to the position deviation. Note that the position sensor conversion circuit 14 generates a phase signal P3 for controlling the switching position of the field of the servo motor 3 from the output P1 of the position sensor 4, and outputs it to the serial communication interface 13.

The speed control section 12 is connected to the position control section 11, the speed calculation section 15, and the serial communication interface 13,
A speed command signal F1 from the position control section 11 and a speed signal F2 indicating the current speed of the servo motor 3 are input. The speed signal F2 is obtained by converting the position data P2 of the position sensor conversion circuit 14 by the speed calculation section 15. The speed calculation section 15 inputs the position data P2 from the position sensor conversion means 14, and calculates the speed of the servo motor by digital calculation based on the change i of the position data P2 per predetermined unit time of light. The speed control unit 12 is connected to the serial communication interface 13, finds the deviation between the speed command signal F1 and the speed signal F2, and generates the torque signal (current command signal) Tl of the servo motor 3 according to this speed deviation. Output to serial communication interface 13.

The serial communication interface 13 is connected to the host controller 10, the speed control unit 12, and the position sensor conversion means 14, and transmits various data D1, torque signal T1, and phase signal P3 from the host controller 10 to the current control system via the communication line. 2 serial communication interface 21
to be transmitted.

The serial communication interface 13 and the serial communication interface 21 are connected by a bidirectional communication line, and various data D1 from the host controller 1O and data D2 generated within the current control system 2 are sent to the host controller 10. The information is exchanged with the current control system 2.

The current control system 2 includes a serial communication interface 21 and a current control section 22.

Serial communication interface 21 is position speed control system 1
serial communication interface 13 and current control unit 2
2, the torque signal T1 and the phase signal P3
is received from the serial communication interface 13 and outputted to the current control unit 22 as a torque signal T2 and a phase signal P4, and various data D2 such as a status signal indicating the control state within the current control unit 22 is transmitted to the serial communication interface 13. do.

The current control unit 22 is connected to the external communication interface 21 and the servo motor 3, and inputs the torque signal T2 and the phase signal P4.
A WM signal is generated to drive the power transistor, and a drive current is supplied to each phase (U phase, ■ phase, W phase) of the servo motor 3. At this time, the current feedback signal T3 of the U-phase and V-phase current values is fed back to the current control section 22 by the current detection isolator CT. Current control section 2
2 amplifies the deviation between the torque signal (current command signal) T2 of each phase and the current feedback signal T3 of each phase and supplies a drive current to the servo motor 3.

Further, the serial communication interface 21 and the current control section 22 are connected by a data line, so that various data can be exchanged between them.

The current control unit 22 has a function of detecting control states such as servo motor overload, power supply voltage drop, overcurrent, overvoltage, and overheat, and also outputs a servo status signal indicating these control states and a current amplifier. ID code indicating the rating.

It has a memory that stores various data such as a motor rating code indicating the rating of the servo motor to be controlled. The data stored in the memory within the current control section 22 is transmitted to the host controller 1o via the data line and the serial communication interfaces 21 and 13 as the data D2, if necessary. Note that the motor rating code is stored in the memory as a table. Therefore, by selecting the table number according to the rating of the servo motor connected via the communication line, the current control unit 22
can control servo motors with different ratings.

With this, even if the servo motor is replaced, the current control section can be changed to a control system suitable for the servo motor by simply changing the table number.

Next, the operation of the servo control system shown in FIG. 2 will be explained. First, after configuring the servo control system as shown in FIG. Send to. However, if the serial communication interface 13 and the serial communication interface 21 are connected one-to-one as shown in Figure 2, the destination station address, transmission request destination station address, and own station address are fixed. things are used.

The table number data transmitted from the serial communication interface 13 is transmitted to the current control section 22 by the serial communication interface 21. Thereby, the current control section 22 specifies the rating of the servo motor 3 and functions as a current control section according to the rating of the servo motor 3.

The host controller 10 outputs position command data FO indicating the target position of the servo motor 3 to the position control section 11. The position control unit 11 receives position command data FO and position data P2.
A speed command signal F1 based on this is output to the speed control section 12.

The speed control unit 12 outputs a torque signal (current command signal) Tl corresponding to the speed command signal F1 and the speed signal F2 to the serial communication interface 13.

The serial communication interface 13 transmits data to the serial communication interface 21 in the frame order shown in FIG.

The serial communication interface 21 outputs the transmitted data of the torque signal T2 and phase signal P4 to the current control section 22.

The current control section 22 controls the drive current of the servo motor 3 based on the torque signal T2, the current feedback signal T3, and the phase signal P4. The output P1 of the position sensor 4 coupled to the servo motor 3 is fed back to the position and speed control system 1. The servo control system repeats the above operations to control the rotation of the servo motor 3.

If an abnormality such as overload, power supply voltage drop, overcurrent, overvoltage, or overheat occurs during this control, status signal data indicating these control states is transmitted from the current control unit 22 to the serial communication interface 21.
is output to. The data of this status signal is sent to the host controller 1 via the serial communication interface 13.
Sent to 0. The host controller 10 receives the data of this status signal and performs processing according to the type of the status signal.

When changing the servo motor 3 to a servo motor with a different rating, simply send the table number indicating the rating of the changed servo motor to the current control unit 22, and the current control unit 22 will change the rating according to the changed servo motor. Current control can be performed.

FIG. 3 is a diagram showing the configuration of the serial communication interfaces 13 and 21 of FIG. 2.

The clock divider 31 inputs a 32 MHz clock,
It outputs a 32 MHz clock, a phase-inverted 32 MHz clock, a 2 MHz clock for driving each logic in the serial communication interface, and clocks ACK and BCK of predetermined frequencies.

The digital filter 32 is connected to the clock frequency divider 31, the shift clock generation circuit 33, and the select switch 34, and receives the received data D11 (corresponding to the data D1) composed of a 32 MHz clock and the frame shown in FIG.
is input, corrects pulse breakage, etc., and outputs it to the shift clock generation circuit 33 and select switch 34.

The shift clock generation circuit 33 includes a clock frequency divider 31, a digital filter 32, and a reception shift! ~ Connected to the register 38 and latch timing signal generation circuit 39, 32M
The Hz clock and the received data D1 corrected by the digital filter 32 are input, and the register shift clock is output to the reception shift register 38 and the latch timing signal generation circuit 39.

The select switch 34 includes a digital filter 32, an idle signal check circuit 35, a start bit detector 36,
Received data D1 connected to the AND circuit 37 and the control register 5 and modified by the digital filter 32
is selectively outputted to the idle signal check circuit 35 or directly to the start bit detector 36 and AND circuit 37 according to the output of the control register 75.

The idle signal check circuit 35 is connected to the select switch 34
, the start bit detector 36 and the AND circuit 37, and checks whether the idle signal added before the received data D1 has been received normally, and sends the result as an idle check result signal IDEL to the outside of the serial communication interface. (upper controller 10 or current control unit 22), and the received data D1
is output to the start bit detector 36 and AND circuit 37. The receiving side can determine whether the communication line is normal or not based on the idle check result signal IDEL.

The start bit detector 36 is connected to the select switch 34, the idle signal check circuit 35, the AND circuit 37, and the latch timing signal generation circuit 39, and receives the received data D1 from either the select switch 34 or the idle check circuit 35. , detects the start bit SB located at the head of each frame SF, IF to 8F that constitutes the data, and at the time the start bit SB is detected, resets the built-in counter and starts the data bit section BO- following the start bit SB. 87, until the number corresponding to the discrimination bit DB and parity bit PB (10 in this embodiment) is counted, a high level "" is applied to the AND circuit 37.
Outputs 1”.

The AND circuit 37 is connected to the select switch 34, the idle signal check circuit 35, the start bit detector 36, and the receiving shift register 38, and receives the received data D1 while the start bit detector 36 outputs the high level 111 I+. The signal is output from the select switch 34 or the idle signal check circuit 35 to the receiving shift register 38.

That is, the start bit detector 36 and the AND circuit 37 detect each frame SF, IF to 8F of the received data D1.
Data bin 1 part B following start bit SB from inside
10 bits corresponding to O to B7, DB to discrimination bit 1, and parity bit PB are output to the reception shift register 38.

The reception shift register 38 is the shift clock generation circuit 3
10 from the AND circuit 37 by the clock of the shift clock generation circuit 33.
Stores bits of data. Further, the reception shift register 38 is connected to the latch timing signal generation circuit 39, and outputs the data of the discrimination bit DB of each frame SF, IF to 8F. Furthermore, the reception shift register 38 is connected to the register 41 via an 8-bit bus, and outputs the data in the data bit section BO-87 of each frame in parallel. When a serial communication interface is provided in the slave station, the reception shift register 38 is connected to the station select decoder 40, and the data bit part B of the frame is
It outputs data O to B5, that is, destination station addresses SO, S1, and S2 and transmission request destination addresses RO, R1, and R2.

Although not shown in the figure, a parity check decoder is connected to the reception shift 1 register 38, and a parity check is performed on the reception data Dll.

The latch timing signal generation circuit 39 is connected to shift 1 to clock generation circuit 33, start bit detector 36, reception shift 1 to register 38, and register 41, and receives data Dll stored in reception shift register 38.
Is the start frame sF? Is it a data frame IF?
~8F is determined based on the determination bit DB, and the received data D is stored in the register 41 position according to the order of the frames.
Store ll.

Furthermore, the latch timing signal generation circuit 39 is connected to the register 4.
1 and 42 are connected to the shift register 45, and output timing signals for respectively transferring received data Dll. Furthermore, the latch timing signal generation circuit 39 is connected to a control register 75, and the frame configuration (number of data frames) shown in FIG. 1 can be arbitrarily set according to the value in the control register 75. That is, in this embodiment, the case where there are eight data frames is explained, but in the case where there are four data frames, it is possible to correspond to four data frames by simply changing the setting value of this control register 75. can do.

The register 41 is connected to the reception shift register 38, the latch timing signal generation circuit 39, the AND circuit 47, and the register 42, and is controlled by the reception shift register 38 by the timing pulse from the latch timing generation circuit 39.
The data in the data bit section BO-87 of each frame is inputted in parallel from the BO-87 and stored. Further, the register 41 is connected to an AND circuit 47, and outputs a high level "1" to the AND circuit 47 when data storage is completed. Therefore,
When the other input of the AND circuit 47 is at a high level "1", the read enable signal RXRDY indicating the end of storage is output to the outside (the upper controller 10 or the current control unit 22). Data is in register 42
The data is transferred to and becomes readable. Note that the register 41 stores the data in the data bit sections BO to B7 for each frame SF,
10 frames (1 frame more than IF~8F) (8X 1
0 bit). This is to make the total of the start frame SF and data frames IF to 8F an even number.

The register 42 has the same capacity (8 x 10 bits) as the register 41, and includes the register 41, a latch timing signal generation circuit 39, an output buffer 43, and a frame selector 44.
connected to. The register 42 stores all the data in the register 41 in response to a timing pulse from the latch timing signal generation circuit 39, and simultaneously outputs the data to the frame selector 44 and output buffer 43 in parallel.

The output buffer 43 has the same capacity as the register 41 (8XIO
It is connected to the register 42 and the decoder 76, and outputs the data of the frame corresponding to the address specified by the decoder 76 from frames IF to 8F to the outside via the external data bus D21.

The frame selector 44 is connected to the register 42, the shift register 45, and the decoder 76, and corresponds to the frame selection signal SE of the decoder 76 for any two frames among frames IF to 8F sequentially output from the register 42. Data is selectively output to shift 1 to register 45.

The shift register 45 has a capacity to store data for two frames (8×2 bits).

Latch timing signal generation circuit 39, frame selector 44, output buffer 46, and control register 75
is connected to the output buffer, stores data for any two frames selected by the frame selector 44 in accordance with the timing signal, shifts the stored data by a predetermined amount in accordance with the output of the control register 75, and outputs data to the output buffer. 46.

That is, this shift register 45 receives the phase signal P4 in FIG.
This is a register to output according to the number of poles of the servo motor. Normally, the phase signal P3 output by the position sensor conversion means 14 is a signal when the number of poles is two, but when the number of poles of the servo motor 3 is 4, 6, or 8, the phase signal P3 is changed accordingly. A phase signal P4 must be output. Therefore,
The shift register 45 converts the received data into a two-pole phase signal P output from the position sensor conversion means 14 shown in FIG.
A phase of 3 to 4 poles, 6 poles or 8 poles <H must be generated. Therefore, shift 1 to register 45 extract the frame carrying the phase signal from the data output from register 42, further shift the data, and generate phase signals with the number of poles of 4, 6, and 8. are doing. Note that when the number of poles of the servo motor 3 is two, the data may be directly outputted via the output buffer 46 without being shifted.

The output buffer 46 is connected to the shift register 45 and converts the data in the shift register 45 into a fixed level phase signal P.
4 and output to the current control section 22.

The processing of received data has been described above, but when connecting communication lines at multiple points, the serial communication interface on the slave station side includes the station select decoder 40, the OR circuit 46, the AND circuit 47, and the transmitting side output buffer 79.
These will be explained below.

The station select decoder 40 includes a reception shift register 38,
Transmission side output buffer 79. If the data of destination station addresses SO, S1, and S2 connected to the OR circuit 46 and stored in the reception shift register 38 are the addresses of the own station, a high level "1" is input to the OR circuit 46, and so on. Otherwise, it outputs a low level II O''.
Output to 7. Therefore, only when the data of the destination station addresses 5O5S1 and S2 stored in the receiving shift register 38 are the addresses of the own station, and the data storage of the register 41 has been completed, the AND circuit 47 A read enable signal RXRDY is output. Therefore, the current control unit 22 can read the data as data for its own station. If not, AND circuit 4
The read enable signal RXRDY is not output from 7.

At this time, if a high level II II I+ is output from the control register 75 to the OR circuit, the received data is read by the current control unit 22 regardless of the output of the station select decoder 40. That is, when a plurality of current control systems 2 are multi-point connected and it is desired to transmit the same data to all current control units 22 at the same time, the control register 75 is set so that a high level is output to the OR circuit 46. All you have to do is set .

In addition, the station select decoder 40 also outputs the transmission request destination address R.
If O1R1 and R2 are the addresses of the own station, a low level "0" is output to the transmitting side output buffer 79, otherwise a high level "I+" is output.Therefore, the serial communication interface is the address of the transmission request destination. Data is output only when addresses RO, R1, and R2 are the addresses of the own station; otherwise, no data is output.

If the receiving side is the master station, such control is not necessary.
All you have to do is read all the data that is sent.

Next, the case of transmitting data will be explained.

The register 70 is connected to the external data bus 021, the data selector 72, and the decoder 76, stores data transmitted via the external data bus D21 in response to the write signal WRI from the decoder 76, and selects the data selector 7.
Output to 2.

The input latch 71 has a capacity to store data for two frames (8 x 2 bits), and is connected to the external data bus D22.
and I indicating the rating of the current amplifier connected to the data selector 72 and stored in the memory area of the current control unit 22
Data such as the D code and motor rating code are stored and output to the data selector 72.

The data selector 72 includes a register 7o, an input latch 71,
It is connected to the register 73, the control register 75 and the decoder 76, and receives the frame selection signal SE of the decoder 76.
Accordingly, data for two frames is selectively inserted into an arbitrary order among frames IF to 8F sequentially outputted from the register 7o, and outputted to the register 73.

The register 73 is connected to the shift timing signal generation circuit 78, the data selector 72, and the register 74, stores data from the data selector 72 in response to the timing signal, and outputs the data to the register 74 at the next stage. Furthermore, register 7
3 is the data in the data bit section BO-37 for each frame S.
F, 10 pieces (8X
10 bits).

Register 74 has the same capacity as register 73 'jIk (8X1
0 bit) and is connected to the register 73, shift timing signal generation circuit 78, and transmission shift register 77. The register 74 is a shift timing signal generation circuit 78
All data in the register 41 is stored in response to timing pulses from the register 41.

When data storage is completed, a transmittable signal TXRDY is output to the current control section 22. Therefore, the current control unit 22 can transfer the data in the register 74 in parallel to the transmitting shift 1 to the register 77 to enable transmission.

The transmission shift register 77 is connected to the register 74, the shift timing signal generation circuit 78, and the transmission output buffer 79, stores the data in the register 74, and serially transfers the stored data to the transmission output buffer 79 according to the timing signal. Output to.

The transmission output buffer 79 is connected to the transmission shift register 77 and the station select decoder 40, and receives a low level 110 I+ signal from the station select decoder 40, that is, a signal indicating that it is OK to transmit, to serially output the output from the transmission shift register 77. The output data is output as transmission data D12.

The control register 75 includes the external data bus D21, the select switch 34, and the latch timing signal generation circuit 3.
9, OR circuit 46, shift register 45. It is connected to the data selector 72 and the shift timing signal generation circuit 78, and transmits various control signals to the external data bus D21.
The control signal is output to each device, and the presence or absence of an idle signal, the number of frames to be sent and received, etc. are defined.

The decoder 76 inputs various signals from the current control unit 22, such as a chip select signal C8, an address signal ADR1, a read signal RD, a write signal WR, and a data read/write signal DRW, and receives read signals RDI, RD2, and a write signal. WRI,
It outputs WR2, frame selection signal SE, etc. to each device.

Next, the operation of this serial communication method will be explained.

First, when the serial communication interface receives data having a frame structure as shown in FIG. 1, it passes it through the digital filter 32 as received data Dll, and corrects pulse breakage and the like in the received data Dll.

The modified received data Dll is sent to the select switch 34.
depending on whether the signal passes through the idle signal check circuit 35 or directly through the AND circuit 37 and the start bit detector 3.
6 is output. Therefore, in the received data Dll, the data bit part BO following the start bit SB of each frame
-B7, only the data of the discrimination bit DB and the parity bit PB are stored in the reception shift register 38.

When the reception data D11 stored in the reception frame 38 is a start frame SF, its data bit part BO-
Based on 85 (destination station addresses SO, S1, and S2 and transmission request destination addresses RO, R1, and R2), the station select decoder 40 determines whether the data is transmitted to the own station or whether it is a transmission request to the own station. to judge.

There is data sent to own station and register 4
If all frames of received data are stored in 1,
Since the AND circuit 47 outputs the read enable signal RXRDY, the received data Dll is taken into the current control unit 22 via the registers 41 and 42, the output buffer 43, and the external data bus D12.

In addition, if the received data Dll includes a phase signal and the number of poles must be converted, the frame selector 44,
A phase signal P4 having a predetermined number of poles is output to the shifter 1 via the register 45 and the output sofa 46.

Next, the case of transmitting data will be explained.

Transmission data is external data bus D21, data selector 7
2, stored in the transmission shift register 77 via registers 73 and 74. At this time, if the data stored in the memory area of the current control unit 22 is to be transmitted simultaneously, the data selector switch 72 inserts the data in the memory area into any location a of the transmitted data.

The register 74 outputs the transmit enable signal TXRDY to the current control unit 22 at the time when the storage of the transmit data is completed.
Transmission data D12 is output from the transmission shift register 77 in response to the transmission enable signal T.sub.XRD.sub.Y. However, the received data Dl stored in the receiving frame 38
If the transmission request destination addresses RO, R1, and R2 of l are not a transmission request for the own station, the transmission output buffer 79 does not output the transmission data D12.

FIG. 4 is a diagram showing an absolute type position sensor consisting of an inductive phase shift type position sensor, which is an example of the position sensor 4 of FIG. 2. The details of this position sensor 4 are known from Japanese Patent Application Laid-Open No. 70406/1982, so a brief explanation will be given here.

The position sensor 4 is inserted into a stator 23 in which a plurality of poles A-D are provided at predetermined intervals (for example, 90 degrees) in the circumferential direction, and a space of the stator 23 surrounded by each pole A-D. and a rotor 24.

The rotor 24 is made of a shape and material that changes the reluctance of each pole A-D depending on the rotation angle, and has an eccentric cylindrical shape, for example. Primary coils IA to ID and secondary coils 2A to 2D are wound around each pole A to D of the stator 23, respectively. The first pair of poles A and C and the second pair of poles B and B, which are radially opposed to each other, are wound with coils so as to operate differentially. It is configured such that a roughtance change occurs.

The primary coils IA and IC wound around the first pole pair A and C are excited by a sinusoidal signal sinωt, and the primary coils IB and IC wound around the second pole pair B and D are excited by the sinusoidal signal sinωt. It is excited by a cosine signal cosωt. As a result, a composite output signal Y is obtained from the secondary coils 2A to 2D. This composite output signal Y is a primary AC signal (primary coil excitation signal) sinω or cosω, which is a reference signal.
With respect to t, a signal Y=sin (ω is 10) whose phase is shifted by an electrical phase angle corresponding to the rotation angle θ of the rotor 24
It is.

Therefore, when using the above-mentioned inductive phase shift type position sensor, the primary AC signal sinω or co
AC signal generating means for generating sωt and a composite output signal Y
It is necessary to provide a phase difference measuring means for measuring the electrical phase shift O of the rotor and calculating the position data of the rotor. The primary AC signal generating means and the phase difference measuring means are provided in the position sensor converting means 14.

FIG. 5 is a diagram showing an example of the position sensor conversion means 14 of FIG. 2. In the position sensor conversion means 14, a predetermined high-speed clock pulse CP is counted by a counter 26,
Based on the output of the counter 26, the sine/cosine signal generating means 27 generates a sine signal sinω and a cosine signal co.
sωt respectively. The output of the sine/cosine signal generating means 27 is applied to the primary coils IA to ID and the secondary coils 2A to 2D, respectively, as described above.

Combined output signal Y=sin (ω
10) is given to the zero cross detection means 28. The zero cross detection means 28 outputs a pulse L in synchronization with the timing when the electrical phase angle of the composite output signal Y is zero. Pulse L is used as a latch pulse for latch circuit 29. Therefore, the latch circuit 29 latches the count value of the counter 26 in response to the rise of the pulse L. counter 2
The period during which the count value of 6 goes around once is synchronized with one cycle of the sine signal sinωt. Then, the latch circuit 29 receives the reference AC signal sinωt and the composite output signal Y=sin (ω
The count value corresponding to the phase difference θ with respect to θ) is latched. Therefore, the latched value is output as digital position data Dθ. Furthermore, latch pulse L
can also be used appropriately as a timing pulse.

Further, among the values latched by the latch circuit 29, a value indicating the absolute position within one rotation of the servo motor is output as digital phase data P3, and is used for field switching position control.

Incidentally, the composite output signal P1 of the phase shift type position sensor as shown in FIG. 4 uses the absolute position of the servo motor as the phase difference of the signal, and therefore has the characteristic that it is not easily affected by noise. Therefore, as shown in FIG. 2, when the composite output signal P1 is fed back from the position sensor 4 to the position and speed control system 1.

This is acceptable because it provides direct feedback without using a communication line and is not affected by noise or the like.

However, the composite output signal P1 of the position sensor 4 may be fed back using a communication line such as a serial communication interface.

Although FIGS. 4 and 5 show that the range of one rotation is detected by absolute coating, it is preferable to combine a plurality of such absolute sensors to detect the absolute coating position over multiple rotations.

FIG. 6 is a diagram showing an embodiment in which a plurality of servo motors are switched and controlled using the communication system of the present invention. In FIG. 6, the same components as in FIG. 2 are denoted by the same reference numerals, so their explanation will be omitted.

This embodiment differs from the one in FIG. 2 in that a plurality of servo motors 3a, 3b to 3n are connected to an axis switching unit 20,
The drive current of the phases (U phase, ■ phase, W phase) and the sine signal, cosine signal, and composite output signal for the position sensor are sent to the axis switching unit 2.
The point is that it is switched at 0 and driven alternately.

The axis switching unit 20 includes a current control section 22, a position sensor conversion means 14, a host controller, and servo motors 3a, 3.
b to 3n and position sensors 4a, 4b to 4n, respectively, and the drive current is applied to each servo motor 3a, 3 according to the axis switching signal channel from the host controller 10.
b to 3n, the position sensor signals are sent to each position sensor 4a,
4b to 4n.

Switch and connect each. Therefore, depending on the axis switching signal channel of the host controller 10, the servo motors 3a, 3
b-3n and a set of position sensors 4a, 4b to 4n are selectively connected to the position and speed control system 1 and the current control system 2,
form respective servo control loops.

That is, the axis switching unit 20 has each servo motor 3a,
3b to 3n and each position sensor 4a, 4b to 4n, and selectively conducts only the switching element corresponding to one set of servo motor and position sensor. This selectively connects only one set of servo motors and position sensors to the control loop.

At this time, if all the ratings of the servo motors 3a, 3b to 3n are the same, it is only necessary to perform switching control while keeping the table number indicating the rating of the servo motors constant. In addition, if the ratings of the servo motors 3a, 3b to 3n are different, if the table number indicating the rating of the servo motor is transmitted via the communication line before controlling the servo motor, one current control can be performed. System 2 can sequentially switch and control servo motors with different capacities.

FIG. 7 is a diagram showing an embodiment in which a plurality of servo motors are controlled simultaneously using the communication method of the present invention. In FIG. 7, the same components as in FIG. 2 are denoted by the same reference numerals, so their explanation will be omitted.

This embodiment differs from the one in FIG. 2 in the current control systems 2X and 2Y that control the drive current of the servo motor.

A plurality of 2Zs are provided, a communication line is used to connect them at multiple points, and servo motors 3X, 3Y, and 3z are connected to each current control system 2X, 2Y, and 2Z, respectively. That is, in this embodiment, a plurality of sets consisting of a servo motor, a position sensor, and a current control system are provided, and these serial communication interfaces 21X, 2], Y, and 21Z and the serial communication interface of the position and speed control system 1 are provided. 13 for multi-point connection. Also, in this embodiment, similarly to the embodiments shown in FIGS. 2 and 6, the outputs PX, PY, and pz of the position sensors 4X, 4Y, and 4Z are converted to the position sensor conversion means 1.
I am trying to import it directly into 4.

The position and speed control system 1 performs position control operations and speed control operations for each axis, and the serial communication interface 13 transmits and receives data for each axis.

The serial communication interface 13 includes serial communication interfaces 21X, 21Y, and 212 for each current control system.
, the torque signal T1, phase data I) 3, and various data D1 can be transmitted simultaneously, making it possible to control the servo motors 3X, 3Y, and 3Z simultaneously. Each of the current control units 22X, 22Y, and 22Z determines whether the transmitted data is for its own station, reads it if it is for its own station, and performs control according to the data. For example, in the case of data regarding the drive of a servo motor, a drive current is supplied to the servo motor based on the data.

Furthermore, when a table number indicating the rating of the servo motor is transmitted, the drive current of the current control section 22 is changed to one corresponding to the rating of the servo motor in accordance with the table number.

As in this embodiment, multiple sets of servo motors and current control systems are provided, the position and speed control systems are common, and the communication lines between them are multi-point connected. can be controlled at the same time.

In the above embodiment, the case where the serial communication method of the present invention is applied to a servo control system has been described, but it is not limited to this and can be similarly applied to other digital communication methods. not.

[Effects of the Invention] The present invention employs a configuration in which only a predetermined number of frames are transmitted and received, with each frame consisting of a start bit, data bit, 1 discrimination bit, and parity bit being one unit, so that the time required for transmission and reception is reduced. In other words, the communication speed can be greatly improved, data can be sent and received between the speed control section and the current control section at high speed, which was previously considered impossible, and the interface for sending and receiving is also inexpensive. This has the advantage that it can be realized with simple hardware.

In addition, since the frame to be sent and received consists of a start frame with the station address set and a predetermined number of data frames, it is easy to check whether the transmitted data is for the own station, even when multi-point connections are made. It also has the effect of being able to make decisions.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing a schematic configuration of an embodiment of transmitted and received data used in the communication method of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a servo control system to which the communication method of the present invention is applied, and FIG. 3 is a block diagram showing an example of the configuration of the serial communication interface shown in FIG. 2, and FIG. 4 shows an absolute position sensor consisting of an inductive phase shift type position sensor, which is an example of the position sensor 4 shown in FIG. 1. 5 is a block diagram showing an example of the position sensor conversion means shown in FIG. 1, and FIG. 6 is a block diagram showing an embodiment in which a plurality of servo motors are switched and controlled using the communication system of the present invention. , FIG. 7 is a block diagram showing an embodiment in which a plurality of servo motors are controlled simultaneously using the communication method of the present invention, and FIG. 8 is a block diagram showing a schematic configuration of an example of a conventional servo control system. . ...Reception shift register, 41.42...Register, 43.46...Output buffer, 45...Shift register, 40...Station select decoder

Claims (1)

[Claims] (1) A start bit consisting of 1 bit to indicate the start of a frame; Data bits consisting of a predetermined number of bits provided next to this start bit; and a frame next to this data bit. One unit is a frame consisting of a 1-bit discrimination bit provided for discriminating the type of information, and a parity bit provided next to this discrimination bit, and at least one station address is set in the data bit. A serial communication system characterized in that a frame in which the data bits are set is a start frame, a frame in which various data are set in the data bits is used as a data frame, and a predetermined number of data frames are added to the start frame and then transmitted and received. (2) The serial communication system according to claim 1, wherein an idle frame in which a high level and a low level are alternately repeated is added before the start frame for transmission and reception. (3) An interface for transmitting and receiving serial data consisting of the start frame and the data frame according to claim 1, which extracts and outputs only the data bits from the received serial data. An interface featuring: (4) start bit detection means for detecting the start bit from among the bits constituting the start frame and the data frame; a first register that stores only the data bits, discrimination bits, and parity bits from the serial data; and only the data bits connected to the first register and stored in the first register. a second register that stores a second register; and a first output buffer connected to the second register for outputting the data bits to the outside. Interface described. (5) a third register connected between the second register and the output buffer, which stores the data bits stored in the second register and transfers them to the output buffer;
a fourth register connected to the third register and storing data bits corresponding to a predetermined number of frames from among the data bits transferred from the third register to the output buffer; connected to this fourth register,
and a second output buffer for outputting the data bits to the outside.
Interface as described in section. (6) connected to the first register and based on the station address among the data bits stored in the first register, the output of the data bits stored in the second and the serial 4. The interface according to claim 3, further comprising a station select decoder for controlling data transmission.