JPH03252151A - Evaluation of semiconductor wafer - Google Patents

Evaluation of semiconductor wafer

Info

Publication number
JPH03252151A
JPH03252151A JP5013590A JP5013590A JPH03252151A JP H03252151 A JPH03252151 A JP H03252151A JP 5013590 A JP5013590 A JP 5013590A JP 5013590 A JP5013590 A JP 5013590A JP H03252151 A JPH03252151 A JP H03252151A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor wafer
absence
microcracks
cracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5013590A
Other languages
Japanese (ja)
Inventor
Hisaaki Suga
須賀 久明
Akiharu Ishigaki
石垣 昭春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP5013590A priority Critical patent/JPH03252151A/en
Publication of JPH03252151A publication Critical patent/JPH03252151A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To obtain a method which allows sure and simple detection of cracks of waters by mounting a wafer on a support member having a cavity opening in top with the inspection face downward and by applying a preset fixed load at the center of the wafer to judge whether microcracks are present from fractures. CONSTITUTION:For evaluation of a semiconductor wafer to judge whether microcracks are present in its inspection face, a semiconductor water 5 is mounted on a support member 2 having a cavity opening in top with its inspection face downward, and the center of the semiconductor wafer 5 is applied with a preset fixed load to judge it from fractures whether microcracks are present. For example, used is a device 1 consisting of a ring-shaped support member 2 grooved 4 for mounting the wafer's peripheral edge and an indenter 3 with a 5-40mm diameter R in the tip. A critical value of the breakdown strength of a crack-free normal standard article is predetermined, and it is applied with a loading at a value of about 95% of the critical value to judge whether microcracks are present from fractures.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体ウェーハの評価方法に関するものであ
り、とくに目視検査やX線回折法では発見することの難
しい微少クラックの存在の有無を検査するのに効果を奏
するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for evaluating semiconductor wafers, particularly for inspecting the presence or absence of minute cracks that are difficult to detect by visual inspection or X-ray diffraction. It is effective in doing so.

[従来の技術] 半導体ウェーハ(以下ウェーハと略称する)は半導体素
子の製造工程において、熱処理や膜付は処理等による強
い応力等を受ける。この際にウェーハにクラックか存在
すると、ウェーハの一部か欠けてしまうことがある。ま
た、この欠けたウェーハの一部かパーティクルとなり、
半導体素子製造プロセス工程の障害となることもある。
[Prior Art] Semiconductor wafers (hereinafter abbreviated as wafers) are subjected to strong stress and the like due to heat treatment, film deposition, etc. in the manufacturing process of semiconductor elements. If there are cracks in the wafer at this time, part of the wafer may be chipped. Also, part of this chipped wafer becomes a particle,
It may also become a hindrance in the semiconductor device manufacturing process.

よってウェーハの出荷の際には、クラックの有無を検査
するために、目視検査やX線回折法による評価を行って
、クラックの存在するウェーハを取り除くことが行なわ
れていた。
Therefore, when wafers are shipped, visual inspection or evaluation by X-ray diffraction is performed to check for the presence of cracks, and wafers with cracks are removed.

[発明が解決しようとする課題] しかじなが′ら、このような従来のウェーハの検査方法
によっては、目視検査で行う場合には、小さすぎるクラ
ックを発見することができないといった課題がある。ま
た、X線回折による検査の場合には、加工歪(塑性歪と
弾性歪)とクラックとの区別がつきにくいといった課題
がある。さらに、上記のいずれの検査の方法によっても
、ウェーハ表面全体の検査を行うのは、かなりの時間と
労力を要し、実際には困難な作業となっていた。
[Problems to be Solved by the Invention] However, depending on such conventional wafer inspection methods, there is a problem that cracks that are too small cannot be discovered when visual inspection is performed. Furthermore, in the case of inspection by X-ray diffraction, there is a problem that it is difficult to distinguish between processing strain (plastic strain and elastic strain) and cracks. Furthermore, with any of the above inspection methods, inspecting the entire wafer surface requires a considerable amount of time and effort, making it a difficult task in practice.

本発明は前記事情に鑑みてなされたもので、ウェーハの
クラックを確実にかつ簡便に検出することのできる半導
体ウェーハの評価方法を提供することを目的とする。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor wafer evaluation method that can reliably and easily detect cracks in a wafer.

[課題を解決するための手段] 第1請求項の発明は、上面に開口する空洞部を有する支
持部材の上に半導体ウェーハを被検査面を下方にして載
せ、この半導体ウェーハの中央部に予め設定した一定の
荷重で負荷をかけ、破断の有無により微小クランクの存
否を判定し、また、第2請求項の発明は、上面に開口す
る空洞部を有する支持部材の上に半導体ウエーノ\を被
検査面を下方にして載せ、この半導体ウェーハに予め設
定した一定量の変形を与え、破断の有無により微小クラ
ックの存否を判定する。
[Means for Solving the Problems] The invention of the first claim is such that a semiconductor wafer is placed on a supporting member having a hollow portion opening on the upper surface with the surface to be inspected facing downward, and a central portion of the semiconductor wafer is placed in advance. A predetermined constant load is applied, and the presence or absence of a microcrank is determined based on the presence or absence of breakage. The semiconductor wafer is placed with its inspection surface facing downward, and a predetermined amount of deformation is applied to the semiconductor wafer, and the presence or absence of microcracks is determined based on the presence or absence of breakage.

「作用」 以下、本発明の半導体ウェーl\の評価方法を詳しく説
明する。
"Function" Hereinafter, the method for evaluating the semiconductor wafer I\ of the present invention will be explained in detail.

シリコン単結晶は650℃以下では、外力か加わると、
金属のように弾性変形および塑性変形を起こさずに、弾
性変形の途中で突然脆性破壊を起こす性質を持っている
。この脆性破壊強度はクラックの存在の有無によって非
常に敏感に変化し、クラックの存在によって急激に低下
することが知られている。
When a silicon single crystal is exposed to an external force at temperatures below 650°C,
Unlike metals, it does not undergo elastic or plastic deformation, but has the property of suddenly undergoing brittle fracture during elastic deformation. It is known that this brittle fracture strength changes very sensitively depending on the presence or absence of cracks, and is rapidly reduced by the presence of cracks.

第1請求項の発明の方法は、このクランクに敏感な脆性
破壊強度を指標にし、クラックの存在しないウェーハの
破壊に至る強度の臨界値の下限よりも低い破壊強度を示
す場合をクランクの存在するウェーハとみなすことかで
きることを利用している。そのために、まずクラックの
存在しない正常な標準品の破壊強度の臨界値を求めてお
き、さらにその統計的な変動の範囲も求めておく。
The method of the invention of claim 1 uses the brittle fracture strength sensitive to the crank as an index, and indicates that the crack exists when the fracture strength is lower than the lower limit of the critical value of the strength leading to the fracture of a wafer without cracks. It takes advantage of what can be considered a wafer. To this end, first, the critical value of the breaking strength of a normal standard product with no cracks is determined, and then the range of statistical variation thereof is also determined.

このようにして、クラックの存在しない正常なウェーハ
の破壊強度の臨界値を求めた後、上面に開口する空洞部
を有する支持部材の上に半導体ウェーハを被検査面を下
方にして載せ、この半導体ウェーへの中央部に上方より
この臨界値の95%程度の値の荷重をかけ、破断の有無
により微小クラックの存否を判定する。
After determining the critical value of the breaking strength of a normal wafer with no cracks in this way, the semiconductor wafer is placed with the surface to be inspected downward on a support member having a cavity opening on the top surface. A load of approximately 95% of this critical value is applied from above to the center of the wafer, and the presence or absence of microcracks is determined based on the presence or absence of breakage.

このように、ウェーハのクラックの有無を評価する際に
、上記破壊強度はその都度絶対値を求めて評価を行うよ
りも、クラックの存在しない正常な標準品と比較した破
壊強度の相対値によって評価するのはより簡便である。
In this way, when evaluating the presence or absence of cracks in a wafer, the above-mentioned breaking strength is evaluated based on the relative value of the breaking strength compared to a normal standard product with no cracks, rather than evaluating the absolute value each time. It is easier to do so.

また、第2請求項の発明は、シリコンの変形量がクラッ
クに敏感であることができることを利用している。その
ために、一定の荷重に対するクラックの存在しない正常
な標準品の変形量の限界を求めておき、さらにその統計
的な変動の範囲も求めておく。そして、上面に開口する
空洞部を有する支持部材の上に半導体ウェーハを被検査
面を下方にして載せ、この半導体ウェーハの中央部に一
定の値の荷重をかけ、変形量が上記の限界値のとちらに
あるかで微小クラックの存否を判定する。
Further, the invention of claim 2 utilizes the fact that the amount of deformation of silicon can be sensitive to cracks. For this purpose, the limit of the amount of deformation of a normal standard product with no cracks under a certain load is determined, and the range of statistical variation thereof is also determined. Then, a semiconductor wafer is placed on a support member having a cavity opening on the top surface with the surface to be inspected facing downward, and a constant load is applied to the center of the semiconductor wafer until the amount of deformation reaches the above limit value. The presence or absence of microcracks is determined by whether or not they are present.

[実施例] 以下、図面を参照してこの発明の一実施例を説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の半導体ウェーハのクラックの有無を評
価するための装置の一例を示すものである。
FIG. 1 shows an example of an apparatus for evaluating the presence or absence of cracks in a semiconductor wafer according to the present invention.

装置1は上面に開口する空洞部を有するリング状の支持
部材2と圧子3とからなっている。支持部材2にはウェ
ーハの周辺端部を載せるための溝部4が形成されている
The device 1 consists of a ring-shaped support member 2 having a cavity opening on the top surface and an indenter 3. A groove 4 is formed in the support member 2 for placing the peripheral edge of the wafer.

この装置1を用いてウェーハのクラックの有無を評価す
るには、まずウェーハ5をその周辺端部5aを溝部4の
上に載せることによって支持部材2の上に載置する。こ
の際ウェーハ5の被検査面の裏面か圧子3側にくるよう
にしておく。
In order to evaluate the presence or absence of cracks in a wafer using this apparatus 1, first the wafer 5 is placed on the support member 2 by placing its peripheral edge 5a on the groove 4. At this time, the wafer 5 should be placed on the back side of the surface to be inspected or on the indenter 3 side.

この支持部材2の寸法は直径か3−o3〜10−.3イ
ンチであり、この上に載置するウェーハの大きさに対応
している。また溝部4の寸法はその幅か0.3〜1 、
0 mm程度である。このようにすることによって、ウ
ェーハ5の中央部6を圧子3によって押した際に、ウェ
ーハ5全体に力か加わるようになっている。
The dimensions of this support member 2 are 3-o3 to 10-. It is 3 inches, which corresponds to the size of the wafer placed on it. In addition, the dimensions of the groove portion 4 are 0.3 to 1 in width,
It is about 0 mm. By doing this, when the center portion 6 of the wafer 5 is pressed by the indenter 3, force is applied to the entire wafer 5.

さらに圧子3の寸法はその径Rが5〜4C)nmで、重
さは1〜500gである。そして、再現性の良いデータ
を得るためには、この圧子3をウエーノ15に接触させ
る際の速度は0.1〜500117分の範囲にくるよう
に設定しておくのが好適である。
Further, the indenter 3 has a diameter R of 5 to 4 C) nm and a weight of 1 to 500 g. In order to obtain data with good reproducibility, the speed at which the indenter 3 is brought into contact with the wafer 15 is preferably set within a range of 0.1 to 500117 minutes.

チョクラルスキー引き上げ法によって作成したシリコン
単結晶のインゴットから厚さ450μm。
450 μm thick from a silicon single crystal ingot made by Czochralski pulling method.

面方位(100)の4インチウエーノ\を作成した。A 4-inch Ueno\ with surface orientation (100) was created.

上記ウェーハの作成工程は、シリコン単結晶のインゴッ
トをスライスした後、歪取りのために、HFとHNO3
とCH,C0OHを体積比テ1 :3 :1に混合した
エツチング液によって化学エツチングを行った後、ラッ
ピングおよび表面研摩を行った。また化学エツチングの
時間を100秒としたものをサンプルAとし、10秒と
したものをサンプルBとした。
The above wafer creation process involves slicing a silicon single crystal ingot and then using HF and HNO3 to remove distortion.
After chemical etching was performed using an etching solution containing CH, COOH mixed in a volume ratio of 1:3:1, lapping and surface polishing were performed. Sample A was obtained by chemical etching for 100 seconds, and sample B was obtained by chemical etching for 10 seconds.

上記の工程によって作成したサンプルAとサンプルBの
ウェーハを、それぞれ第1図に示した装置および引張試
験機を用いてその破壊強度を求めた。この結果を第2図
に示す。
The breaking strength of the sample A and sample B wafers prepared through the above steps was determined using the apparatus and tensile tester shown in FIG. 1, respectively. The results are shown in FIG.

第2図より化学エツチングの時間が100秒であるサン
プルA(12枚)のウエーノ\と、10秒であるサンプ
ルB(20枚)のウエーノ\の破壊強度の分布には明確
な差があることがわかる。このことから化学エツチング
の時間が10秒であるウェーハ(サンプルB)には微少
なりラックが存在していることがわかる。よってこの場
合には、正常なウェーハ(クラックの存在しないウエー
ノ\)であるサンプルAのウエーノ\の破壊強度の下限
(I(20kg重)を臨界強度とする。
From Figure 2, there is a clear difference in the distribution of fracture strength between Sample A (12 sheets), whose chemical etching time was 100 seconds, and Sample B (20 sheets), whose chemical etching time was 10 seconds. I understand. From this, it can be seen that the wafer (sample B) for which the chemical etching time was 10 seconds had a slight rack. Therefore, in this case, the lower limit (I (20 kg weight) of the breaking strength of the wafer of sample A, which is a normal wafer (wafer without cracks), is the critical strength.

従って、上記の加工工程によって作成されたウェーハの
クラックの存在することによる破壊強度の上限値は20
kg重の95%程度の値に設定する。
Therefore, the upper limit of the fracture strength due to the presence of cracks in the wafer created by the above processing process is 20
Set the value to approximately 95% of the kg weight.

また、この20kg重の力を装置1の圧子3によってウ
ェーハにかけた場合のウェーハの変形量は引張試験器で
の変位計によって測定したところ2゜10mmであった
。よって、本発明の方法においてはこの変形量2.1O
n+mの95%程度のところて圧子3か停止するように
設定して試験すれば、ウェーハのクラックの有無を非常
に簡便にかつ確実に知ることができる。
The amount of deformation of the wafer when a force of 20 kg was applied to the wafer by the indenter 3 of the apparatus 1 was 2.degree. 10 mm as measured by a displacement meter in a tensile tester. Therefore, in the method of the present invention, this deformation amount is 2.1O
If the indenter 3 is set to stop at about 95% of n+m and tested, the presence or absence of cracks in the wafer can be determined very easily and reliably.

[発明の効果] 以上詳述したように、本発明の半導体ウェハーの評価方
法によれば、第1請求項の発明は、上面に開口する空洞
部を有する支持部材の上に半導体ウェーハを被検査面を
下方にして載せ、この半導体ウェーハの中央部に予め設
定した一定の荷重で負荷をかけ、破断の有無により微小
クラックの存否を判定し、また、第2請求項の発明は、
上面に開口する空洞部を有する支持部材の上に半導体ウ
ェーハを被検査面を下方にして載せ、この半導体ウェー
ハに予め設定した一定量の変形を与え、破断の有無によ
り微小クラックの存否を判定するので、ウェーハ全体の
微少クラックの有無の評価を確実にかつ簡便に知ること
かできる。
[Effects of the Invention] As described in detail above, according to the semiconductor wafer evaluation method of the present invention, the invention of the first claim is such that the semiconductor wafer to be inspected is placed on the support member having the hollow portion opening on the upper surface. The semiconductor wafer is placed with its surface facing downward, a predetermined constant load is applied to the central part of the semiconductor wafer, and the presence or absence of microcracks is determined based on the presence or absence of breakage.
A semiconductor wafer is placed with the surface to be inspected facing downward on a support member having a cavity opening on the top surface, a predetermined amount of deformation is applied to the semiconductor wafer, and the presence or absence of microcracks is determined based on the presence or absence of breakage. Therefore, the presence or absence of microcracks on the entire wafer can be evaluated reliably and easily.

従って、この方法によってウエーノ1を管理すれば、従
来見落としていたクラ、りの存在するウェーハや加工工
程そのものを確実に排除することができ、生産性および
信軌性の向上に大きく貢献する。
Therefore, if the wafer 1 is managed using this method, it is possible to reliably eliminate wafers and the processing process itself in which cracks and defects, which have been overlooked in the past, are present, and this greatly contributes to improving productivity and reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体ウェーハのクラックの有無を評
価するための装置の一例を示すもの、第2図は加工工程
の異なる半導体ウエーノ\をそれぞれ第1図に示した装
置および引張試験機を用いてその破壊強度を求めた結果
を頻度で表したグラフである。 2・・・支持部材、 5・・・半導体ウェーハ 5a・・・周辺端部、 6・・・半導体ウェーハの中央部。
Figure 1 shows an example of an apparatus for evaluating the presence or absence of cracks in semiconductor wafers according to the present invention, and Figure 2 shows an example of the apparatus and tensile testing machine shown in Figure 1 for semiconductor wafers processed in different processing steps. This is a graph showing the results of determining the fracture strength using frequency. 2... Supporting member, 5... Semiconductor wafer 5a... Peripheral end, 6... Center of semiconductor wafer.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体ウェーハの被検査面の微小クラックの存否
を判定する半導体ウェーハの評価方法において、 上面に開口する空洞部を有する支持部材の上に半導体ウ
ェーハを被検査面を下方にして載せ、この半導体ウェー
ハの中央部に上方より予め設定した一定の荷重で負荷を
かけ、破断の有無により微小クラックの存否を判定する
ことを特徴とする半導体ウェーハの評価方法。
(1) In a semiconductor wafer evaluation method that determines the presence or absence of microcracks on the surface to be inspected of a semiconductor wafer, a semiconductor wafer is placed with the surface to be inspected downward on a support member having a hollow portion opening on the top surface. A semiconductor wafer evaluation method characterized by applying a preset constant load from above to the center of the semiconductor wafer, and determining the presence or absence of microcracks based on the presence or absence of breakage.
(2)半導体ウェーハの被検査面の微小クラックの存否
を判定する半導体ウェーハの評価方法において、 上面に開口する空洞部を有する支持部材の上に半導体ウ
ェーハを被検査面を下方にして載せ、この半導体ウェー
ハに予め設定した一定量の変形を与え、破断の有無によ
り微小クラックの存否を判定することを特徴とする半導
体ウェーハの評価方法。
(2) In a semiconductor wafer evaluation method for determining the presence or absence of microcracks on the surface to be inspected of a semiconductor wafer, a semiconductor wafer is placed with the surface to be inspected downward on a support member having a cavity portion opening on the upper surface; A method for evaluating a semiconductor wafer, which comprises applying a predetermined amount of deformation to the semiconductor wafer, and determining the presence or absence of microcracks based on the presence or absence of breakage.
JP5013590A 1990-03-01 1990-03-01 Evaluation of semiconductor wafer Pending JPH03252151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5013590A JPH03252151A (en) 1990-03-01 1990-03-01 Evaluation of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5013590A JPH03252151A (en) 1990-03-01 1990-03-01 Evaluation of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH03252151A true JPH03252151A (en) 1991-11-11

Family

ID=12850704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5013590A Pending JPH03252151A (en) 1990-03-01 1990-03-01 Evaluation of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH03252151A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332536A (en) * 2005-05-30 2006-12-07 Shin Etsu Handotai Co Ltd Device and method of inspecting cracking in wafer and manufacturing method of wafer
JP2013254905A (en) * 2012-06-08 2013-12-19 Mitsubishi Electric Corp Probing stage for semiconductor wafer, semiconductor inspection device, and method of determining stage groove width

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332536A (en) * 2005-05-30 2006-12-07 Shin Etsu Handotai Co Ltd Device and method of inspecting cracking in wafer and manufacturing method of wafer
JP2013254905A (en) * 2012-06-08 2013-12-19 Mitsubishi Electric Corp Probing stage for semiconductor wafer, semiconductor inspection device, and method of determining stage groove width

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