JPH03252148A - Bump structure of tab inner lead and its formation - Google Patents

Bump structure of tab inner lead and its formation

Info

Publication number
JPH03252148A
JPH03252148A JP4991190A JP4991190A JPH03252148A JP H03252148 A JPH03252148 A JP H03252148A JP 4991190 A JP4991190 A JP 4991190A JP 4991190 A JP4991190 A JP 4991190A JP H03252148 A JPH03252148 A JP H03252148A
Authority
JP
Japan
Prior art keywords
bump
inner lead
bonding
hollow
lsi chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4991190A
Other languages
Japanese (ja)
Inventor
Yasuhiro Otsuka
泰弘 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4991190A priority Critical patent/JPH03252148A/en
Priority to US07/510,208 priority patent/US5123163A/en
Publication of JPH03252148A publication Critical patent/JPH03252148A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a structure capable of attaining bonding to semiconductor elements with sufficient bonding strength and high reliability despite of dispersion in bump height in a simple process of forming bumps by inlaying the inner face of a hollow bump with a material whose melting point is higher than a temperature in bonding of an LSI chip and its bump. CONSTITUTION:A bump 15 formed in the vicinity of the tip of an inner lead 14 of a TAB tape carrier is structured in hollow, and the inner face of its hollow bump 15 is inlaid with a stopper material 16 whose melting point is higher than a temperature in bonding of an LSI chip and its hollow bump 15. In the case of forming the bump 15 in the vicinity of the tip of an inner lead 14 of the TAB tape carrier, the inner lead 14 is loaded with a sheet of material 13 whose melting point is higher than a temperature in bonding of an LSI chip and its hollow bump 15, and this material 13 is punched out by mechanical pressing using a punch 12 and a die 11, and the inner lead 14 is continuously press-molded into the bump 15.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体素子の実装に用いられるTAB(Ta
pe Automated Bonding)用テープ
キャリアのインナーリード先端部に形成されるバンプの
構造およびその形成方法に関する。
Detailed Description of the Invention (Field of Industrial Application) The present invention is directed to a TAB (Ta
The present invention relates to the structure of a bump formed at the tip of an inner lead of a tape carrier for (Automated Bonding) and a method for forming the same.

(従来の技術) 一般に、半導体素子をTAB用テープキャリアに実装す
るには、半導体素子の電極部またはテープキャリアのイ
ンナーリード先端部のいずれか一方に、バンプとなる突
起を形成する必要がある。半導体素子の電極部にバンプ
形成する方法には、例えば、アイビーエムジャーナル(
IBM Journal)第8巻(1964年)102
頁に記載のように電極部に直接バンプとなる突起をメツ
キ法により形成する方法や、エレクトロニック・パッケ
ージング・アンド・プロダクション(Electron
ic Packaging & Production
)、1984年12月号、33〜39頁に記載のように
エツチング技術を用いたペデスタル法、すなわちバンプ
を形成する部分をマスキングしておき、他のインナーリ
ード部分をハーフエツチングすることにより、30〜4
0pmの高さの突起を形成する方法がある。しかし、こ
れらの方法でバンプを形成するには、高価な露光装置や
メツキ装置などの設備が必要となるだけでなく、パター
ニングのためのりソゲラフイエ程やエツチング工程が必
要になるためバンプ形成工程も長くなる課題がある。
(Prior Art) Generally, in order to mount a semiconductor element on a TAB tape carrier, it is necessary to form a protrusion that becomes a bump on either the electrode part of the semiconductor element or the inner lead tip of the tape carrier. For example, there are methods for forming bumps on the electrodes of semiconductor devices, as described in IBM Journal (
IBM Journal) Volume 8 (1964) 102
There is a method of forming protrusions that will become bumps directly on the electrode part using the plating method as described in the page, and a method of forming bumps directly on the electrode part,
IC Packaging & Production
), December 1984 issue, pages 33 to 39, the pedestal method using etching technology, that is, masking the part where the bump will be formed and half-etching the other inner lead parts, is used. ~4
There is a method of forming protrusions with a height of 0 pm. However, forming bumps using these methods not only requires expensive equipment such as exposure equipment and plating equipment, but also requires a photolithography process and an etching process for patterning, making the bump formation process long. There is a problem.

このため、特公昭64−10094号公報に記載のよう
に金型を用いた機械的なプレス成形加工技術を用いてイ
ンナーリード先端部にペデスタルを製作する方法が提案
されている。この方法は第4図(a)に示すように、下
型23ヘフイルム21とインナーリード14が一体とな
ったテープキャリア22を装着し、上方からインナーリ
ード14の幅よりも大きな凸部27を有する上型24を
降下させて、第4図(e)に示すようにインナーリード
14の先端部に四部28をプレス成形よって形成し、バ
ンプとなるペデスタル25をインナーリード先端部に形
成する方法である。なお、上型24の凸部27により押
圧されたインナーノード14の凹部28の材料の逃げの
ため、第4図(b)に示すように輻方向に切欠き26が
設けられている。
For this reason, a method has been proposed in which a pedestal is manufactured at the tip of the inner lead using a mechanical press forming technique using a mold, as described in Japanese Patent Publication No. 10094/1983. In this method, as shown in FIG. 4(a), a tape carrier 22 in which a film 21 and an inner lead 14 are integrated is attached to a lower die 23, and a convex portion 27 larger than the width of the inner lead 14 is formed from above. In this method, the upper die 24 is lowered, and as shown in FIG. 4(e), a four part 28 is formed at the tip of the inner lead 14 by press molding, and a pedestal 25, which becomes a bump, is formed at the tip of the inner lead. . In order to allow the material in the recess 28 of the inner node 14 pressed by the projection 27 of the upper mold 24 to escape, a notch 26 is provided in the radial direction as shown in FIG. 4(b).

(発明が解決しようとする課題) ところが、このようなプレス加工方法によりインナーリ
ード先端部に成形されたバンプつまりペデスタル25は
、中実構造であるため、半導体素子とバンプを熱圧着で
接合する工程において作用させる圧縮荷重に対して、は
ぼ剛体として作用する。このため個々のバンプの高さに
バラツキがあると、半導体素子とバンプを接合するとき
、すべてのバンプを均一に接合することができず、電気
的に接続不良が発生するという課題がある。接続不良を
発生させないためには、バンプの高さのバラツキを少な
くとも0.5pm以下とすることが必要であり、極めて
高精度にバンプを形成することが要求される。また、イ
ンナーリードの四部には、事前に切欠きを設ける加工を
行う必要がある等の課題もある。
(Problem to be Solved by the Invention) However, since the bump or pedestal 25 formed at the tip of the inner lead by such a press working method has a solid structure, it is difficult to bond the semiconductor element and the bump by thermocompression bonding. It acts as a rigid body in response to the compressive load applied to it. For this reason, if there is variation in the height of individual bumps, there is a problem that when bonding the bumps to the semiconductor element, it is not possible to bond all the bumps uniformly, resulting in electrical connection failures. In order to prevent connection failures, it is necessary to limit the variation in the height of the bumps to at least 0.5 pm or less, and it is required to form the bumps with extremely high precision. Further, there are also problems such as the need to process the four parts of the inner lead to provide notches in advance.

本発明の目的はこのような従来の課題を解決し、バンプ
形成工程が簡単で、バンプ高さのバラツキが存在しても
十分な接合強度で、しかも信頼性高く半導体素子との接
合が達成できるインナーノードのバンプ構造およびその
形成方法を提供することにある。
The purpose of the present invention is to solve these conventional problems, to simplify the bump formation process, to achieve sufficient bonding strength even with variations in bump height, and to achieve highly reliable bonding with semiconductor elements. An object of the present invention is to provide a bump structure for an inner node and a method for forming the same.

(課題を解決するための手段) 本発明のTABインナーリードのバンプ構造は、前記バ
ンプが中空構造であり、かつ該中空構造バンプの内面に
、LSIチップと前記中空構造バンプとのボンディング
時の温度よりも融点が高い材料を埋め込んで構成される
(Means for Solving the Problems) In the bump structure of the TAB inner lead of the present invention, the bump has a hollow structure, and the temperature at which the LSI chip and the hollow structure bump are bonded is set on the inner surface of the hollow structure bump. It is constructed by embedding a material with a higher melting point.

本発明のTABインナーリードのバンプ形成方法は、イ
ンナーリード上に、LSIチップと前記中空構造バンプ
とのボンディング時の温度よりも融点が高い薄板状の材
料を配置し、ポンチとダイスを用いた機械的なプレス法
により、前記薄板状の材料を打ち抜くとともに、連続的
に前記インナーリードをプレス成形しバンプを形成して
構成される。
The method for forming bumps on TAB inner leads of the present invention is to place a thin plate-like material on the inner leads with a melting point higher than the temperature at which the LSI chip and the hollow structure bumps are bonded, and use a machine using a punch and a die. The thin plate-like material is punched out using a conventional pressing method, and the inner leads are continuously press-molded to form bumps.

(作用) 本発明のバンプ構造は、第1図に示すようなインナーリ
ード14の幅よりも小さなドーム状に形成した中空構造
のバンプ15である。中空構造バンプではバンプ形成の
ための前加工が不要となりバンプ形成工程を大幅に簡略
化できる利点があり、しかも中実構造に比べ圧縮力に対
して変形し易いバンプ構造となるため、バンプの高さに
バラツキが存在しても熱圧着時の圧縮荷重によりバンプ
が塑性変形し、均一な高さにバンプ高さを矯正すること
ができる。
(Function) The bump structure of the present invention is a hollow bump 15 formed in a dome shape smaller in width than the inner lead 14 as shown in FIG. Hollow structure bumps have the advantage of greatly simplifying the bump formation process by eliminating the need for pre-processing for bump formation.Moreover, the bump structure is more easily deformed by compressive force than solid structures, so it is possible to increase the height of the bump. Even if there is variation in the bump height, the bump is plastically deformed by the compressive load during thermocompression bonding, and the bump height can be corrected to a uniform height.

しかしその反面中空構造のバンプでは、僅かな圧縮荷重
でバンプが押し潰されてしまうため、熱圧着後に十分な
バンプ高さを確保することが困難であり、また、変形抵
抗が小さいため、熱圧着時にバンプとLSIチップ上の
電極部とを十分な圧力で密着させることができず、十分
な強度でボンディングすることが困難である課題があっ
た。そこで本発明のバンプ構造では、中空構造バンプ1
5の内面に熱圧着時の温度よりも融点が高いストッパー
材料16が埋め込まれている。このため第3図に示すよ
うに本発明の中空構造のバンプは、熱圧着時の圧縮荷重
によりまず中空バンプとして容易に塑性変形を開始する
が、ストッパー材料16がボンディングツール19に接
触すると、従来の中実構造のバンプと同様にほぼ剛体構
造のバンプとして作用するため、バンプ15とLSIチ
ップの電極18とを十分な圧力で密着させることが可能
となる。またバンプ高さは、ストッパ材料16の厚さを
変えることにより容易に調整でき、熱圧着後にも十分な
バンプ高かを確保することが可能となる。
However, on the other hand, with hollow bumps, it is difficult to ensure sufficient bump height after thermocompression bonding because the bumps are crushed by a slight compressive load, and because the deformation resistance is low, There has been a problem in that sometimes it is not possible to bring the bumps and the electrodes on the LSI chip into close contact with each other with sufficient pressure, making it difficult to bond with sufficient strength. Therefore, in the bump structure of the present invention, the hollow structure bump 1
A stopper material 16 having a melting point higher than the temperature at the time of thermocompression bonding is embedded in the inner surface of 5. Therefore, as shown in FIG. 3, the bump having the hollow structure of the present invention easily starts plastic deformation as a hollow bump due to the compressive load during thermocompression bonding, but when the stopper material 16 comes into contact with the bonding tool 19, Since it acts as a substantially rigid bump like the solid bump, it is possible to bring the bump 15 and the electrode 18 of the LSI chip into close contact with each other with sufficient pressure. Further, the bump height can be easily adjusted by changing the thickness of the stopper material 16, making it possible to ensure a sufficient bump height even after thermocompression bonding.

上記のような構造の中空構造のバンプは、インナーリー
ド上にストッパー材料となる薄板状の材料を配置し、ポ
ンチとダイスを用いた機械的なプレス法により、前記薄
板状の材料を打ち抜くとともに、前記インナーリードを
プレス成形することにより、中空構造内面にストッパ材
料を埋め込むことができ、容易に形成することができる
In order to obtain a bump having a hollow structure as described above, a thin plate-shaped material serving as a stopper material is placed on the inner lead, and the thin plate-shaped material is punched out by a mechanical pressing method using a punch and a die. By press-molding the inner lead, the stopper material can be embedded in the inner surface of the hollow structure, and the inner lead can be easily formed.

(実施例) 以下本発明について図面を用いて詳細に説明する。第1
図は、本発明のインナーリードのバンプ構造の一実施例
を示す断面図、第2図(a)、(b)は、本発明のバン
プ形成方法の一実施例を工程順に示す断面図である。
(Example) The present invention will be described in detail below with reference to the drawings. 1st
The figure is a cross-sectional view showing an embodiment of the bump structure of the inner lead of the present invention, and FIGS. 2(a) and 2(b) are cross-sectional views showing an embodiment of the bump forming method of the present invention in the order of steps. .

まず第2図(a)に示すように、ダイス11上にインナ
ーリード14および板厚30μmのCu箔13を配置し
、ダイス11の中心軸と軸心を一致させてポンチ12を
固定した。ここで、ダイス穴17の直径は70pmであ
り、ポンチの直径は50pmとした。次いで第2図(b
)に示すようにポンチ12を徐々に下方に移動しインナ
ーリード14をプレス成形したところ、Cu箔13は打
ち抜かれ、インナーリード14上に第1図に示すような
ストッパー材料16が埋め込まれた中空構造のバンプ1
5を形成することができた。なお、打ち抜かれたCu箔
13がストッパー材料16として作用する。ここで、イ
ンナーリードは幅100νm、厚さ30pm、ピッチ2
00pmのCu箔にAuメツキをlpm施したものを用
いた。
First, as shown in FIG. 2(a), an inner lead 14 and a Cu foil 13 having a thickness of 30 μm were placed on the die 11, and the punch 12 was fixed so that the central axis of the die 11 and the axis coincided with each other. Here, the diameter of the die hole 17 was 70 pm, and the diameter of the punch was 50 pm. Next, Figure 2 (b
), the punch 12 was gradually moved downward to press-form the inner lead 14, the Cu foil 13 was punched out, and a hollow hole was formed on the inner lead 14 in which a stopper material 16 was embedded as shown in FIG. Structure bump 1
We were able to form 5. Note that the punched Cu foil 13 acts as the stopper material 16. Here, the inner lead has a width of 100 νm, a thickness of 30 pm, and a pitch of 2.
00 pm Cu foil plated with 1 pm of Au was used.

形成された中空構造バンプ15の外径は70pm、内径
は50μmであり、バンプ高かは30±lpmであった
。また、中空構造バンプ15の断面観察を行ったところ
、バンプ内面に埋め込まれたストッパー材料16である
Cu箔13は、第1図に示すように僅かに深絞り加工さ
れたため、その厚さは25pmに減少した。
The formed hollow structure bump 15 had an outer diameter of 70 pm, an inner diameter of 50 μm, and a bump height of 30±lpm. Further, when observing the cross section of the hollow structure bump 15, the Cu foil 13, which is the stopper material 16 embedded in the inner surface of the bump, was slightly deep drawn as shown in FIG. 1, so its thickness was 25 pm. decreased to

以上のようにして形成した中空バンプ15とLSIチッ
プ18のAI電極19とを第3図に示すように低温ボン
ディング法(素子加熱温度=275°C1加圧用ツール
20の温度:450°C1圧力ニ60gf/リード、1
秒)により接合した結果、強度的(引張り強度:60g
f/1リード)にも電気的にも良好な接続が達成され、
インナーリードのバンプとして十分に使用できることを
確認した。バンプ高さに±lpmのバラツキがあるにも
かかわらず良好な接続を達成できたのは、ストッパー材
料16が加圧用ツール20と接触するまでは、バンプが
中空構造として作用し容易に塑性変形を生じ、全てのバ
ンプを均一な高さに矯正できたためであり、ボンディン
グ後のバンプ高さが20pmと十分な高さを確保できた
のは、ストッパー材料16が加圧用ツール20と接触す
ると、バンプがほぼ剛体構造として作用したためである
As shown in FIG. 3, the hollow bumps 15 formed as described above and the AI electrodes 19 of the LSI chip 18 are bonded using a low temperature bonding method (element heating temperature = 275°C1 temperature of the pressure tool 20: 450°C1 pressure bonding). 60gf/lead, 1
As a result of bonding (tensile strength: 60g)
f/1 lead) and electrically, a good connection is achieved.
It was confirmed that it can be used satisfactorily as a bump for inner leads. The reason why we were able to achieve a good connection despite the ±lpm variation in bump height is that the bumps act as a hollow structure and are easily plastically deformed until the stopper material 16 comes into contact with the pressurizing tool 20. This is because all the bumps could be corrected to a uniform height.The reason why the bump height after bonding was 20 pm, which was a sufficient height, was that when the stopper material 16 came into contact with the pressure tool 20, the bumps This is because it acted almost as a rigid structure.

最後に接合の信頼性を評価するために、半導体素子とイ
ンナーリードとの接合を行った後、120°C〜−40
°C(1サイクル/時間)の熱衝撃試験を500サイク
ルに行い、熱応力に対する強度試験を行なった。その結
果、本発明の一実施例によるバンプ構造では、接合不良
は全く生じないことを確認した。
Finally, in order to evaluate the reliability of the bonding, after bonding the semiconductor element and the inner lead, the
A thermal shock test at 500 degrees Celsius (1 cycle/hour) was conducted to test the strength against thermal stress. As a result, it was confirmed that in the bump structure according to an embodiment of the present invention, no bonding failure occurred at all.

(発明の効果) 以上説明したように、本発明のTABインナーリードの
バンプ構造では、バンプのバラツキが存在しても、バン
プと半導体素子の電極部とを均一に十分な接合強度でボ
ンディングでき、しかも接合後に熱応力や外力が作用し
ても接合不良が生じない信頼性の高い接合を実現できる
効果がある。
(Effects of the Invention) As explained above, with the bump structure of the TAB inner lead of the present invention, even if there are variations in the bumps, the bumps and the electrode portions of the semiconductor element can be bonded uniformly and with sufficient bonding strength. Furthermore, it is possible to realize highly reliable joining that does not cause a joining failure even if thermal stress or external force is applied after joining.

また本発明のTABインナーリードのバンプ形成方法で
は、中空構造のバンプの内面にストッパ材料を埋め込ん
だ中空構造のバンプを容易に形成できる効果がある。
Furthermore, the TAB inner lead bump forming method of the present invention has the effect of easily forming a hollow bump in which a stopper material is embedded in the inner surface of the hollow bump.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明のインナーリードのバンプ構造を示す
断面図、第2図(a)、 (b)はそれぞれ本発明のバ
ンプ形成方法を工程順に示す概略図、第3図は、本発明
の一実施例で形成した中空構造のバンプとLSIチップ
のAI電極部とのボンディング時の状態を示す断面図、
第4図(a)〜(e)はそれぞれ従来の中実構造バンプ
の形成方法を示す、断面図、平面図、および側面図であ
る。 11・・・ダイス、12・・・ポンチ、13・・・Cu
箔、14・・・インナーリード、15・・・中空構造バ
ンプ、16・・・ストッパー材料、17・・・ダイス穴
、18・・・LSIチップ、19・・・AI電極、20
・・・加圧用ツール、21・・・フィルム、22・・・
テープキャリア、23・・・下型、24・・・上型、2
5・・・ペデスタル、26・・・切欠き、27・・・凸
部、28・・・凹部
FIG. 1 is a sectional view showing the bump structure of the inner lead of the present invention, FIGS. 2(a) and 2(b) are schematic diagrams showing the bump forming method of the present invention in the order of steps, and FIG. 3 is a cross-sectional view showing the bump structure of the inner lead of the present invention. A cross-sectional view showing a state of bonding between a hollow bump formed in an example and an AI electrode part of an LSI chip,
FIGS. 4(a) to 4(e) are a sectional view, a plan view, and a side view, respectively, showing a conventional method for forming a solid bump. 11...Dice, 12...Punch, 13...Cu
Foil, 14... Inner lead, 15... Hollow structure bump, 16... Stopper material, 17... Dice hole, 18... LSI chip, 19... AI electrode, 20
...pressure tool, 21...film, 22...
Tape carrier, 23...lower mold, 24...upper mold, 2
5... Pedestal, 26... Notch, 27... Convex part, 28... Concave part

Claims (1)

【特許請求の範囲】 1、TAB用テープキャリアのインナーリード先端部近
傍に形成するバンプの構造において、前記バンプが中空
構造であり、かつ該中空構造バンプ内面に、LSIチッ
プと前記中空構造バンプとのボンディング時の温度より
も融点が高い材料を埋め込んだことを特徴とするTAB
インナーリードのバンプ構造。 2.TAB用テープキャリアのインナーリード先端部近
傍にバンプを形成する方法において、インナーリード上
に、LSIチップと前記中空構造バンプとのボンディン
グ時の温度よりも融点が高い薄板状の材料を配置し、ポ
ンチとダイスを用いた機械的なプレス法により、前記薄
板状の材料を打ち抜くとともに、連続的に前記インナー
リードをプレス成形しバンプを形成することを特徴とす
るTABインナーリードのバンプ形成方法。
[Claims] 1. In the structure of the bump formed near the tip of the inner lead of the TAB tape carrier, the bump has a hollow structure, and an LSI chip and the hollow structure bump are arranged on the inner surface of the hollow structure bump. A TAB characterized by being filled with a material whose melting point is higher than the bonding temperature of
Bump structure of inner lead. 2. In a method of forming a bump near the tip of an inner lead of a TAB tape carrier, a thin plate-like material having a melting point higher than the temperature at which the LSI chip and the hollow structure bump are bonded is placed on the inner lead, and a punch is formed. A method for forming bumps on a TAB inner lead, characterized in that the thin plate material is punched out by a mechanical pressing method using a die and a die, and the inner lead is continuously press-molded to form a bump.
JP4991190A 1989-04-27 1990-02-28 Bump structure of tab inner lead and its formation Pending JPH03252148A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4991190A JPH03252148A (en) 1990-02-28 1990-02-28 Bump structure of tab inner lead and its formation
US07/510,208 US5123163A (en) 1989-04-27 1990-04-17 Process and apparatus for forming bumps on film carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4991190A JPH03252148A (en) 1990-02-28 1990-02-28 Bump structure of tab inner lead and its formation

Publications (1)

Publication Number Publication Date
JPH03252148A true JPH03252148A (en) 1991-11-11

Family

ID=12844198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4991190A Pending JPH03252148A (en) 1989-04-27 1990-02-28 Bump structure of tab inner lead and its formation

Country Status (1)

Country Link
JP (1) JPH03252148A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US6034428A (en) * 1993-11-22 2000-03-07 Fujitsu Limited Semiconductor integrated circuit device having stacked wiring and insulating layers
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034428A (en) * 1993-11-22 2000-03-07 Fujitsu Limited Semiconductor integrated circuit device having stacked wiring and insulating layers
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US5804467A (en) * 1993-12-06 1998-09-08 Fujistsu Limited Semiconductor device and method of producing the same
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
US6379997B1 (en) 1993-12-06 2002-04-30 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same

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