JPH03250761A - Manufacture of semiconductor memory element - Google Patents

Abstract

PURPOSE:To restrain the effective channel length from shortening by a method wherein an electrode connecting to at least a storage electrode for capacitor out of the electrodes of MOS type transistor for memory cell is covered with a mask. CONSTITUTION:An electrode 16 connecting to at least a storage electrode 14 for capacitor out of the electrodes of MOS type N channel transistor for memory cell is covered with a mask covering a P type transistor part in ambient circuit during phosphorus ion implanting process for the formation of N<->region in LDD(lightly doped drain) structure of the N channel transistor. Accordingly, the N<->region in the MOS type transistor is not formed in the electrode region not implanted with phosphorus. However, the impurities are diffused from the contact part of the storage electrode 14 for capacitor with a cell transistor during the process after the formation of said electrode 14 so as to form the phosphorus diffused region in the peripheral part of an N<+> diffused region. Through these procedures, the phosphorus concentration in the region near the channel is lowered to restrain the effective gate length from shortening.

Description

[Detailed Description of the Invention] <Industrial Field of Application> The present invention relates to a method for manufacturing a semiconductor memory device, and more specifically, to a method for manufacturing a memory cell of a dynamic random access memory (hereinafter referred to as DRAM). Regarding the method.

<Conventional technology> The storage capacity of DRAM, which is at the forefront of high integration, is increasing at a rate of four times every three years, and in the future it will increase to 16Mb and 64Mb.
It is expected that the capacity will gradually increase to 256Mb and 256Mb. In order to improve the degree of integration, it is necessary to reduce the area of memory cells, which are the storage units of DRAMs. After 4 Mb DRAM, in order to maintain a constant capacitance of a memory cell while reducing the area of the memory cell, the capacitor structure has become three-dimensional, and a stacked memory cell with high area utilization efficiency is desired.

On the other hand, with the miniaturization of elements, a decrease in breakdown voltage due to an increase in the internal electric field of a transistor and deterioration of element characteristics due to hot carriers have become problems. Therefore, in order to suppress the hot carrier effect and increase the reliability of the device, an n-resistance section is provided at the source and drain of the transistor, and an LDD (light
Ly doped drain.

A write doped drain structure is used.

<Problems to be Solved by the Invention> FIG. 1O shows a cross-sectional view of a general stacked memory cell. Here, 101 is a storage electrode serving as one electrode of the memory cell capacitor, and 102 is a plate electrode serving as the other electrode. Further, 103 is a gate electrode of an NMOS transistor that becomes a memory cell transistor, 104 is a source region of a memory cell transistor connected to the storage electrode 101 via a contact portion 105, and 106 is a source region of a bit line 107 and a contact portion 108. This is the drain electrode of the memory cell transistor connected through the gate. 109
is the channel portion of the memory cell transistor. Incidentally, as shown in FIG. 9, the pit line 107 and the memory cell MO
Contact with the electrode portion of the S-type transistor may be formed using a W plug.

In a DRAM having such a stacked memory cell, since a capacitor is formed after forming a MOS transistor, impurities are diffused from the capacitor storage electrode. The storage electrode 101 is arranged so that the capacitor capacitance is not reduced.
O'. An impurity concentration of approximately /c*" must be maintained, and in normal DrLAM, phosphorus, which is easily diffused, is used as an impurity. Phosphorus has a larger diffusion coefficient in Sl than arsenic. Memory cell area As you reduce the
The distance between the contact portion 105 between the capacitor storage electrode 101 and the source electrode 104 of the N-channel cell transistor and the channel portion 109 of the cell transistor becomes shorter. Therefore, in the process after forming the storage electrode for the capacitor, impurities diffuse from the contact portion 105 to the vicinity of the channel of the cell transistor, further shortening the effective channel length of the cell transistor, which has the shortest gate length in the semiconductor memory element. The channel effect gets worse. In particular, in DrtAM with an integration density of megabits or more, an LDD structure is used for the transistor to prevent pot carriers, and there is an n- diffusion region on the channel side of the N+ diffusion region, and due to phosphorus diffusion from the capacitor storage electrode 101, the above-mentioned The phosphorus concentration in the n-diffused region increases and a decrease in the effective channel length occurs. As a result, deterioration of the off-characteristics of the cell transistor becomes a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor memory cell that does not cause the reduction in effective channel length as described above.

Means for Solving the Problems> In order to achieve the above object, the first invention comprises a MOS transistor formed on the surface of a semiconductor substrate, a capacitor formed on the surface of the semiconductor substrate, and a MOS transistor formed on the surface of the semiconductor substrate. A method for manufacturing a semiconductor memory device having a plurality of memory cells comprising a plurality of memory cells, the method comprising: ion-implanting a low concentration impurity to form a low concentration diffusion region of a source region or a drain region of the MO5 type transistor; Among the electrodes, at least the electrode connected to the capacitor is covered with a mask so that ion implantation of impurity at a lower concentration is not performed.

Further, the second invention is an MO formed on the surface of a semiconductor substrate.
A method for manufacturing a semiconductor memory element having a plurality of memory cells each including a S-type) transistor and a capacitor formed on the surface of the semiconductor substrate, the method comprising: In the step of ion-implanting high-concentration impurities to form a diffusion region, at least one of the MOS transistor electrodes connected to the capacitor is covered with a mask so that the high-concentration impurity ions are not implanted. It is characterized by

<Operation> The case of a MOS type transistor channel transistor of a memory cell will be explained.

No.! In the invention, at least the electrode connected to the storage electrode for the capacitor among the MO9 type N-type child channel transistor electrodes of the memory cell is connected to the P of the peripheral circuit when phosphorus ions are implanted to form the n-region of the LDD structure of the N-channel transistor. A mask covering the type transistor section is used.

Therefore, the electrode region does not undergo the above-mentioned phosphorus implantation and becomes a MOS
The n-region of the type transistor is not formed.

However, in a process after forming the capacitor storage electrode, impurities are diffused from the contact portion between the capacitor storage electrode and the cell transistor, and a phosphorus diffusion region is formed around the N+ diffusion region. Therefore, compared to the second normal process, the phosphorus concentration near the channel is lowered, and the shortening of the effective gate length is suppressed.

Further, in the second invention, the MOS type N of the memory cell
At least one of the electrodes of the channel transistor that is connected to the storage electrode for the capacitor is covered with a mask that covers the P-type transistor portion of the peripheral circuit during arsenic ion implantation to form the N+ region of the N-channel transistor.

Therefore, the electrode region is not subjected to the arsenic implantation and is not formed as an N+ region. As a result, the diffusion region of the memory cell transistor connected to the capacitor storage electrode is made up of phosphorus due to N- injection and phosphorus diffused from the capacitor storage electrode. Since there is no high concentration region, the diffusion distance of phosphorus is shortened, and the reduction in effective channel groups is suppressed. In addition, the ON resistance of the transistor will be high if there is no N+ diffusion region, but if the above-mentioned phosphorus diffusion becomes a problem, the contact part between the capacitor storage electrode and the memory cell transistor electrode and the channel of the memory cell transistor Since the distance between the bit lines is very short, the resistance will never become so high that the time taken to transfer charge from the capacitor to the bit line cannot be ignored.

In this way, both the first and second inventions can optimize the LDD structure transraster region concentration of the DRΔM peripheral circuit,
It is possible to suppress the decrease in the effective channel group of the memory cell transistor and maintain the off-characteristics of the cell transistor at a favorable level.

Note that among the electrodes of the MO9ffiN channel transistor of the memory cell, at least the electrode connected to the storage electrode for the capacitor is covered during the phosphorus ion implantation to form the n- region of the N channel transistor, and the N+ region of the N channel transistor is covered. It is also possible to cover the arsenic ion implantation during formation so that neither ion implantation is performed. The phosphorus concentration diffused from the storage electrode for the capacitor is on the order of IO"7 cm3, whereas the phosphorus a change in the n- region is on the order of 101"/cj13, so there is no significant influence.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

Examples include two embodiments of the first invention (first embodiment and second embodiment) and two embodiments of the second invention (third embodiment).
Example and Fourth Example). First, I will give an overview.

In the first embodiment, N channel transistor glue, I
) During the phosphorus ion implantation to form the groove region of the D structure, the electrode region connected to the storage electrode for the MO9 type N-type child channel transistor capacitor of the memory cell is covered by the mask covering the P-type transistor portion of the peripheral circuit. This ensures that the electrode region does not undergo phosphorus implantation.
- No region is formed.

In the second embodiment, the M of the memory cell is
It covers two electrode regions: the electrode connected to the capacitor storage electrode of the OS type N-channel transistor and the electrode connected to the bit line wiring. As a result, these two electrode regions do not undergo phosphorus implantation and no n-region is formed.

In the third embodiment, when arsenic ions are implanted to form the N+ region of the LDD structure of the N-channel transistor, the P-type transistor section of the peripheral circuit is connected to the capacitor storage electrode of the MOS-type N-channel transistor of the memory cell using a mask that covers the P-type transistor section. cover the electrode area. As a result, the electrode region is not subjected to the arsenic implantation described above and no N+ region is formed.

In the fourth embodiment, the M of the memory cell is
It covers two electrode areas: the electrode connected to the capacitor storage electrode of the O9 type N-channel transistor, and the electrode connected to the bit line wiring. As a result, these two electrode regions are not subjected to the arsenic implantation and are not formed as N+ regions.

Next, details of each embodiment will be explained based on the drawings.

The manufacturing method of these examples is characterized by the step of forming the source and drain of a transistor of the same type (peripheral circuit) as the memory cell transistor, and the other manufacturing steps were performed according to known procedures. In the process up to the source and drain forming steps of the memory cell transistor and the peripheral circuit transistor, as shown in FIG. 1(a), the device isolation region 1.
P well 2, N well 3, lead wire 4 forming the gate electrode of the cell transistor, gate electrode 5 of the NMOS transistor not forming part of the peripheral circuit, PM forming part of the peripheral circuit.
A gate electrode 6 and an insulating film 7 of the OS transistor are formed.

In the first embodiment, the state shown in FIG. 1(a) is changed from the state shown in FIG.
Proceed to state a). In FIG. 2(a), the MOS type transistor for the memory cell covers the r) channel transistor part of the peripheral circuit when phosphorus ions are implanted to form the n-region of the LDD structure of the peripheral circuit MOS type N-channel transistor. The resist mask 8 protects the electrode connected to the capacitor storage electrode. As a result, the MOS type transistor for the memory cell becomes a transistor in which an n- region is not formed on the electrode side connected to the storage Ti electrode for the capacitor. Thereafter, as shown in FIG. 3(a), a sidewall insulating film 10 is formed on the gate sidewall, and ions are implanted into the N+ region 11 and P+ region of the transistor.
Region 12 is formed. Here, 9 is a region formed in the step of FIG. 2(a). Next, after forming a Si0 film as an interlayer insulating film 13 on the transistor, a contact hole is opened on the electrode of the transistor to be connected to the capacitor storage electrode of the MOS transistor. And as a material for storage electrodes for capacitors,
After forming a polycrystalline silicon film, phosphorus diffusion is performed,
The storage electrode 14 is formed by etching this film.

Further, a capacitor insulating film 15 is formed, and a counter cell plate electrode 16 is processed using a polycrystalline silicon film in which phosphorus is diffused. Next, as shown in FIG. 3(b), a 5iOy film is formed as an interlayer insulating film 17 on the opposite cell plate electrode 16, and the other electrode connected to the capacitor storage electrode 14 of the transistor 1 is A contact hole is formed on the electrode.

Furthermore, polycide is formed as a material for bit line wiring,
This film is etched to form bit line wiring 18. Finally, as shown in FIG. 4, after a glabellar insulating film 19 is deposited and flattened, contact holes are opened by a known procedure and wiring is processed using A(!-9i alloy 20).

In the semiconductor memory device manufactured according to this example, the electrode region of the MOS type transistor for the memory cell connected to the storage electrode for the capacitor was formed by the process shown in FIG. 2(a).
- Although the transistor does not have a region formed, impurities are diffused from the contact portion between the capacitor storage electrode 14 and the transistor electrode during the thermal process after the formation of the capacitor storage electrode, forming the n-region 9 (FIG. 4). . Furthermore, the ninth
As shown in the figure, the contact between the bit line wiring and the electrode portion of the MOS type transistor for the memory cell may be formed using a W plug.

The second embodiment is the same as the first embodiment up to the horizontal gate a formation step shown in FIG. 1(a). after that,
Proceed to FIG. 2(b). In FIG. 2(b), a MOS type transistor for a memory cell has a peripheral circuit MO9 type N-type child channel transistor, and a resist covering the peripheral circuit l) channel transistor part at the time of ion implantation for forming the DD tank structure n-region. The mask 8 protects the two electrodes of the memory cell MOS transistor connected to the capacitor storage electrode and the human wiring, respectively.

As a result, the MO9 type transistor for memory cell becomes a transistor in which no n- region is formed in the two electrode regions. Thereafter, as shown in FIG. 5(a), a sidewall insulating film 10 is formed on the sidewall of the gate, and an N+ region +1 and a P+ region 12 of the transistor are formed by ion implantation. Further, a 5iOy film is formed as an interlayer insulating film 13, and a contact pole is formed on the other electrode of the transistor connected to the capacitor storage electrode.

Furthermore, polycide is formed as a material for bit line wiring,
This film is etched to form bit line wiring 18. Next, as shown in FIG. 5(b), after forming a 5iOz film as the interlayer insulating film 17, the above M OS! ! ! A contact hole is opened in the electrode of the transistor to be connected to the storage electrode for the capacitor of the transistor. After forming a polycrystalline silicon film as a material for the storage electrode for the capacitor, phosphorus is diffused, and this film is etched to form the storage electrode 14. Further, a capacitor insulating film 15 is formed, and a counter cell plate electrode 16 is processed using a polycrystalline silicon film in which phosphorus is diffused. Finally, as shown in FIG. 6, after depositing and planarizing an interlayer insulating film 19, contact holes are opened using a known procedure and wiring is processed using A12-3i alloy 20.

The semiconductor memory device manufactured according to this example is a MOS type memory cell connected to a storage electrode for a capacitor and a bit line wiring]・The electrode area of the transistor is shown in FIG. 2(b).
However, in the heat process after forming the storage electrode for the capacitor, impurities are diffused from the contact area between the storage electrode for the capacitor and the contact area between the wiring and the electrode for the memory cell. An n-region of an M, O3 type transistor is formed.

In the third embodiment, steps up to the gate electrode formation step shown in FIG. 1(a) are performed in the step 1 above. This is the same as the second embodiment. Thereafter, as shown in FIG. 1(b), an ion implantation process (n-region formation) is performed to form an n-region 9 and a sidewall insulating film 10.
is formed. Next, proceeding to FIG. 2(c), the electrode region connected to the capacitor storage electrode of the memory cell MOS type N-channel transistor is connected to the peripheral circuit MO9 type N-channel transistor and the memory cell MOS type N-channel transistor N+ A resist mask 8 is used to cover the P-type transistor portion of the peripheral circuit during arsenic ion implantation to form the region. As a result, the two-set electrode region is not subjected to the arsenic implantation described above, and an N+ region is not formed.

Next, as shown in FIG. 7(a), the P+ region 12 of the transistor is formed by ion implantation. After forming an SiOv film as an interlayer insulating film 13 on the transistor, a contact is made on the electrode of the transistor to be connected to the storage electrode for the capacitor of the MOS transistor.
・Open the hole. After forming a polycrystalline silicon film as a material for the capacitor storage electrode, phosphorus is diffused and the shoulder is etched to form the capacitor storage electrode 144. Furthermore, capacitor insulating film 1
5 is formed, and the opposing cell plate electrode 16 is processed using a polycrystalline silicon film in which phosphorus is diffused.

Next, as shown in No. 7i51(b), an interlayer insulating film 17 is formed on the above-mentioned opposing cell brake I-electrode, and S10. A contact hole is formed on the other electrode of the transistor connected to the capacitor storage electrode by forming a film. Furthermore, polycide is formed as a material for bit line wiring, and this film is etched to form bit line wiring 1.
form 8. Finally, as shown in FIG. 4, after depositing and planarizing the glabellar insulating film 19, contact holes are opened using a known procedure, and wiring is processed using A(!-3i alloy 20).

The semiconductor memory device manufactured according to this example has a MOS type transistor for the memory cell connected to the storage electrode for the capacitor.
Although an N+ region is not formed in the electrode region of the transistor by the process shown in FIG. A territory is formed.

The fourth embodiment is the same as the third embodiment up to the step of forming the n' region shown in FIG. 1(b). Thereafter, as shown in FIG. 2(d), the electrode region connected to the capacitor storage electrode and bit line wiring of the memory cell MOS type N-channel transistor is connected to the N+ of the LDD structure of the peripheral circuit MO9 type N-channel transistor. It is covered by a resist mask 8 that covers the P-type transistor portion of the peripheral circuit during arsenic ion implantation for region formation. As a result, these electrode regions are not subjected to the arsenic implantation described above and no N+ regions are formed. Thereafter, as shown in FIG. 8(a), the P+ region 12 of the transistor is formed by ion implantation. A SiO2 film is roughly formed as an interlayer insulating film 13, and a contact hole is formed on the other electrode of the transistor to be connected to the capacitor storage electrode.

Furthermore, polycide is formed as a material for bit line wiring,
This film is etched to form bit line wiring 18.

Next, as shown in FIG. 8(b), as an interlayer insulating film 17,
After forming the iOy film, a contact hole is opened on the electrode of the transistor to be connected to the storage electrode for the capacitor of the MOS type transistor.

After forming a polycrystalline silicon film as a material for the capacitor storage electrode, phosphorus is diffused and this film is etched to form the storage electrode 14. Furthermore, a capacitor insulating film 15 is formed to form an opposing cell plate electrode 16.
processed using a phosphorus-diffused polycrystalline silicon film. Finally, as shown in FIG. 6, after depositing and planarizing the interlayer insulating film 19, contact holes are opened using a known procedure, and the AQ-9i
Process the wiring using Alloy 20.

In the semiconductor memory device manufactured according to this example, the electrode region of the MO9 type transistor for the memory cell connected to the storage electrode for the capacitor and the bit line wiring is shown in FIG. 2(d).
Although the N+ region is not formed in the step shown in FIG. 1, the impurity is diffused from the contact portion between the capacitor storage electrode and the bit line wiring and the transistor electrode in the thermal process after forming the capacitor storage electrode, and the N+ region is formed.

Note that it is also possible to combine the embodiments of the first invention and the second invention. In other words, MO for memory cells
Of the electrodes of the type 9 transistor, at least the region of the electrode connected to the storage electrode for the capacitor is connected to the MO9 of the peripheral circuit.
N-type child channel transistor I) D structure n-
By protecting with a resist mask during P ion implantation to form the region and during arsenic ion implantation to form the N+ region of the peripheral circuit MO9 type N-channel transistor D D structure,
It is also possible to avoid forming the n- region and the N+ region in this region. In this case, the phosphorus concentration diffused from the capacitor storage electrode is on the order of IO"/cR3, whereas the phosphorus concentration in the n- region is on the order of 1018/ex', so there is no major influence.

<Effects of the Invention> As is clear from the above, in the first invention, in the ion implantation process of a low concentration impurity for forming a low concentration diffusion region of a source region or a drain region of a MOS transistor for a memory cell, Among the electrodes of the MO9 type transistor for the memory cell, at least the electrode connected to the storage electrode for the capacitor is covered by the mask λ, so that a low concentration diffusion region is formed in the electrode connected to the storage electrode for the capacitor. First, in a process after forming the capacitor storage electrode, impurities are diffused from the contact portion between the capacitor storage electrode and the memory cell MOS transistor to form a low concentration diffusion region,
The impurity concentration of the low concentration diffusion region of the MOS transistor for the memory cell can be optimized, and the MOS transistor for the memory cell
It is possible to suppress a decrease in the effective channel length of a type transistor and maintain its off-state characteristics at a good level.

Further, in the second invention, in the step of ion-implanting high-concentration impurities for forming a high-concentration diffusion region of a source region or a drain region of an MO9-type transistor for a memory cell, "1. Since at least the electrode connected to the storage electrode for the capacitor is covered by the mask, a high concentration diffusion region is not formed in the electrode connected to the storage electrode for the capacitor, and as a result, the electrode connected to the storage electrode for the capacitor is not formed. The diffusion region of the MOS type transistor for the memory cell connected to the storage electrode consists of impurities implanted in the ion implantation process of low concentration impurities and impurities diffused from the storage electrode for the capacitor, and there is no high concentration diffusion region. , the diffusion distance of impurities becomes short, the reduction in the effective channel group of the MOS type transistor for memory cell can be suppressed, and the off-state characteristics can be maintained at a good level.

[Brief explanation of drawings]

FIG. 1(a) shows an embodiment of the first invention (the first embodiment and the second embodiment).
Example) and Example of the second invention (Third Example and Fourth Example)
FIG. 1(b) is a cross-sectional structural diagram of an element formed up to the gate electrode of a memory cell transistor and peripheral circuit transistor by a known procedure in the second embodiment of the present invention, and FIG. 1(a) Figure 2 (a), (b), which shows the state where N- ions are implanted from the state of
(c) and (d) are respectively 1st. Second. Figures illustrating ion implantation of transistors in the third and fourth embodiments; Figures 3(a) and (b) are diagrams showing steps after ion implantation in the first embodiment; Figure 4 is the diagram for the first embodiment. and third
FIG. 5 (a) is a completed diagram of the semiconductor memory device in the example.
), (b) are diagrams showing the process after ion implantation in the second embodiment, FIG. 6 is a completed diagram of the semiconductor memory element in the second and fourth embodiments, and FIGS. 7(a), (b) )
8(a) and 8(b) are diagrams showing the steps after ion implantation in the fourth embodiment, and FIG. 9 shows the process after ion implantation in the third embodiment. FIG. 1O is a cross-sectional view of a stacked memory cell in which a contact is formed between a transistor and a transistor. 1... Element isolation region, 2... P well, 3... N
well, 45.6... gate electrode, 7... gate insulating film, 8... resist mask, 9... n- region, 10
...Zide wall insulating film, 11...N+ region 12
...P+ region, 13.17.19... interlayer insulating film,
! 4... Storage single pole, 15... Capacitor insulating film, 16... Opposite cell plate ta pole, 18... Bit line wiring, 20... Al-8i alloy.

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor memory element having a plurality of memory cells each including a MOS transistor formed on the surface of a semiconductor substrate and a capacitor formed on the surface of the semiconductor substrate, the method comprising: In the ion implantation process of low concentration impurities for forming the low concentration diffusion region of the source region or the drain region, at least the electrode of the MOS transistor connected to the capacitor is covered with a mask to form the low concentration diffusion region of the source region or the drain region. A method for manufacturing a semiconductor memory device, characterized in that ion implantation of concentrated impurities is not performed. (2) A method for manufacturing a semiconductor memory element having a plurality of memory cells each including a MOS transistor formed on the surface of a semiconductor substrate and a capacitor formed on the surface of the semiconductor substrate, the method comprising: In the step of ion-implanting high-concentration impurities to form a high-concentration diffusion region in the source region or drain region, at least the electrode connected to the capacitor among the electrodes of the MOS transistor is covered with a mask to form the high-concentration diffusion region in the high-concentration region. A method for manufacturing a semiconductor memory device, characterized in that ion implantation of concentrated impurities is not performed.