JPH0324895A - Clock generation circuit for video signal - Google Patents

Abstract

PURPOSE:To obtain a clock synchronized with a horizontal synchronizing signal by setting the oscillation output of a crystal oscillator as a clock signal by applying level adjustment with a saw-tooth wave AGC voltage synchronized with a pulse outputted from a gate circuit, waveform arrangement, and stabilization and/or frequency conversion. CONSTITUTION:The clock oscillating at the crystal oscillator 8 is inputted to a gain adjusting amplifier 10 via a buffer amplifier 9. The oscillation clock of the crystal oscillator 8 is attenuated with the lapse of time, however, since its gain is adjusted with a sawtooth wave voltage (AGC voltage synchronizing with an L pulse) outputted from a horizontal oscillation circuit 2 at the gain adjusting amplifier 10, the level of the oscillation clock can be kept at a constant value. The oscillation clock obtained in such way is waveform-arranged to a rectangular wave at a waveform arranging circuit 11, and after that, it is inputted to a PLL circuit 18 via a frequency division circuit 12, and is stabilized and frequency-converted at need at the circuit, then, it is outputted from a clock output terminal 17. Thereby, the clock can be synchronized with the horizontal synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that generates a clock used in video signal processing.

[Conventional technology]

For example, converting a video signal from an analog signal to a digital signal {t
The A/D converter requires a sampling clock for the video signal. Furthermore, since high-definition video signals do not have bursts, it is necessary to incorporate the burst clock when recording onto tape. These clocks must be synchronized with the horizontal synchronization signal. (Problem to be Solved by the Invention) Conventionally, a clock generation circuit was configured using a coil and a capacitor or a resistor and a capacitor to synchronize with the horizontal synchronization signal. There were problems in terms of temperature coefficient (fluctuation) and temperature coefficient.

The present invention has been made in view of these points, and an object thereof is to provide a clock generation circuit that can obtain a stable clock.

[Means to solve the problem]

To this end, the present invention provides a horizontal oscillation circuit that is reset by a horizontal synchronization signal, a one-shot multi that receives an output from the horizontal oscillation circuit and is reset by the horizontal synchronization signal, and an output signal from the one-shot multi. A gate circuit that generates a synchronization signal from the gate circuit, a crystal oscillation element that starts oscillation at the same time as it is reset each time it receives a pulse output from the gate circuit as a trigger, and a crystal oscillation element that synchronizes the oscillation output of the crystal oscillation element with the pulse. a gain adjustment circuit that adjusts the level using a sawtooth wave AGC voltage, a waveform shaping circuit that shapes the output from the gain adjustment circuit, and a clock signal by stabilizing and/or converting the frequency of the output of the waveform shaping circuit. I was wary of the PLL circuit.

In this invention, the pulse output from the gate circuit can be used for horizontal counting.

〔Example〕

Examples of the present invention will be described below. FIG. 1 is a diagram showing a circuit of one embodiment. 2 is a synchronization signal input terminal to which a horizontal synchronization signal is applied, and 2 is an AFC horizontal oscillation circuit. This horizontal oscillation circuit 2 generates a free-run oscillation of a pseudo synchronization signal by itself, but when a synchronization signal is applied to the input terminal 1, it generates a horizontal synchronization signal synchronized with the synchronization signal. Reference numeral 3 denotes a one-shot multi to which the pseudo synchronization signal from the horizontal oscillation circuit 2 is input as a trigger. This one shot multi 3
The output pulse width of is determined by resistor R1 and capacitor C1. 4 is a NAND gate which receives the Q output of the one-shot multi 3, a signal passed through a differentiating circuit consisting of a resistor R2 and a capacitor C2, and the inverted Q output of the multi 3. 5 is an inverter, Q1 is a transistor that receives the output of the inverter 5, Q2 is a transistor that receives the output of the transistor Ql, and Q3 is a transistor that receives the output of the NAND game 14. 6 is an inverter, and 7 is a horizontal synchronization signal output terminal. Reference numeral 8 denotes a crystal oscillation element, to which a power supply voltage is applied by the switching action of the transistor Q3. Furthermore, one of the resistors R3 and R4 on the output side of this crystal oscillation element 8, R4, is short-circuited by a transistor Q2. 9 is a buffer amplifier, and lO is a gain adjustment amplifier having a tuning circuit whose center frequency is set to the oscillation frequency of the crystal oscillation element 8. This gain adjustment circuit 10 receives a horizontal sawtooth wave from the horizontal oscillation circuit 2 and periodically changes its gain. 11 is a waveform shaping circuit consisting of a zero clock comparator, 12 is a frequency dividing circuit, 13 is an exclusive OR gate that functions as a PC (phase comparator), 14 is a low-pass filter, 15 is a voltage-controlled oscillation circuit, and 16 is a In the frequency dividing circuit, l7 is a clock output terminal. The frequency dividing circuit 12, exclusive OR gate 13, low pass filter 14, oscillation circuit 15, and frequency dividing circuit 16 are
It constitutes the LL circuit l8.

Now, when a horizontal synchronization signal is applied to input terminal 1 (a video signal is input), horizontal oscillation circuit 2 is reset by this horizontal synchronization signal, so a signal synchronized with this horizontal synchronization signal is generated. Output to one-shot multi 3 as a trigger signal.

Note that this one-shot multi 3 is also reset at the same time by the horizontal synchronization signal. Therefore, the L pulse synchronized at this reset is output to the output side of the NAND gate 4,
In synchronization with this, transistors Ql-Q3 are turned on. As a result, the crystal oscillation element 8 is periodically triggered (re-triggered) by applying a voltage at this timing, and starts oscillating at a unique frequency every time it is triggered. Further, at this trigger time, the resistor R4 is short-circuited by turning on the transistor Q2, so that the crystal oscillation element 8 is reset and the input voltage of the buffer amplifier 9 becomes zero.

Further, the L pulse is inverted by an inverter 6 and outputted to the output terminal 7 as an H pulse for horizontal counting.

When the above-mentioned L pulse disappears, the transistor Q2 is turned off, so that the cross signal oscillated by the crystal oscillation element 8 is inputted to the gain adjustment amplifier 1O via the buffer amplifier 9. The oscillation clock of the crystal oscillation element 8 attenuates over time, but in this gain adjustment amplifier 10, its gain is adjusted by the sawtooth wave voltage (AGC voltage synchronized with the above-mentioned L pulse) output from the horizontal oscillation circuit 2. Therefore, the level of the oscillation clock is held at a constant value. The oscillation clock obtained in this way is waveform-shaped into a rectangular wave in the waveform shaping circuit 11, and then the frequency dividing circuit l
2 to the PLL circuit 18, where it is stabilized and, if necessary, frequency converted (multiplied) and output from the clock output terminal 17. Frequency conversion is performed by changing the frequency division ratio of the frequency divider circuit 12 or l6.

As described above, since the crystal element 8 is triggered by timing synchronized with the horizontal synchronizing signal, the clock frequency is stable and synchronized with the horizontal synchronizing signal. Furthermore, even if there is a slight phase shift between the clocks, the PLL circuit 18 averages it out.

In addition, if for some reason the horizontal synchronization signal is not applied to the input terminal l temporarily (there is no video signal),
Since the horizontal oscillation circuit 2 free-runs the pseudo horizontal synchronization signal, the L pulse based on this signal is sent to the NAND gate 4.
The crystal oscillation element 8 operates. However, since the video signal is already missing at this time, the generation cross is not used. However, output terminal 7
Since the H pulse synchronized with the pseudo-horizontal synchronization signal is output, the counter counts normally and prevents the tape count of the VTR and the address specification of the frame memory provided on the output side of the A/D converter from going out of order. Ru. [Effects of the Invention] As described above, according to the present invention, a clock synchronized with a horizontal synchronization signal can be obtained. This clock is stable and unaffected by temperature.

Therefore, it is extremely useful as a clock for video signal processing such as color synchronization burst signals, A/D conversion sampling, and the like.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing chart. 1...Horizontal synchronization signal input terminal, 2...AFC horizontal oscillation, 3...One shot soto multi, 4...NAND gate, 5, 6...Inverter, 7...Horizontal synchronization signal output terminal , 8... crystal oscillation element, . 9...
Banfa amplifier, 10... Gain adjustment amplifier, 11.
... Waveform shaping circuit, 12... Frequency dividing circuit, 13... Exclusive OR gate, 14... Low pass filter, 15... Voltage controlled oscillation circuit, 16... Frequency dividing circuit, 17.・・Closet output terminal, 18...P L
L circuit.

Claims (2)

[Claims] (1) A horizontal oscillation circuit that is reset by a horizontal synchronization signal, a one-shot multi that receives the output from the horizontal oscillation circuit and is reset by the horizontal synchronization signal, and a synchronization signal from the output signal from the one-shot multi. a crystal oscillation element that is reset and starts oscillating every time it receives a pulse output from the gate circuit as a trigger, and a sawtooth waveform that synchronizes the oscillation output of the crystal oscillation element with the pulse. A gain adjustment circuit that adjusts the level with an AGC voltage, a waveform shaping circuit that shapes the waveform of the output from the gain adjustment circuit, and a PLL circuit that stabilizes and/or converts the frequency of the output of the waveform shaping circuit to generate a clock signal. A video signal clock generation circuit comprising: (2) The video signal clock generation circuit according to claim 1, wherein the pulse output from the gate circuit is used for horizontal counting.