JPH03248641A - Quadrature modulator - Google Patents

Abstract

PURPOSE:To suppress a phase error in a modulation output and fluctuation of amplitude by selectively operating 4 analog switches receiving 4 kinds of quadrature signals with a signal of a shift register driven by a clock having a period four times that of a carrier. CONSTITUTION:Four signals I-Q, I+Q, -I+Q, -I-Q led in advance from an in-phase input I and a quadrature input Q are respectively inputted to analog switches 2A-2D. On the other hand, when a level of a reset terminal 7 is logical 0 in a shift register 4, outputs of each DFF are all 0 and the analog switches 2A-2D are all opened. When a level of the reset terminal 7 is logical 1, the output of the shift register 4 is exclusively logical 1 in the order of a-d from the leading of the synchronizing clock being four times the period of the carrier. Thus, the analog switches 2A-2D are sequentially conductive exclusively accordingly and a desired quadrature signal is obtained from an output terminal 3. Thus, unbalance of an output of the modulation signal is not caused due to the overlapped modulation wave having taken place in a conventional modulator.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a quadrature modulator for performing quadrature phase modulation.

[Conventional technology]

Generally, as shown in FIG. 3, a quadrature modulator inputs an in-phase component I signal and a quadrature component Q component as modulating waves, and uses carrier waves A and B that are out of phase by 90 degrees. Double balanced mixers 11A and IIB perform modulation, respectively, and adder 12 adds them to obtain a phase modulated output signal. Carrier waves A and B are obtained by carrier signal C as it is and by phase shifting it by 90° phase shifter 13.

Here, the phase of the output signal is O
'', then φt = -jan -'Q/ I (I > O
)φ, =x −jan −′Q/ I (
I<0) However, -z/2<jan-'<π/2.

As the simplest circuit to realize this principle, the one shown in FIG. 4 has been adopted. In this circuit, considering that it is difficult to configure a 90° phase shifter with high precision, a clock frequency of four times the carrier wave is divided by a frequency divider 25 consisting of two D flip-flops 26A and 26B. , carrier waves A and B having a 90° phase difference are obtained. In addition, the double-balanced mixer has a switching type analog switch 22A, 22
The input signal and its inverted signals I, -1, Q, and -Q are inputted to the input terminals 21A, 21B, 21C, and 21D of these analog switches 22A and 22B, respectively. And analog switch 22A.

22B with carrier waves A and B, and add the selected signals with the adder 23, the output terminal 24
The modulated output is obtained. In addition, FIG. 5 is a signal waveform diagram of each part.

[Problem to be solved by the invention]

In the circuit shown in FIG. 4 described above, when the rise times of the outputs of the two D flip-flops 26A and 26B forming the frequency divider 25 are different, the carrier wave A is used.

The duty ratio of B will deviate from 50%.

For this reason, a shift occurs in the switching timing of the analog switches 22A and 22B, and the signals input from each analog switch to the adder 23 are instantaneously fluctuated. This causes an error in the phase of the modulated output output from the adder 23, as well as adverse effects such as fluctuations in amplitude. This phenomenon becomes more pronounced as the frequency of the carrier wave becomes higher.

Particularly, this becomes a serious problem when the frequency of the input clock is close to the operating limit of the D flip-flop.

An object of the present invention is to provide a quadrature modulator that prevents such phase errors and amplitude fluctuations in modulated output.

[Means to solve the problem]

The quadrature modulator of the present invention includes an input terminal into which four types of orthogonal signals are input, four analog switches respectively connected to these input terminals, one output terminal connected to these analog switches, and a carrier wave. Driven by a clock input with a period four times that of the carrier wave,
A shift register that outputs different signals is provided, and the four analog switches are selectively operated by the four types of signals from this shift register.

Here, the shift register is configured by connecting four D flip-flops in series and outputting the output from each D flip-flop as four types of signals of the shift register.

Furthermore, four D flip-flops are formed as one integrated circuit.

[Effect]

According to the present invention, the four analog switches are selectively operated by the output signal of the shift register to output four types of orthogonal signals, thereby preventing different orthogonal signals from overlapping and adjusting the phase in the modulated output. Suppress errors and amplitude fluctuations.

Further, by integrating the D flip-flops constituting the shift register, deviations in their operation can be suppressed, and phase errors and amplitude fluctuations can be more effectively prevented.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, IA-ID are four input terminals into which signals to be modulated are input, and analog switches 2A-2D are connected to each input terminal IA-ID, respectively. Further, these analog switches 2A to 2D are connected to one output terminal 3.

On the other hand, 4 is a shift register, which is composed of four D flip-flops 5A to 5D and one AND gate 5a. A clock signal is inputted to the shift register 4 from a clock terminal 6, and a reset signal is inputted to a reset terminal 7. The outputs a to d of the D flip-flops 5A to 5D are connected to the analog switches 2A to 2D, respectively, and the analog switches are turned on and off by the outputs of the D flip-flops.

According to this configuration, the input signals are four signals derived in advance from an in-phase human input I signal and a quadrature human input Q signal: an I-Q signal, an I+Q signal, and a -I+Q signal.

I-Q signals are input to input terminals IA to ID, respectively.

On the other hand, in shift register 4, when the reset terminal is "0", the outputs of each D flip-flop are all "0".
”, and analog switches 2A to 2D are all opened accordingly. When the reset terminal becomes “1”, a, b, c are sequentially opened from the first clock rise.
, d, the output of the shift register 4 is exclusively “°1”
become. In response to this, the analog switches 2A to 2D are sequentially and exclusively turned on, and the output terminal 3 receives the I-Q signal and the I+ signal.
The values of the Q signal, -1+Q signal, and -I-Q signal are output,
A desired orthogonal modulated signal will be obtained.

Here, in the present invention, since the D flip-flops 5A to 5D constituting the analog switch 4 are all configured in the same manner using an integrated circuit or the like, the four analog switches 2A to
The opening/closing timing, duty ratio, etc. of the 2D are almost the same in principle.

In addition, even if there is a slight timing difference, each analog switch 2A to 2D is configured to be selectively operated and a modulated signal is output from the selected analog switch, so there is no overlap of modulated waves as in the conventional case. Therefore, there is no imbalance in the modulated signal output.

〔Effect of the invention〕

As explained above, the present invention obtains a modulated output by selectively operating four analog switches provided corresponding to four types of orthogonal signals using signals from a shift register, so that different orthogonal signals do not overlap. can be prevented, and phase errors and amplitude fluctuations in the modulated output can be suppressed. In addition, by integrating the D flip-flops that make up the shift register, it is possible to suppress deviations in their operation.
Phase errors and amplitude fluctuations can be more effectively prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a conceptual configuration diagram of a quadrature modulator, FIG. 4 is a block diagram of a conventional example, and FIG. 5 is a signal waveform diagram of each part in FIG. 4. IA to ID...Input terminal, 2A to 2D...Analog switch, 3...Output terminal, 4...Shift register, 5A to 5D...D flip-flop, 6...Clock terminal, 7 ...Reset terminal, 11A, 11B...
・Double balanced mixer, 12...adder, 13・
...90° phase shifter, 21A to 21D...input terminal, 2
2A, 22B... Analog switch, 23... Adder, 24... Output terminal, 25... Frequency divider, 25A,
25B...D flip-flop. Figure 3 Figure 1A Figure 4

Claims (1)

[Claims] An input terminal into which one or four types of orthogonal signals are input, four analog switches connected to these input terminals, one output terminal connected to these analog switches, and a carrier wave. and a shift register that is driven by a clock that is input at a cycle four times as long as A quadrature modulator characterized in that it is configured to selectively operate each of the modulators. 2. The shift register is constructed by connecting four D flip-flops in series and outputting the output from each D flip-flop as four types of signals of the shift register, as set forth in claim 1. Quadrature modulator. 3. The quadrature modulator according to claim 2, wherein three or four D flip-flops are formed as one integrated circuit.